JP3516664B2 - Reference clock generator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference clock generator, and more particularly to a reference clock generator in a radio base station which uses a digital PLL circuit and is synchronized with a reference clock from an upper station. The voltage value set in the oscillator is stored in a storage unit such as a memory, which shortens the time required for the frequency pull-in process after the power supply of the wireless base station device is momentarily cut off by a lightning strike or the like. The present invention relates to a reference clock generator.

The present invention is described in more detail in FIG.
When the phase difference P becomes 0 for a certain period of time, the arithmetic unit 10
5 is judged to be the phase synchronization process, and the digital input value V at that time
The digital input value storage unit 106 stores D. After that, when an external factor such as a lightning strike causes a failure in the power supply generation device 109 and the power supply VBTS supplied to the reference clock generation device 100 is momentarily cut off, the calculation unit 105 causes the digital input value storage unit 106 to operate. By reading the digital input value VD and setting it in the D / A converter 107, the voltage value before the power interruption can be set in the voltage controlled oscillator 108. Therefore, after the power interruption, the reference clock of the same frequency as before the power interruption. fo can be supplied and the phase synchronization process can be maintained.

[0003]

2. Description of the Related Art FIG. 11 shows a block configuration of a first conventional example of this type of reference clock generator.

Reference clock generator 10 shown in FIG.
0'is different from the configuration of the present invention shown in FIG. 1 in that the digital input value storage unit 106 is not provided.

In the first conventional reference clock generator 100 'shown in FIG. 11, the same operation as the reference clock generator 100 according to the present invention shown in FIG. 1 is performed from the frequency pulling process to the steady process. To do.

When the power supply VBTS of the power supply generator 109 is momentarily cut off due to a lightning strike or the like in the state where the reference clock generator 100 'is in the phase synchronization process, the power supply of the reference clock generator 100' is cut off. , Calculation unit 105
Then, the power supplied to the D / A converter 107 is also cut off.

Then, when the power supply generator 109 is restored, the power supply VBTS is supplied again to the reference clock generator 100 ', so that the arithmetic unit 105 and the D / A converter 107 are also supplied with power again. Then, since the D / A converter 107 is in the initial state, the analog output is V
Adef, and the voltage-controlled oscillator 108 operates at that voltage value, so that the frequencies of the reference clock fr from the upper station and the radio device reference clock fo are different, and the frequency pull-in process starts again. This process is shown in FIG.

When the frequency pull-in state is restored again after a momentary power failure, the reference clock generator 100 'cannot supply the reference clock synchronized with the upper station to the radio base station until the phase synchronization process is started. .

An example of a conventional technique for a PLL circuit similar to the present invention is disclosed in Japanese Patent Laid-Open No. 04-107011, which is cited as a second conventional example, and is obtained from a phase comparator through a filter. Voltage is stored in the memory, and when the detection circuit detects an input signal disconnection, the switching circuit switches to the voltage stored in the memory to operate the voltage-controlled oscillator with the voltage stored in the memory. As a result, the output frequency can be accurately maintained at the required frequency.

[0010]

However, the above first and second conventional examples have the following drawbacks.

First, in the first conventional example, since the voltage-controlled oscillator cannot be driven to oscillate with the voltage value before the power-off after the power-off, the reference clock from the upper station and the clock of the voltage-controlled oscillator are The frequencies are different, and as a result, the frequency pulling state occurs.

Further, in the second conventional example, when the power supply is interrupted, the input signal is not interrupted, so that the detection circuit does not perform the operation of switching to the voltage stored in the memory. However, since the voltage value set in the voltage-controlled oscillator returns to the initial state, the voltage-controlled oscillator cannot be operated with the voltage before the power is cut off.

A phase-locked loop protection circuit disclosed in Japanese Patent Laid-Open No. 63-228821, which has the same structure as the second conventional example and has the same problem, is disclosed in Japanese Laid-Open Patent Publication No. HEI 5-1993.
A PLL circuit and the like disclosed in Japanese Patent Publication No. 90961 are known.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to provide a novel reference clock generator capable of eliminating the above-mentioned drawbacks inherent in the conventional technology. To do.

[0015]

In order to achieve the above object, a reference clock generator according to the present invention is provided with a first frequency divider for inputting a reference clock from an upper station and converting it to a first phase comparison clock. And a second frequency divider for inputting a reference clock of the radio base station device and converting it into a second phase comparison clock, and a first phase comparison clock for inputting a reset signal to the second frequency divider. A reset circuit for outputting, a sampling clock generating means for generating a sampling clock, the first and second phase comparison clocks and the sampling clock are input, the first and second phase differences are detected, and the phase differences are output. Phase comparing means, computing means for inputting the phase difference to control the digital input value, digital input value storing means for storing the digital input value, and analog for inputting the digital input. A D / A converter for converting into a power, a voltage control type oscillating means for inputting the analog output and outputting the reference clock of the radio base station apparatus, and a power supply voltage generating apparatus for supplying a power supply voltage to the respective means It is equipped with.

The digital input value storage means includes the first
And the digital input value in the phase synchronization process in which the phase difference of the second phase comparison clock is 0 continuously for a certain period.

When the output of the power supply voltage generator is restored after being cut off, the arithmetic means reads the digital input value from the digital input value storage means, and the D
The / A converter converts the analog value and supplies the analog value to the voltage-controlled oscillation means to obtain a phase synchronization process without performing a frequency pull-in operation.

It is also possible to provide a digital input value reading means for periodically reading the digital input value set in the D / A converter and outputting the value to the arithmetic means.

A power supply monitoring means for inputting a power supply voltage from the power supply voltage generator and outputting a switching signal based on the level of the power supply voltage, and a power supply for supplying to the digital input value storage means are a backup power supply or the power supply voltage. It is also possible to provide a switch for switching to the power supply of the generator and a backup power supply circuit for inputting the power supply voltage of the power supply voltage generator and outputting a backup power supply.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described in detail with reference to the drawings for each preferred embodiment thereof.

[0021]

[First Embodiment] FIG. 1 is a block diagram showing a first embodiment according to the present invention.

[0022]

[Structure of First Embodiment] Referring to FIG. 1, a reference clock generator 100 includes a reference clock f from an upper station.
Frequency divider A for inputting r and converting it to a phase comparison clock frc
101, and a frequency divider B102 for inputting a reference clock fo of the wireless base station device and converting it to a phase comparison clock foc,
The reset circuit 110 that inputs the phase comparison clock frc and outputs the reset signal to the frequency divider B102, the sampling clock generator 103 that generates the sampling clock fs, the phase comparison clock frc, the phase comparison clock foc, and the sampling clock fs are input. A phase comparator 104 that detects the phase difference between the phase comparison clock frc and the phase comparison clock foc and outputs the phase difference P; and a calculation unit 105 that inputs the phase difference P and controls the digital input value VD.
Digital input value storage unit 1 for storing the digital input value VD
06 and digital input value VD are input and analog output VA
D / A converter 107 for converting to analog output V
A voltage-controlled oscillator 108 that inputs A and outputs a reference clock fo of the wireless base station is input, and the power supply VBTS generated by the power supply generator 109 is input.

The phase comparison unit 104 has a phase comparison clock f.
When the phase comparison clock foc is delayed with respect to rc, the value of the phase difference P is made negative, and when it is advanced, the value of the phase difference P is made positive.

The arithmetic unit 105 increases the digital input VD when the value of the input phase difference P is negative, and decreases the digital input VD when the value is positive.

The digital input value storage unit 106 includes the arithmetic unit 1
The output of No. 05, that is, the digital input VD of the D / A converter 107 is stored, and a nonvolatile memory such as a flash ROM is used, and the stored digital input value VD is not erased even when the power is cut off.

The D / A converter 107 increases the analog output VA when the digital input VD increases, and decreases the analog output VA when the digital input VD decreases.

The voltage controlled oscillator 108 outputs the reference clock fo of the radio base station apparatus having a frequency corresponding to the voltage value of the analog output VA, and when the analog output VA increases, the frequency of the reference clock fo increases. , The frequency of the reference clock fo becomes low.

The reset circuit 110 outputs a reset signal to the frequency divider B102 so that the phase comparison clock fr
The phase difference between c and the phase comparison clock foc is matched.

[0029]

[Operation of First Embodiment] Next, the operation of the first embodiment of the present invention will be described.

In the reference clock generator 100 according to the first embodiment of the present invention shown in FIG. 1, the reference clock fr from the upper station is converted into the phase comparison clock frc by the frequency divider A101, The reference clock fo of the radio base station apparatus is synchronized with the reference clock fr from the upper station by adjusting the phase of the phase comparison clock foc obtained by converting the reference clock fo of the radio base station apparatus by the frequency divider B102. It is supplied to the station equipment.

Here, an operation example of the reference clock generator 100 when the phase of the phase comparison clock foc is delayed with respect to the phase comparison clock frc will be described with reference to FIGS. 2 and 3.

In FIG. 2, for the phase comparison clock frc,
An example of the phase relationship between the phase comparison clock frc, the phase comparison clock foc, and the sampling clock fs when the phase of the phase comparison clock foc is delayed by 8 clocks of the sampling clock fs is shown. In the case of FIG. 2, since the phase comparison clock foc is delayed in phase with respect to the phase comparison clock frc, the phase difference comparison unit 104 outputs the negative phase difference P (−) to the calculation unit 105.

Since the negative phase difference P (-) is input to the arithmetic unit 105, the arithmetic unit 105 calculates the phase comparison clock fr.
It is determined that the phase comparison clock foc is delayed with respect to c, and the digital input value VD (+) obtained by increasing the value of the digital input value VD is output to the D / A converter 107.
The D / A converter 107 converts the input digital input value VD (+) into an analog value, and the voltage controlled oscillator 1
It outputs to 08.

At this time, since the analog input value VA also increases due to the increase in the digital input value VD, the radio device reference clock fo output from the voltage controlled oscillator 108.
Frequency becomes higher. Therefore, the phase comparison clock f
The cycle of oc becomes short. As a result, as shown in FIG. 3, the phase comparison clock foc and the phase comparison clock frc
2 becomes smaller than that in the case of FIG.

Next, with respect to the phase comparison clock frc,
An operation example of the reference clock generation device 100 when the phase of the phase comparison clock foc is advanced will be described with reference to FIGS. 4 and 5.

In FIG. 4, for the phase comparison clock frc,
An example of the phase relationship between the phase comparison clock frc, the phase comparison clock foc, and the sampling clock fs when the phase of the phase comparison clock foc is advanced by 8 clocks of the sampling clock fs is shown. In the case of FIG. 4, since the phase comparison clock foc leads the phase comparison clock frc in phase, the phase difference comparison unit 104 outputs the positive phase difference P (+) to the calculation unit 105.

Since the positive phase difference P (+) is input to the arithmetic unit 105, the arithmetic unit 105 calculates the phase comparison clock fr.
It is determined that the phase comparison clock foc is advanced with respect to c, and the digital input value VD (−) obtained by reducing the value of the digital input value VD is output to the D / A converter 107.
The D / A converter 107 converts the input digital input value VD (−) into an analog value, and the voltage controlled oscillator 1
It outputs to 08.

At this time, since the digital input value VD is reduced and the analog input value VA is also reduced, the wireless device reference clock fo output from the voltage controlled oscillator 108 is output.
The frequency becomes low. Therefore, the phase comparison clock f
The cycle of oc becomes longer. As a result, as shown in FIG. 5, the phase comparison clock foc and the phase comparison clock frc
4 becomes smaller than that in the case of FIG.

Reference clock generator 100 shown in FIG.
Then, the operations described with reference to FIGS. 2 to 5 are continuously performed, and the phase of the phase comparison clock frc is matched with the phase of the phase comparison clock frc, so that the frequencies of the phase comparison clock frc and the phase comparison clock foc become equal to each other. The reference clock fo of the radio base station device is used as the reference clock fr from the upper station.
Will synchronize.

The reference clock generator 10 is continuously shown in FIG.
Phase comparison clock frc when 0 is operating,
An example of the relationship among the phase comparison clock foc, the phase difference P, and the analog output VA is shown.

Referring to FIG. 6, when the phase difference P is negative, the arithmetic unit 105 increases the digital input value VD, and therefore the analog output VA. When the value of the analog output VA increases, the frequency of the reference clock fo of the wireless base station device also increases, and as a result, the phase difference P also increases.

If the phase difference P is positive, the computing unit 1
In 05, since the digital input value VD is decreased, the value of the analog output VA is also decreased. When the value of the analog output VA decreases, the frequency of the reference clock fo of the wireless base station device also decreases, and as a result, the phase difference P also decreases.

If this operation is continuously performed, the phase difference between the phase comparison clock frc and the phase comparison clock foc will slightly change in the vicinity of 0. As a result, the reference clock fo of the wireless base station device is in a state of being synchronized with the reference clock fr from the upper station.

Here, the reference clock f of the radio base station apparatus
“Frequency pulling process” until the frequency of o and the frequency of the reference clock fr from the upper station match, and “phase synchronization process” when the phase difference between the phase comparison clock frc and the phase comparison clock foc is 0 for a certain period. Call.

FIG. 7 shows a general example in which the reference clock generator changes from the frequency pull-in process to the phase synchronization process after the power is turned on, which will be described below.

Referring to FIG. 7, it is assumed that the digital input in the initial state after power-on is VDdef and the analog output is AVdef. In addition, the digital input during the phase synchronization process is VDLoc.
k, analog output is VALock. After the power is turned on, the reset circuit 110 outputs a reset signal to the frequency divider B102 to match the phase of the input phase comparison clock frc with the phase of the phase comparison clock foc.

Therefore, the phase difference P after the power is turned on becomes zero. Further, the D / A converter 107 sets the initial value VAdef
Is output to the voltage controlled oscillator 108. Therefore, the voltage controlled oscillator 108 outputs the reference clock fo of the wireless base station device corresponding to VAdef.

In this state, since the frequency of the reference clock fr from the higher station and the frequency of the reference clock fo of the radio base station apparatus do not match, the phase of the phase comparison clock frc and the phase of the phase comparison clock foc deviate, In the frequency pull-in process, the reference clock generator 100 is shown in FIG.
The operation shown in (1) is performed to operate so that the phase difference P becomes zero.

In a general PLL circuit, in the frequency pull-in process, as shown in FIG. 7, the amplitude is centered around the phase difference 0, and the phase difference P gradually decreases, and eventually converges to near 0. To work. Here, when the phase difference P becomes 0 continuously for a certain period of time, the calculation unit 105
The digital input value at that time is determined to be VDLock, and the value of VDLock is stored in the digital input value storage unit 106.

FIG. 8 shows an example of the relationship between the phase difference P and the analog output VA when the power source VBTS of the power source generator 109 is momentarily cut off due to a lightning strike or the like during the phase synchronization process, and its operation is shown below. .

When the power supply generator 109 becomes abnormal due to a lightning strike and the power supply VBTS is cut off, the power supply to the arithmetic unit 105 and the D / A converter 107 is also cut off. Then, when the power generator 109 is restored, the power VBTS is supplied to the inside of the reference clock generator 100 again.

After power is supplied, the reset circuit 110 outputs a reset signal to the frequency divider B102, and the phase of the input phase comparison clock frc and the phase comparison clock foc.
Match the phases of. Therefore, the phase difference P after power-on becomes 0.

Further, the arithmetic unit 105, when starting the operation, outputs the digital input value VDLock from the digital input value storage unit 106.
Is read and output to the D / A converter 107.

D / when the digital input value VDLock is input
The A converter 107 converts the value into an analog value,
The analog output value VALock is output to the voltage controlled oscillator 108.

The voltage-controlled oscillator 108, to which the analog output value VALock is input, can supply the frequency of the radio device reference clock fo before power-off to the radio base station device. As a result, the frequency of the reference clock fr from the upper station and the frequency of the radio device reference clock fo coincide with each other, so that the phase synchronization process is performed without performing the frequency pull-in operation.

[0056]

Second Embodiment Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 9 is a block diagram showing a second embodiment according to the present invention.

[0058]

[Structure of the Second Embodiment] Referring to FIG. 9, the second embodiment according to the present invention shown in FIG. 9 is compared with the first embodiment shown in FIG. The difference is that the digital input value reading unit 111 is provided. The digital input value reading unit 111 periodically reads the digital input value set in the D / A converter 107 and outputs the value to the arithmetic unit 105.

[0059]

Operation of the Second Embodiment In the reference clock generator 100 of FIG. 9, the same operation as the reference clock generator of FIG. 1 is performed from the frequency pulling process to the phase synchronization process. When the power supply VBTS is turned off in the phase synchronization process in the reference clock generation device 100 of FIG. 9, the power supply of the reference clock generation device 100 is turned off, and the arithmetic unit 105 and the D / A converter 107 are connected. The power supplied to is also cut off. Then, the power generator 109
When the power supply is restored, the power supply VBTS is used as the reference clock generator 1
00 again.

After the power supply VBTS is supplied, the reset circuit 1
Reference numeral 10 outputs a reset signal to the frequency divider B102 to match the phase of the input phase comparison clock frc with the phase of the phase comparison clock foc. Therefore, the phase difference P after power-on becomes 0.

Further, the arithmetic unit 105, when starting the operation, outputs the digital input value VDLock from the digital input value storage unit 106.
Is read and output to the D / A converter 107. The calculation unit 105 includes a digital input value input from the digital input value reading unit 111 and a digital input value storage unit 106.
The digital input value VDLock read from is compared, and the digital input value VDLock is output to the D / A converter 107 until the same value is obtained.

D / when the digital input value VDLock is input
The A converter 107 converts the value into an analog value,
The analog output value VALock is output to the voltage controlled oscillator 108.

The voltage-controlled oscillator 108, to which the analog output value VALock is input, can supply the frequency of the wireless device reference clock fo before power-off to the wireless base station device. As a result, the frequency of the reference clock fr from the upper station and the frequency of the radio device reference clock fo coincide with each other, so that the phase synchronization process is performed without performing the frequency pull-in operation.

According to the second embodiment, the arithmetic unit 105 outputs the digital input value VDLock before the D / A converter 107 is activated, so that the digital input value VDLock can be normally processed. It is possible to prevent that the analog output becomes the initial value VAdef without being set to 107, and the voltage-controlled oscillator 108 operates at that voltage value.

[0065]

Third Embodiment Next, a third embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 10 is a block diagram showing the third embodiment according to the present invention.

[0067]

[Configuration of Third Embodiment] Referring to FIG.
The third embodiment shown in FIG. 0 is the first embodiment shown in FIG.
Compared with the embodiment of FIG.
A point at which a volatile memory is used and a power supply VBTS are input and a switching signal is output, a switch 114 for switching the power supply to the digital input value storage unit 112 to a backup power supply or a power supply VBTS,
And a backup power supply circuit 115 for inputting the power supply VBTS and outputting a backup power supply.

The digital input value storage unit 112 includes a RAM
When the power supply is stopped, the stored digital input value VD is erased.

The power supply monitor 113 receives the input power supply VB.
The voltage level of TS is monitored, and if the voltage level exceeds the threshold value VTH, the voltage level of the switching signal is set to a high potential and output, and the voltage level is set to the threshold value VTH.
When the voltage is below TH, the voltage level of the switching signal is set to a low potential and output. Here, the threshold value VTH is VB at which the operation of the digital input value storage unit 112 is stopped.
It is set a little higher than the voltage level of TS.

The switch 114 switches the power source of the digital input value storage unit 112 to the power source VBTS when the voltage level of the input switching signal is high potential, and when the voltage level of the input switching signal is low potential. First, the power supply of the digital input value storage unit 112 is switched to the backup power supply.

The backup power supply circuit 115 has a large-capacity capacitor internally stored by the power supply VBTS,
The backup power supply is output to the switch 114.

[0072]

[Operation of Third Embodiment] Next, the operation of the third embodiment of the present invention will be described.

The reference clock generator 100 of FIG. 10 operates in the same manner as the reference clock generator shown in FIG. 1 from the frequency pulling process to the phase synchronization process.
In the reference clock generator 100 of FIG. 10, the operation when the power supply VBTS is momentarily cut off in the phase synchronization process will be described below.

Before a momentary power failure, the power source VB of the power generator is
Since the voltage level of TS exceeds the threshold value VTH, the power supply monitoring unit 113 sets the voltage level of the switching signal to a high potential and outputs it.

The switch 114, to which the switching signal with the high voltage level is input, has the digital input value storage section 112.
Power source VBT generated by the power source generator 109
Switch to S. If a failure occurs in the power supply generator 109 from this state and the voltage level of the power supply VBTS falls below the threshold value VTH, the power supply monitoring unit 113 sets the voltage level of the switching signal to a low potential and outputs it. A switch 1 to which a switching signal with a low voltage level is input
14 switches the power source of the digital input value storage unit 112 to the backup power source.

After the switch 114 is switched, the backup power supply circuit 115 causes the digital input value storage section 112 to operate.
Is supplied with backup power.

As described above, since the digital input value storage section 112 can be supplied with a power source of a voltage level capable of operating even when the power supply is interrupted, the digital input stored in the memory is not erased.

According to the third embodiment, since the operation of the digital input value storage unit 112 is maintained before and after the power interruption, even if a volatile memory is used for the digital input value storage unit 112, The digital input value is not erased.
Therefore, since the arithmetic unit 105 can set the digital input VDLock in the D / A converter 107 during the phase synchronization process after the power supply is cut off, the phase synchronization state can be maintained even after the power supply is instantaneously cut off.

[0079]

The present invention is constructed and operates as described above, and according to the present invention, the following effects can be obtained.

The reference clock generator 100, which supplies the reference clock fo of the radio base station apparatus synchronized with the reference clock fr from the upper station to the radio base station, does not go into the frequency pull-in process again after a momentary power failure. .

The reason is that when the phase synchronization process is started, the arithmetic unit 105 stores the digital input value VDLock at that time in the digital input value storage unit 106 and is stored in the digital input value storage unit 106 after a momentary power failure. By reading the digital input value VDLock and outputting it to the D / A converter 107, the analog output VDLock during the phase synchronization process can be set in the voltage controlled oscillator 108, and the radio base station of the same frequency as before the power is turned off. This is because the reference clock fo of the device can be supplied to the radio base station.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a first embodiment of a reference clock generator according to the present invention.

FIG. 2 shows a phase comparison clock foc as a phase comparison clock f.
It is a figure which shows the example of the phase relationship in case the phase of 8 clocks of the sampling clock fs is lagging behind rc.

FIG. 3 is a diagram showing an example of a phase relationship after controlling the voltage controlled oscillator from the state of FIG.

FIG. 4 shows the phase comparison clock foc as the phase comparison clock f.
It is a figure which shows the example of a phase relationship in case the phase of 8 sampling clocks fs has advanced with respect to rc.

5 is a diagram showing an example of a phase relationship after controlling the voltage controlled oscillator from the state of FIG.

FIG. 6 is a diagram showing a relationship of a phase difference between a phase comparison clock and an analog output during operation of the digital PLL circuit.

FIG. 7 is a diagram showing a phase difference and an analog output from a frequency pulling process to a phase synchronization process.

FIG. 8 is a diagram showing a phase difference and an analog output at the time of instantaneous power failure.

FIG. 9 is a block configuration diagram showing a second embodiment of a reference clock generation device according to the present invention.

FIG. 10 is a block configuration diagram showing a third embodiment of a reference clock generation device according to the present invention.

FIG. 11 is a block diagram of a conventional reference clock generator.

FIG. 12 is a diagram showing a phase difference and an analog output when the power supply of the conventional reference clock generator is interrupted.

[Explanation of symbols]

100, 100 '... Reference clock generator 101, 102 ... Divider 103 ... Sampling clock generator 104 ... Phase difference comparator 105 ... Operation unit 106, 112 ... Digital input value storage unit 107 ... D / A converter 108 ... Voltage-controlled oscillator 109 ... Power generator 110 ... Reset circuit 111 ... Digital input value reading unit 113 ... Power supply monitoring unit 114 ... switch 115 ... Backup power supply circuit

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-11-308104 (JP, A) JP-A-2-192319 (JP, A) JP-A-9-238070 (JP, A) JP-A-9- 214327 (JP, A) JP 3-131122 (JP, A) JP 6-338784 (JP, A) JP 10-126401 (JP, A) JP 64-61120 (JP, A) JP-A-8-298456 (JP, A) JP-A-2001-77688 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03L 7/10 H03L 7/093

Claims (8)

(57) [Claims] 1. Inputting a reference clock from a host station,
, A second frequency divider for converting the reference clock of the radio base station apparatus into a second phase comparison clock, and a first phase comparison clock Then, a reset circuit that outputs a reset signal to the second frequency divider, a sampling clock generation unit that generates a sampling clock, and the first and second phase comparison clocks and the sampling clock are input to the first and the second frequency dividers. A phase comparing means for detecting the phase difference of 2 and outputting the phase difference; a computing means for inputting the phase difference and controlling a digital input value; a digital input value storing means for storing the digital input value; A D / A converter for receiving an input and converting it into an analog output; and a voltage control type oscillating means for receiving the analog output and outputting the reference clock of the wireless base station device. Reference clock generating apparatus; and a power supply voltage generator for supplying a power supply voltage to each unit. 2. The reference clock generation device according to claim 1, further comprising a nonvolatile memory for the digital input value storage means. 3. The digital input value storage means stores a digital input value in a phase synchronization process in which the phase difference between the first and second phase comparison clocks is continuously 0 for a certain period. The reference clock generation device according to claim 1, further characterized. 4. When the output of the power supply voltage generator is cut off and then restored again, the arithmetic means reads the digital input value from the digital input value storage means, and the analog value is read by the D / A converter. By supplying the analog value to the voltage control type oscillation means,
4. The reference clock generator as claimed in claim 2, further characterized by obtaining a phase synchronization process without performing a frequency pulling operation. 5. A digital input value reading means for periodically reading a digital input value set in the D / A converter and outputting the read value to the arithmetic means is further provided. 4. The reference clock generation device according to claim 4. 6. The calculating means compares the digital input value input from the digital input value reading means with the digital input value read from the digital input value storing means, and digitally outputs the digital input value until the two values are the same. The reference clock generator according to claim 5, further comprising outputting an input value to the D / A converter. 7. A power supply monitoring means for inputting a power supply voltage from the power supply voltage generator and outputting a switching signal based on the level of the power supply voltage, and a power supply for supplying the digital input value storage means to a backup power supply or the The switch according to any one of claims 1 to 3, further comprising a switch for switching to a power supply of the power supply voltage generator and a backup power supply circuit for inputting a power supply voltage of the power supply voltage generator and outputting a backup power supply. Reference clock generator described. 8. The reference clock generating device according to claim 7, further comprising a volatile memory as the digital input value storage means.