JP3592291B2 - Automatic frequency adjustment method and automatic frequency adjustment device for reference clock generator - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an automatic frequency adjustment method and an automatic frequency adjustment device for a reference clock generation device, and more particularly to a PLL (Phase Locked Loop) that receives a high-accuracy reference clock from an external source by using a highly stable oscillator inside the reference clock generation device. The present invention relates to an automatic frequency adjustment method and an automatic frequency adjustment apparatus for a reference clock generator that automatically adjusts a frequency by performing frequency synchronization by a circuit and storing a control voltage of a PLL circuit.
[0002]
More specifically, in FIG. 1, when the frequency is automatically adjusted according to the present invention, the reference clock generator 101 receives the reference clock fr output from the clock generator 110 in FIG. The input signal detection unit 111 notifies the calculation unit 105 that the reference clock has been input. At this time, the calculation unit 105 starts adjusting the frequency and simultaneously displays the signal indicating that the frequency is being adjusted to the adjustment state display unit 109. The adjustment state display unit 109 displays that the apparatus is in the frequency adjustment state outside the apparatus, and the calculation unit 105 displays the phase difference P obtained from the phase difference comparison unit 104 as “0”. The D / A converter 107 is controlled so that the phase difference P remains “0” for a certain period of time. It is determined that the adjustment has been completed, and the digital input value of the D / A converter 107 at that time is stored in the digital input storage unit 106, and at the same time, a signal indicating that the frequency adjustment has been completed is transmitted to the adjustment state display unit 109. The status display unit 109 is an automatic adjustment method of the reference clock generation device that indicates that the frequency adjustment is completed outside the device.
[0003]
[Prior art]
FIG. 6 shows a configuration example of a first prior art of a reference clock generator in this type of technology.
[0004]
The reference clock generator 201 shown in FIG. 6 is different from FIG. 1 showing the block configuration of the reference clock generator according to the present invention in that a frequency divider A 102, a frequency divider B 103, a phase comparator 104, an arithmetic The difference is that the unit 105, the digital input value storage unit 106, the D / A converter 107, and the adjustment state display unit 109 are not provided, and the variable resistor 204 and the resistor 209 are provided.
[0005]
The variable resistor 204 is connected to the resistor 209 and a power supply. The resistor 209 is connected to the variable resistor 204 and the ground. The voltage at the connection between the variable resistor 204 and the resistor 209 is defined as the control voltage Vc203 of the high stability oscillator 202.
[0006]
Further, a frequency counter 207 and an adjuster 205 are prepared outside the reference clock generator 201. The frequency counter 207 receives the reference clock fr output from the clock generator 208 and the reference clock fo of the radio base station, and displays the value of the reference clock fo of the radio base station. The adjuster 205 can change the resistance value of the variable resistor 204.
[0007]
The operation of the reference clock generator 201 shown in FIG. 6 at the time of frequency adjustment will be described below.
[0008]
When the frequency adjustment operator increases the resistance value of the variable resistor 204 using the adjuster 205, the voltage value of the control voltage Vc203 of the high-stability oscillator 202 decreases because the voltage drop between the power supply and the voltage Vc increases. . Then, since the frequency of the reference clock fo of the wireless base station device output from the high stability oscillator 202 decreases, the value displayed on the frequency counter 207 also decreases.
[0009]
Further, when the operator lowers the resistance value of the variable resistor 204 using the adjuster 205, the voltage drop between the power supply and the voltage Vc becomes smaller, so that the voltage value of the control voltage Vc203 of the highly stable oscillator 202 increases. . Then, since the frequency of the reference clock fo of the wireless base station device output from the high stability oscillator 202 increases, the value displayed on the frequency counter 207 also increases.
[0010]
Therefore, the operator raises and lowers the resistance value of the variable resistor 204 using the adjuster 205 and visually observes the frequency displayed on the frequency counter 207, whereby the radio base station output from the reference clock generator 201 is output. The reference clock fo of the device can be adjusted to the desired frequency.
[0011]
Japanese Patent Application Laid-Open No. 63-070616, which is a second prior art, provides a correction circuit that corrects a clock frequency error by inputting a comparison clock and a storage circuit that stores a correction amount. There is disclosed a clock frequency adjustment circuit for automatically adjusting the clock frequency to reduce the adjustment time and eliminate human error.
[0012]
As a third prior art, Japanese Patent Application No. 2001-067268, which is filed by the same applicant as the present applicant, discloses that when a phase difference P becomes zero for a certain period of time, an arithmetic unit performs a phase synchronization process. And the digital input value VD at that time is stored in the digital input value storage unit. After that, a failure occurs in the power supply device due to an external factor such as a lightning strike, and the power supply supplied to the reference clock generator is determined. When the VBTS is momentarily interrupted, the arithmetic unit reads the digital input value VD from the digital input value storage unit and sets the digital input value VD in the D / A converter. A reference clock generator that can be set, can supply a reference clock fo having the same frequency after a momentary power failure as before the momentary power failure, and maintain a phase synchronization process is described.
[0013]
Japanese Patent Application Laid-Open No. H11-136632, which is a fourth prior art, discloses that when a PCR signal is input as reference information for generating a reference clock, the PCR signal is extracted by a PCR detector and the PCR signal is output. And a control voltage corresponding to the result of comparison with the output signal of the voltage controlled oscillator (VCO) is supplied to the VCO, whereby the VCO is controlled so that its output signal is phase-locked to the PCR signal, and the PCR signal is A clock generation device is disclosed in which a control voltage stored in a memory is supplied to a VCO when not input.
[0014]
[Problems to be solved by the invention]
However, the first prior art reference clock generator 201 has the following problems.
[0015]
The first problem is that there is a variation in quality due to manual adjustment of the operator and visual confirmation of the frequency.
[0016]
The second problem is that only one reference clock generator can be adjusted per worker, so that the time or labor required for frequency adjustment is required.
[0017]
A third problem is that since the frequency counter is used at the time of frequency adjustment, equipment costs required for the adjustment are required.
[0018]
In the configuration of the second prior art, the frequency division ratio is stored in the storage circuit, and the frequency according to the frequency division ratio is output. The difference is that adjustment is performed by changing the frequency of the stable oscillator 108 itself, and the digital value of the control voltage of the highly stable oscillator 108 is stored in the digital input value storage unit 106.
[0019]
Further, as a problem of the second prior art, there is no part for displaying the frequency adjustment state to the outside, so that an operator cannot easily judge the completion of the frequency adjustment.
[0020]
In the third prior art, a voltage value in a phase synchronization process set in a VCO is stored in a memory, and the voltage value stored in the memory is restored in the VCO when the power of the wireless base station device is restored after a momentary power failure. However, the clock frequency cannot be adjusted automatically.
[0021]
In a fourth prior art, the control voltage supplied to the VCO is stored in a memory, and when the PCR signal is momentarily interrupted, the control voltage stored in the memory is switched to the VCO and connected. Again, as in the third prior art, the adjustment of the clock frequency cannot be performed automatically.
[0022]
The present invention has been made in view of the above-described conventional circumstances, and accordingly, an object of the present invention is to provide a new reference clock generating device capable of solving the above-described drawbacks inherent in each of the above prior arts. An object of the present invention is to provide an automatic frequency adjustment method and an automatic frequency adjustment device.
[0023]
[Means for Solving the Problems]
In order to achieve the above object, a method for automatically adjusting the frequency of a reference clock generator according to the present invention is characterized in that, when a reference clock output from a clock generator is input to the reference clock generator, the input signal detector detects the reference clock. The arithmetic unit is notified that the clock is being input, and the arithmetic unit starts automatic frequency adjustment by the notification, and further, the arithmetic unit sets the phase difference obtained by the phase difference comparing unit to “0”. The D / A converter is controlled as described above, and when the state where the phase difference is “0” continues for a certain period of time, it is determined that the frequency adjustment has been completed, and the digital input value of the D / A converter at that time is digitally input. It is characterized in that the frequency of the reference clock generator in the radio base station is automatically adjusted by storing it in the value storage unit and arithmetically processing the control voltage of the voltage controlled oscillator using the PLL circuit. It is set to.
[0024]
At the same time as the arithmetic unit starts adjusting the frequency, the arithmetic unit transmits a signal indicating that the frequency is being adjusted to the adjustment state display unit and causes the adjustment state display unit to indicate that the device is in the frequency adjustment state outside the device, If it is determined that the frequency adjustment has been completed, a signal indicating that the frequency adjustment has been completed is transmitted to the adjustment state display unit, and the fact that the frequency adjustment has been completed is displayed outside the apparatus.
[0025]
In the present invention, The reference clock output from the clock generator is divided into a plurality of reference clocks, and the distributed number of reference clocks are supplied to a plurality of arranged reference clock generators, respectively, thereby simultaneously providing a plurality of reference clocks for a plurality of radio base station apparatuses. Can be adjusted.
[0026]
An automatic frequency adjustment device of a reference clock generation device according to the present invention includes a first frequency divider that inputs a reference clock output from a clock generator and converts the input reference clock into a first phase comparison clock; A second frequency divider for inputting a reference clock and converting it into a second phase comparison clock; inputting the first phase comparison clock, the second phase comparison clock, and the sampling clock to the first and second clocks; Phase comparison means for detecting a phase difference between the two phase comparison clocks and outputting the phase difference; a calculation means for inputting the phase difference and calculating a digital input value to be a control voltage of a high-stability oscillator, which will be described later; A digital input value storage unit for storing a value, a D / A converter for receiving the digital value and converting the digital input value to an analog output, Constructed and a highly stable oscillator for outputting a reference clock of a frequency of a radio base station apparatus corresponding to the voltage value of the analog output.
[0027]
It is desirable that the digital input value storage section is constituted by a nonvolatile memory such as a flash ROM.
[0028]
The reference clock can be used as the sampling clock.
[0029]
The automatic frequency adjustment device of the reference clock generation device according to the present invention further includes input signal detection means for detecting that a reference clock output from the clock generator has been input, and the reference signal generated by the input signal detection means. Adjustment state display means for displaying frequency adjustment state information and frequency adjustment completion information, which are determined and output by the arithmetic means which has been notified of the clock and started frequency adjustment in the arithmetic processing process, outside the apparatus, may be provided. it can.
[0030]
The automatic frequency adjustment device of the reference clock generation device according to the present invention also has a phase in which the reference clock output from the clock generator and the reference clock of the radio base station output from the high-stability oscillator described below are input and a phase difference signal is output. A comparator, a loop filter to which the phase difference signal is input and which outputs a control voltage of a high-stability oscillator to be described later, and a control voltage output from the loop filter to be turned on and off by an operation means to be described later A high-stability oscillator supplied through a switch to generate the reference clock; input signal detection means for outputting a reference clock status signal when the reference clock is detected; and inputting the reference clock status signal to perform frequency calculation processing Operation means for starting, and a control voltage which is an output of the loop filter, An A / D converter for generating a corresponding digital value and supplying the digital value to the arithmetic means; and a digitizing control voltage value output from the A / D converter being monitored by the arithmetic means for controlling the reference clock and a reference. A digital input value storage unit for storing a value of the control voltage at that time when a clock coincides and the value of the digitized control voltage has not changed for a certain period of time; and Adjustment for displaying outside that the normal state where the reference clock is not input, the fact that the reference clock is input to the input signal detecting means and the frequency adjustment state, and the fact that the frequencies match and the adjustment is completed state. Status display means; and, in the normal state after the completion of the adjustment completion state, the digital value writing at a certain period by the arithmetic means. It receives the digital values read from the part into an analog value comprised a D / A converter to be supplied to the high stability oscillator.
[0031]
The arithmetic unit switches the switch to an “off” state in a normal state in which the reference clock is not supplied to the input signal detecting unit.
[0032]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0033]
[First Embodiment]
First, a first embodiment according to the present invention will be described in detail with reference to the drawings.
[0034]
FIG. 1 is a block diagram showing an example of the first embodiment according to the present invention.
[0035]
[Configuration of First Embodiment]
Referring to FIG. 1, a reference clock generator 101 receives a reference clock fr input from a clock generator 110 and converts it into a phase comparison clock frc, and a reference clock fo of a radio base station apparatus. A frequency divider B103 for inputting a phase comparison clock foc and converting it into a phase comparison clock foc, a phase comparison clock frc, a phase comparison clock foc, and a sampling clock fs are input, and the phase difference between the phase comparison clock frc and the phase comparison clock foc is detected to detect the phase difference P , A computing unit 105 that receives the phase difference P to control the digital input value VD, a digital input value storage unit 106 that stores the digital input value VD, and a digital signal that receives the digital input value VD. A D / A converter 107 for converting an input VD into an analog output VA, and an analog output VA A high-stable oscillator 108 for inputting and outputting a reference clock fo of the radio base station; an adjustment state display unit 109 for receiving an adjustment state signal output from the arithmetic unit 105 and displaying the adjustment state outside the reference clock generator 101; And an input signal detection unit 111 that notifies the calculation unit 105 of the input state of the reference clock fr.
[0036]
The phase comparison unit 104 sets the value of the phase difference P negative when the phase comparison clock foc is delayed with respect to the phase comparison clock frc, and sets the value of the phase difference P positive when the phase comparison clock foc is advanced.
[0037]
The arithmetic unit 105 increases the digital input VD when the input value of the phase difference P is negative, and decreases the digital input VD when the value is positive.
[0038]
The digital input value storage unit 106 stores the output of the arithmetic unit 105, that is, the digital input VD of the D / A converter 107. The non-volatile memory such as a flash ROM is used. The digital input value VD is not erased.
[0039]
The D / A converter 107 increases the analog output VA when the digital input VD increases, and decreases the analog output VA when the digital input VD decreases.
[0040]
The high-stable oscillator 108 outputs the reference clock fo of the radio base station apparatus having a frequency corresponding to the voltage value of the analog output VA. When the analog output VA increases, the frequency of the reference clock fo increases and decreases. , The frequency of the reference clock fo decreases.
[0041]
The adjustment state display unit 109 distinguishes the three states of the frequency adjustment, the completion of the frequency adjustment, and the normal state based on the adjustment state signal input from the arithmetic unit 105, and displays the three states outside the reference clock generator 101.
[0042]
The input signal detection unit 111 inputs a reference clock state signal to the arithmetic unit 105 by distinguishing between two states when the reference clock fr is input to the reference clock generation device 101 or when the reference clock fr is not input.
[0043]
[Operation of First Embodiment]
Next, the operation of the first embodiment according to the present invention will be described.
[0044]
When the reference clock fr is not input to the reference clock generator 101 shown in FIG. 1, the input signal detection unit 111 notifies the calculation unit 105 that the reference clock fr is not input. Since the reference clock fr has not been input, the arithmetic unit 105 notifies the adjustment state display unit 109 of the normal state, and the adjustment state display unit 109 notifies the adjustment state display unit 109 of the normal state to the outside of the reference clock generator 101. indicate. Thereby, it is determined that the state is the normal state.
[0045]
Next, a series of operations at the time of frequency adjustment will be described below.
[0046]
When adjusting the frequency, the reference clock fr output from the clock generator 110 is input to the reference clock generator 101. At this time, the input signal detection unit 111 notifies the calculation unit 105 that the reference clock fr has been input. Since the reference clock fr has been input, the arithmetic unit 105 notifies the adjustment state display unit 109 that it is in the frequency adjustment state. The adjustment state display unit 109 displays the fact that it is in the frequency adjustment state outside the reference clock generator 101. Thereby, it is determined that the state is the frequency adjustment state.
[0047]
Next, the operation inside the reference clock generator 101 in the frequency adjustment state will be described below.
[0048]
When the reference clock fr is input, the phase difference comparator 104 detects a phase difference between the reference clock fo and the reference clock fr, and outputs a phase difference P to the calculator 105. When the phase difference P is negative, the operation unit 105 operates to increase the digital input value VD.
[0049]
Therefore, the value of the analog output VA also increases.
[0050]
When the value of the analog output VA increases, the frequency of the reference clock fo of the wireless base station device also increases, and as a result, the phase difference P also increases.
[0051]
When the phase difference P is positive, the operation unit 105 operates to decrease the digital input value VD.
[0052]
Therefore, the value of the analog output VA decreases. When the value of the analog output VA decreases, the frequency of the reference clock fo of the radio base station device also decreases, and as a result, the phase difference P also decreases.
[0053]
When the above operations are continuously performed, as shown in FIG. 2, the phase difference between the phase comparison clock frc and the phase comparison clock foc eventually slightly changes near zero.
[0054]
As a result, the reference clock fo of the wireless base station device is in a state of being synchronized with the reference clock fr input from the clock generator 110.
[0055]
When the phase difference P has become “0” for a certain period, the arithmetic unit 105 determines that the frequency of the reference clock fr input from the clock generator 110 matches the frequency of the reference clock fo of the radio base station apparatus. The digital input value VD at that time is stored in the digital input value storage unit 106, and the fact that the adjustment has been completed is input to the adjustment state display unit 109 using an adjustment state signal.
[0056]
The adjustment state display unit 109 displays the adjustment completion state outside the reference clock. At this time, the adjustment state display unit 109 determines that the adjustment is completed, and the input of the reference clock fr from the clock generator 110 to the reference clock generator 101 is stopped.
[0057]
Since the reference clock fr has not been input, the arithmetic unit 105 notifies the adjustment state display unit 109 of the normal state, and the adjustment state display unit 109 notifies the adjustment state display unit 109 of the external state of the reference clock generator 101 To be displayed. Thus, it is determined that the state is the normal state.
[0058]
In the normal state, the arithmetic unit 105 keeps inputting the value read from the digital input value to the D / A converter 107 by a certain fixed frequency divider. The D / A converter 107 oscillates at a frequency corresponding to the voltage value at the time when the frequency adjustment is completed, in order to output an analog voltage corresponding to the digital input value input from the arithmetic unit 105.
[0059]
Thereby, the reference clock generator 101 can supply the same frequency as the reference clock fr to the radio base station.
[0060]
[Second embodiment]
Next, a second embodiment according to the present invention will be described in detail with reference to the drawings.
[0061]
FIG. 4 is a block diagram showing an example of the second embodiment according to the present invention.
[0062]
[Configuration of the Second Embodiment]
Referring to FIG. 4, in the second embodiment of the present invention, the phase synchronization of the reference clock fr and the reference clock fo of the radio base station is performed using an analog PLL circuit.
[0063]
The second embodiment shown in FIG. 4 includes a frequency divider A102, a frequency divider B103, and a phase difference comparing unit 104, as compared with the first embodiment shown in FIG. This is different from the above-mentioned configuration in that the phase comparator 112, the loop filter 113, the switch 114, and the A / D converter 115 are provided.
[0064]
The phase comparator 112 receives the reference clock fr output from the clock generator 110 and the reference clock fo of the wireless base station output from the high stability oscillator 108, and outputs a phase difference signal PD. The phase difference signal PD is input to the loop filter 113, and the loop filter 113 outputs a control voltage Vc of the highly stable oscillator 108. The switch 114 is turned on or off by the arithmetic unit 105. The control voltage Vc is input to the A / D converter 115, and the A / D converter 115 outputs a digital value Vcd corresponding to the input voltage value to the arithmetic unit 105.
[0065]
When the reference clock fr is not input to the reference clock generator 101 shown in FIG. 4, the input signal detection unit 111 notifies the calculation unit 105 that the reference clock fr is not input. Since the reference clock fr has not been input, the arithmetic unit 105 notifies the adjustment state display unit 109 of the normal state, and sets the switch 104 to the “OFF” state.
[0066]
The adjustment state display unit 109 displays the normal state outside the reference clock generator 101. The operator performing the frequency adjustment visually checks the adjustment state display unit 109 and determines that the state is the normal state.
[0067]
When adjusting the frequency, the reference clock fr output from the clock generator 110 is input to the reference clock generator 101. At this time, the input signal detection unit 111 notifies the calculation unit 105 that the reference clock fr has been input.
[0068]
Since the reference clock fr has been input, the calculation unit 105 notifies the adjustment state display unit 109 of the frequency adjustment state, and turns the switch 104 on. The adjustment state display unit 109 displays the fact that it is in the frequency adjustment state outside the reference clock generator 101. Thereby, it is determined that the state is the frequency adjustment state.
[0069]
[Operation of Second Embodiment]
Next, the internal operation of the reference clock generator 101 in the frequency adjustment state will be described below with reference to FIG.
[0070]
The phase comparator 112 compares the reference clock fr with the reference clock fo of the radio base station. If the rise of the reference clock fo is later than the rise of the reference clock fr, the phase difference signal PD (+ ) Is output. When the positive pulse phase difference signal PD (+) is input, the loop filter 113 increases the voltage value of the control voltage Vc, which is its output. When the voltage value of the control voltage Vc increases, the frequency of the high stability oscillator 108 increases.
[0071]
If the rise of the reference clock fo is earlier than the rise of the reference clock fr, the phase comparator 112 outputs a negative pulse phase difference signal PD (-). When the negative pulse phase difference signal PD (−) is input, the loop filter 113 decreases the voltage value of the control voltage Vc.
[0072]
By performing the operations described above continuously, the phases of the reference clock fr and the reference clock fo match, so that the frequencies match. At that time, the voltage value of the control voltage Vc becomes substantially constant.
[0073]
The arithmetic unit 105 monitors the value of the value Vcd obtained by digitally converting the control voltage Vc output from the A / D converter 115, and if the value of the digital voltage Vcd has not changed for a certain period, the digital The value of the voltage Vcd is stored in the digital input value storage unit 106, and the adjustment completion signal is input to the adjustment state display unit 109 with the adjustment state signal, and the switch 104 is turned off.
[0074]
The adjustment state display unit 109 displays the adjustment completion state outside the reference clock. At this time, the adjustment state display unit 109 is checked, it is determined that the adjustment is completed, and the input of the reference clock fr to the reference clock generator 101 is stopped.
[0075]
At that time, since the reference clock fr has not been input, the arithmetic unit 105 notifies the adjustment state display unit 109 of the normal state, and sets the switch 104 to the “OFF” state. The adjustment state display unit 109 displays the normal state outside the reference clock generator 101. Thereby, it is determined that the state is the normal state.
[0076]
In the normal state, the arithmetic unit 105 keeps inputting the value read from the digital input value storage unit 106 to the D / A converter 107 at a certain fixed cycle. Since the D / A converter 107 outputs an analog voltage corresponding to the digital input value input from the arithmetic unit 105, the high-stability oscillator 108 oscillates at a frequency corresponding to the voltage value at the time when the frequency adjustment is completed. The clock generator 101 supplies the same frequency as the reference clock fr to the radio base station.
[0077]
【The invention's effect】
The present invention is configured and operates as described above, and according to the present invention, the following effects can be obtained.
[0078]
A first effect of the present invention is that the reference clock fo of the reference clock generator 101 of the wireless base station device can be adjusted without using a frequency counter.
[0079]
The reason is that, when the reference clock fr is input from the outside, the reference clock generator 101 operates so that the reference clock fr and the reference clock fo of the radio base station apparatus coincide with each other. This is because the frequency adjustment state can be determined only by checking the adjustment state display unit 109 of the reference clock generator 101 in order to display the completion and store the control voltage.
[0080]
A second effect of the present invention is that the quality of the reference clock fo of the radio base station apparatus after the frequency adjustment can be made constant as compared with an external reference clock fr.
[0081]
The reason is that the calculation unit 105 determines that the phase difference P during the frequency adjustment has become “0” for a predetermined period.
[0082]
A third effect of the present invention is to increase the working efficiency because the frequency is automatically adjusted only by inputting the reference clock fr from the outside.
[0083]
The reason is that only the reference clock fr is input from the outside, and no manual adjustment is required to automatically adjust the frequency.
[0084]
A fourth effect of the present invention is to adjust the reference clock fo of the reference clock generators 101 of a plurality of wireless base station devices at a time, thereby increasing work efficiency.
[0085]
The reason will be described with reference to FIG. Referring to FIG. 3, the reference clock from the clock generator is distributed to a plurality, and the distributed number of reference clocks are supplied to the reference clock generator 101 to adjust the reference clocks fo of the plurality of radio base station apparatuses at once. be able to.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of a reference clock generator according to a first embodiment of the present invention.
FIG. 2 is a timing chart showing a relationship between a phase comparison clock, an analog output, and a phase difference during operation of the digital PLL circuit according to the first embodiment of the present invention.
FIG. 3 is a block diagram illustrating a method for adjusting the frequencies of a plurality of reference clock generators.
FIG. 4 is a block diagram showing an example of a reference clock generator according to a second embodiment of the present invention.
FIG. 5 is a timing chart showing a relationship between each clock, a phase difference signal, and a control voltage when an analog PLL circuit operates in a second embodiment of the present invention.
FIG. 6 is a block diagram illustrating a configuration example of a conventional reference clock generator.
[Explanation of symbols]
101, 201: Reference clock generator
102: frequency divider A
103 ... frequency divider B
104: phase difference comparison unit
105 arithmetic unit
106: Digital input value storage unit
107 ... D / A converter
108, 202: Highly stable oscillator
109 ... adjustment state display section
110, 208 ... clock generator
111 ... input signal detection unit
112 ... phase comparator
113 ... Loop filter
114 ... Switch
115 ... A / D converter
203: control voltage Vc
204: Variable resistance
205 ... Adjuster
207 ... frequency counter
209 ... resistance

Claims (5)

When the reference clock output from the clock generator is input to the reference clock generator, the input signal detection unit notifies the arithmetic unit that the reference clock is input, and the arithmetic unit uses the notification to determine the frequency. The automatic adjustment is started, and the arithmetic unit controls the D / A converter so that the phase difference obtained from the phase difference comparison unit is set to “0”. In this case, it is determined that the frequency adjustment has been completed, the digital input value of the D / A converter at that time is stored in the digital input value storage unit, and the control voltage of the voltage controlled oscillator is arithmetically processed using the PLL circuit. A method for automatically adjusting the frequency of a reference clock generator in a wireless base station by automatically adjusting the frequency of the reference clock generator in the wireless base station. At the same time as the arithmetic unit starts adjusting the frequency, the arithmetic unit transmits a signal indicating that the frequency is being adjusted to the adjustment state display unit and causes the adjustment state display unit to indicate that the device is in the frequency adjustment state outside the device, If the frequency adjustment is determined to have been completed, a signal indicating that the frequency adjustment has been completed is transmitted to the adjustment state display unit, and the fact that the frequency adjustment has been completed is displayed outside the apparatus. 2. The method for automatically adjusting the frequency of the reference clock generator according to 1. A first frequency divider for inputting a reference clock output from the clock generator and converting it into a first phase comparison clock; , The first phase comparison clock, the second phase comparison clock, and the sampling clock are input to detect a phase difference between the first and second phase comparison clocks and output a phase difference. Phase comparing means, calculating means for calculating the digital input value to be the control voltage of the high-stability oscillator to be described later by inputting the phase difference, digital input value storing section for storing the digital input value, and inputting the digital value A D / A converter for converting the digital input value to an analog output, and a reference for a radio base station apparatus which receives the analog output and has a frequency corresponding to the voltage value of the analog output A high-stable oscillator that outputs a lock, input signal detection means for detecting that a reference clock output from the clock generator has been input, and a notification of the input of the reference clock by the input signal detection means, and A reference clock generator comprising: a frequency adjustment state information output by the arithmetic means which has started the adjustment and a frequency adjustment completion information determined and output in an arithmetic processing process . Automatic frequency adjustment device. A phase comparator that receives a reference clock output from a clock generator and a reference clock of a radio base station that is output from a high-stability oscillator, and outputs a phase difference signal; A loop filter that outputs a control voltage, a high-stable oscillator that supplies the control voltage output from the loop filter through a switch that is turned “on” and “off” by arithmetic means, and generates the reference clock. An input signal detection unit that outputs a reference clock state signal when the reference clock is detected, an operation unit that inputs the reference clock state signal to start frequency operation processing, and a control voltage that is an output of the loop filter. A / D converter that generates a digital value corresponding to the control voltage and supplies the digital value to the arithmetic means The arithmetic unit monitors the value of the digitized control voltage output from the converter and the A / D converter, and when the reference clock and the reference clock match, the digitized control voltage value is constant. A digital input value storage unit that stores the value of the control voltage at that time when there is no change in the period; a normal state in which the reference clock is not input to the input signal detection unit; Means for externally displaying that the reference clock is input to the means and that the frequency is in an adjusted state and that the frequencies match and the adjustment is completed; and Inputting the digital value read from the digital value storage unit at a certain period by the arithmetic unit, converting the digital value into an analog value, Automatic frequency adjustment device of the reference clock generating apparatus; and a D / A converter to be supplied to the high stability oscillator. 5. The automatic frequency control apparatus according to claim 4, wherein the arithmetic unit switches the switch to an "off" state in a normal state in which the reference clock is not supplied to the input signal detecting unit. Adjustment device.

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