JP3518092B2 - Wiring structure - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode or wiring structure of a semiconductor device operating at a high frequency, and relates to a high electron mobility transistor (hereinafter referred to as "H").
(Referred to as EMT), passive elements such as capacitors, and monolithic microwaves I in which they are integrated.
C (Monolithic Microwave Integrated Circuit: M below)
MIC).

[0002]

2. Description of the Related Art In recent years, the frequency of MMICs has been increasing, and in order to improve the performance at high frequencies, the MMICs have to be improved.
It is indispensable to improve the performance of transistors such as HEMTs that compose the. The most effective means for improving the performance of a transistor such as HEMT is to improve the electron mobility of a semiconductor layer in which electrons travel. Therefore, GaAs, which has a higher electron mobility than Si, has been used as a semiconductor material of the electron transit layer in transistors such as HEMTs for high frequencies. In order to cope with higher frequencies in recent years, HE using InGaAs, which has a higher electron mobility than GaAs, as an electron transit layer
Development of MT and MMIC in which they are integrated on an InP substrate is underway. Conventionally, an AuGe / Ni / Au electrode that can obtain a low contact resistance has been used as an ohmic electrode for a transistor using GaAs as an electron transit layer. A proposal for applying this AuGe / Ni / Au ohmic electrode to an ohmic electrode for a transistor having InGaAs as an electron transit layer is disclosed in JP-A-62-1.
No. 94671, for example.

[0003]

[Problems to be Solved by the Invention] However, InP
An electron transit layer made of InGaAs is formed on the substrate H
In the case of EMT or MMIC, AuGe /
When Ni / Au electrode is used, In in the semiconductor is AuGe by heat treatment (alloy) for obtaining ohmic contact.
There is a problem that it diffuses to the surface of the / Ni / Au electrode. FIG. 8 shows a concentration profile in the depth direction from the electrode surface when an AuGe / Ni / Au electrode was formed on an InP substrate and alloyed at 360 ° C. for 2 minutes.
This concentration profile in the depth direction was obtained by Auger analysis while etching by sputtering at 2 nm / min. The horizontal axis represents the sputtering time, and the vertical axis represents the Auger detection intensity. From FIG. 8, it is observed that In diffuses from the InP substrate and In segregates on the electrode surface. H
In EMT and MMIC, such segregation of In on the surface of the ohmic electrode causes problems such as poor adhesion when another wiring is laminated on the ohmic electrode. In particular, there is a high possibility that the wiring will be separated from the interface portion between the ohmic electrode and the wiring formed on the ohmic electrode due to contact of the probe during wire bonding or characteristic measurement. Further, as a method for preventing the diffusion of In to the surface of the ohmic electrode, a method of inserting a barrier metal made of a refractory metal into the ohmic electrode has been proposed in JP-A-4-92471, etc. Since it hinders mutual diffusion of the ohmic electrode material and the semiconductor material, an increase in contact resistance of the ohmic electrode to the semiconductor becomes a problem. Furthermore, when the frequency becomes extremely high, the skin depth becomes shallow (for example, about 300 nm at 60 GHz), and Au is contained in the ohmic electrode.
Another problem is the increase in wiring resistance due to the insertion of a barrier metal having a higher resistance than the above.

Therefore, in view of the above problems, an object of the present invention is to form an intermediate wiring on an ohmic electrode in a wiring structure in which another wiring is laminated on an ohmic electrode formed on a semiconductor substrate containing In. By forming the wiring structure in which the end of the intermediate wiring is fixed by the insulating film and the contact between the intermediate wiring and the upper wiring is made by the contact hole formed in the insulating film, the ohmic electrode of the lower wiring and the intermediate wiring laminated on the ohmic electrode An object of the present invention is to provide a wiring structure capable of preventing wiring peeling such as upper layer wiring.

[0005]

In order to solve the above problems, the structure of the present invention is a wiring structure of an integrated circuit, wherein a first wiring formed on a substrate and a first wiring on the first wiring are formed. An insulating film formed so as to cover the substrate, the first wiring and the second wiring formed on the second wiring, and having an opening smaller than the size of the second wiring on the second wiring. If, to be in contact with the second wiring through the opening, and a third wiring formed in at least the opening and the edge on the second distribution
The technical measure is adopted that the size of the line is smaller than the size of the first wiring .

[0006]

The structure of the second invention is a wiring structure of an integrated circuit.
And the first wiring formed on the substrate and the first wiring
The second wiring formed on the wiring, the substrate, the first wiring and
And the second wiring, and the first wiring is formed on the second wiring.
An insulating film having an opening smaller than the size of the second wiring;
At least touch the second wire through the opening.
Also has an opening and a third wire formed on its edge.
For example, the size of the first wiring is to employ a technical means that less than the magnitude of the second wiring.

According to a third aspect of the invention, the substrate is a semiconductor substrate containing In having at least an active layer provided on the upper surface thereof, and the first wiring is brought into ohmic contact with the active layer by heat treatment. It adopts the technical means of being an ohmic electrode.

The structure of the fourth invention adopts a technical means in which the second wiring is made of Au.

The structure of the fifth invention adopts a technical means that the openings of the first wiring, the second wiring and the insulating film are formed at both end portions under the third wiring. .

According to a sixth aspect of the present invention, the wiring structure has a first wiring, a second wiring, an opening and a third wiring, respectively.
By providing pairs, by arranging an insulating film between one of the first wiring and the second wiring and the other third wiring,
The technical means of forming a capacitor is adopted.

In the structure of the seventh invention, the opening of the insulating film is formed at both ends of the second wiring, and the third wiring is formed so as to contact the second wiring through the opening. Along with
The technical means of being formed on the insulating film so as to intersect the first wiring and the second wiring is adopted.

[0013]

[0014]

[0015]

[0016]

[0017]

The first function of the present invention having the above-described structure is that the second wiring is laminated on the first wiring formed on the substrate, and the substrate, the first wiring and the second wiring are formed. An insulating film is formed so as to cover the second wiring, and an opening smaller than the size of the second wiring is provided in a portion of the insulating film on the second wiring. Then, the third wiring is formed at least over the opening and the edge thereof so as to contact the second wiring through the opening of the insulating film. By configuring the wiring structure as described above, the second wiring formed on the first wiring is held down by the insulating film. Therefore, for example, when the first wiring is formed on the substrate by heat treatment. Even if the adhesion of the first wiring is lowered due to the diffusion and segregation of the components in the substrate, there is an effect that the adhesion between the first wiring and the second wiring can be sufficiently secured. Further, since the first wiring is covered by the second wiring, Ru can be adhesion to the second wiring and the third wiring may be sufficiently secured.

Furthermore, since the second step due to the more first wiring and the second wiring magnitude and child smaller than the size of the first wiring of the wiring is stepped, first an insulating film This has the effect of improving the coverage of the second wiring and the second wiring. Further, since the film thickness of the second wiring can be increased, if the second wiring is made of a low resistance material, the resistance can be reduced as compared with a wiring structure in which the second wiring is not provided. Yes ( Claim 1 ).

The second action is the first wiring of the first action.
And the size of the second wiring is reversed,
It is to make the size of the first wiring smaller than the size of the second wiring, and since the step between the first wiring and the second wiring becomes stepwise, the same effect as the first effect is obtained. The effect of can be obtained ( Claim 2 ).

A third action is to use a substrate as a semiconductor substrate containing In having at least an active layer provided on the upper surface thereof, and a first wiring as an ohmic electrode which is in ohmic contact with the active layer by heat treatment. It is to be. As a result, even if In diffuses and segregates on the surface of the first wiring due to the heat treatment and the adhesion of the first wiring decreases, the second wiring formed on the first wiring becomes an insulating film. Since the pressure is suppressed, there is an effect that the adhesiveness between the first wiring and the second wiring can be sufficiently secured. Further, since the first wiring in which In is segregated is covered with the second wiring, sufficient adhesion between the second wiring and the third wiring via the opening can be secured (( Claim 3 ).

The fourth effect is that the second wiring is made of Au, which has the effect of preventing an increase in wiring resistance at high frequencies ( claim 4 ).

The fifth function is to form the openings of the first wiring, the second wiring and the insulating film at both end portions under the third wiring. As a result, for example, when bonding wires are bonded to both ends of the third wiring, there is an effect that peeling from the both ends of the third wiring can be prevented ( Claim 5 ).

The sixth function is to connect the first wiring, the second wiring,
A pair of openings and third wirings are provided, and an insulating film is arranged between one first wiring and second wiring and the other third wiring to form a capacitor. This can improve the adhesion between the first wiring and the second wiring and the adhesion between the second wiring and the third wiring through the opening ( claim 6 ).

A seventh action is to form an opening in the insulating film at both ends on the second wiring and to form a third wiring so as to contact the second wiring through the opening. It is formed on the insulating film so as to intersect the first wiring and the second wiring.
Thereby, the adhesion between the second wiring and the third wiring can be improved through the opening ( claim 7 ).

[0025]

[0026]

[0027]

[0028]

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) The present invention will be described below based on specific embodiments. FIG. 1 is a schematic structural diagram showing a configuration of a wiring structure 100 (corresponding to a wiring structure) of a semiconductor device according to the present invention. As shown in FIG. 1, a semiconductor substrate 14 such as an InP substrate 14
Lower wiring 11 (corresponding to the first wiring), intermediate wiring 12 (corresponding to the second wiring) made of Au or the like, and contact hole 17 (corresponding to the opening) are provided on (corresponding to the substrate),
An insulating film 15 (corresponding to an insulating film) made of a nitride film or the like and an upper wiring 13 (corresponding to a third wiring) made of Au or the like are sequentially laminated to form a wiring structure 100 of a semiconductor device.

This wiring structure 100 is formed by the following method. First, the lower layer wiring 11 is formed on the semiconductor substrate 14 by metal lift-off. Subsequently, the intermediate wiring 12 is similarly laminated and formed on the lower wiring 11 by metal lift-off. Here, when the lower wiring 11 is an ohmic electrode such as AuGe / Ni / Au for obtaining ohmic contact with the active layer on the surface of the semiconductor substrate 14, alloying is performed before forming the intermediate wiring 12. Intermediate wiring 1
2 is formed, the insulating film 15 is deposited on the substrate 14, the lower layer wiring 11 and the intermediate wiring 12, and then the contact hole 17 is formed.
By RIE, an opening smaller than the size of the intermediate wiring 12 is formed in a portion of the insulating film 15 on the intermediate wiring 12. Then, the upper wiring 13 is formed on the contact hole 17 and the insulating film end portion 16 (corresponding to the edge portion) by electroplating. Here, by making the contact hole 17 smaller than the intermediate wiring 12, the end portion of the intermediate wiring 12 becomes the insulating film end portion 16.
The structure is fixed by. The contact between the intermediate wiring 12 and the upper wiring 13 is made through a contact hole 17 formed in the insulating film 15.

In this way, the wiring structure 10 of the semiconductor device is obtained.
By configuring 0, the end portion of the intermediate wiring 12 is fixed by the insulating film end portion 16 even if the lower wiring 11 has a surface state in which it is difficult to obtain adhesion with the intermediate wiring 12 laminated thereon. Therefore, peeling of the intermediate wiring 12 can be prevented. Further, since the lower layer wiring 11 is covered with the intermediate wiring 12 and the upper layer wiring 13 does not directly contact the lower layer wiring 11, the adhesion of the upper layer wiring 13 can be secured. Accordingly, even if wire bonding is performed on the upper layer wiring 13 or a probe for measuring electrical characteristics is brought into contact with the upper layer wiring 13, the upper layer wiring 13 and the intermediate wiring 12 can be prevented from being separated from the lower layer wiring 11. In addition, since the intermediate wiring 12 is made of a low resistance material such as Au, the wiring resistance is not increased even at a high frequency where the skin depth becomes extremely shallow. Further, by using the metal lift-off for forming the lower layer wiring 11 and the intermediate wiring 12, it is possible to satisfactorily form a metal having low resistance and low reactivity such as Au.
By forming 7 by RIE, the contact hole 17
The processing accuracy of can be improved. Since the upper layer wiring 13 is formed by electroplating, the film thickness of the upper layer wiring 13 is 2 μm.
It is also possible to form the above.

On the other hand, for example, the lower layer wiring 21 is formed on the semiconductor substrate 24, the insulating film 22 having the contact hole 25 is formed on the lower layer wiring 21, and the upper layer wiring 23 is formed on the lower layer via the contact hole 25. A wiring structure 101 that directly contacts the wiring 21 is shown in FIG. Wiring structure 101
In such a case, if the adhesiveness between the lower layer wiring 21 and the upper layer wiring 23 is poor, the bonding wire 26 is connected to the upper layer wiring 2
The upper layer wiring 23 is peeled off from the lower layer wiring 21 when the probe for measuring the electrical characteristics is brought into contact with the upper layer wiring 23.

(Second Embodiment) FIG. 3 is a schematic diagram when the wiring structure 102 according to the present invention is used to improve the adhesion of wirings such as a transmission line of an MMIC. As shown in FIG. 3, the present embodiment is characterized in that a lower layer wiring 31, an intermediate wiring 32, and a contact hole 37 are formed at both end portions of an upper layer wiring 33 serving as a transmission line. Will be explained. First, the lower wiring 31 such as AuGe / Ni / Au ohmic electrode is formed on the semiconductor substrate 34 such as InP by metal lift-off, and after alloying, the intermediate wiring 32 is formed on the lower wiring 31 by metal lift-off. . Then, an insulating film 35 such as a nitride film is deposited thereon, and a contact hole 37 smaller than the size of the intermediate wiring 32 is opened by RIE in a portion of the insulating film 35 on the intermediate wiring 32. Further, an upper layer wiring 33, which will be a transmission line such as a microstrip in the MMIC, is formed thereon by electrolytic plating. In this way, the wiring structure 102 is formed.

With the above structure, the upper wiring 33
Even when the bonding wires 36 are bonded to both ends of the upper wiring 33, the upper layer wiring 33 can be prevented from peeling from both ends. This is AuGe / Ni / A
The lower layer wiring 31 such as the u ohmic electrode secures strong adhesiveness due to the alloy, and the adhesiveness between the lower layer wiring 31 and the upper layer wiring 33 via the intermediate wiring 32 is the same as in the first embodiment. This is because the effect of is sufficiently secured. On the other hand, when the lower layer wiring 31, the intermediate wiring 32, and the contact hole 37 are not provided at both ends of the upper layer wiring 33 and all the upper layer wiring 33 is formed on the insulating film 35, the adhesion of the wiring on the insulating film 35 is improved. Since it is weak, when the bonding wires 36 are bonded to both end portions of the upper layer wiring 33, peeling from the both end portions of the upper layer wiring 33 is likely to occur.

(Third Embodiment) FIG. 4 shows the wiring structure 103 according to the present invention as an MMIC.
FIG. 3 is a schematic diagram when used for an IM (Metal Insulator Metal: metal-insulating film-metal) capacitor. The feature of this embodiment is that the lower layer wiring 41 and the intermediate wiring 4 are
2 and the upper wiring 43 which is in contact with the intermediate wiring 47 through the contact hole 49, and the insulating film 45 is arranged to form a capacitor. The manufacturing method thereof will be described below. To do. First, lower layer wirings 41 and 46 such as AuGe / Ni / Au ohmic electrodes are formed by metal lift-off on a semiconductor substrate 44 such as InP, and after alloying, intermediate wirings 42 and 47 are similarly formed by metal lift-off, respectively. , 46 on top of each other. Then, an insulating film 45 such as a nitride film is deposited thereon, and contact holes 4 smaller than the sizes of the intermediate films 42 and 47 are formed on the insulating films 45 on the intermediate wirings 42 and 47.
8 and 49 are opened by RIE. Further, an upper layer wiring 43, which will be a transmission line such as a microstrip in the MMIC, is formed thereon by electrolytic plating.
In this way, the wiring structure 103 is formed.

With the above structure, the adhesion of the upper layer wiring 43 on the contact holes 48, 49 can be improved by the same effect as the first embodiment. Also,
It goes without saying that the upper layer wiring 43 can be prevented from peeling off even by contact with a probe for wire bonding or electrical characteristic measurement, and the lower layer wiring 41 is formed by laminating the intermediate wiring 42 made of a low resistance material such as Au. The wiring resistance can be reduced as compared with a single layer of the wiring 41.

(Fourth Embodiment) FIG. 5 is a schematic view of a case where the wiring structure 104 according to the present invention is used at a wiring intersection of an MMIC. As shown in FIG. 5, the feature of this embodiment lies in the structure in which the lower layer wiring 51, the intermediate wiring 52 and the upper layer wiring 53 intersect with each other, and the manufacturing method thereof will be described below. First, a semiconductor substrate 5 such as InP
A lower wiring 51 such as an AuGe / Ni / Au ohmic electrode is formed on the lower electrode 51 by metal lift-off, and after alloying, an intermediate wiring 52 is formed on the lower wiring 51 by metal lift-off. Then, an insulating film 57 such as a nitride film is deposited from above, and the intermediate wiring 5 of the insulating film 57 is deposited.
Contact holes 58 and 59, which are smaller than the intermediate wiring 52, are formed in the upper portion by 2 by RIE. Further, in the MMIC, upper layer wirings 54, 55, 57 which will be transmission lines such as microstrips in the MMIC are formed by electroplating. The upper layer wirings 54 and 55 are connected to the lower layer wiring 51 and the intermediate wiring 52 through contact holes 58 and 59, respectively. In this way, the wiring structure 104 is formed.

Needless to say, with the above-mentioned structure, the adhesion of the upper wirings 54, 55 on the contact holes 58, 59 can be improved, and the intermediate wiring 52 of a low resistance material such as Au is laminated on the lower wiring 51. As a result, the wiring resistance can be reduced as compared with the single layer of the lower layer wiring 51.

(Fifth Embodiment) FIG. 6 is a schematic view showing the structure of a wiring structure 105 according to the present invention. As shown in FIG. 6, the feature of the present embodiment is that the size of the intermediate wiring 62 is smaller than that of the lower layer wiring 61, and the manufacturing method thereof will be described below. First, AuGe / N is formed on the semiconductor substrate 64 such as InP.
A lower layer wiring 61 such as an i / Au ohmic electrode is formed by metal lift-off, and after alloying, the lower layer wiring 6 is formed.
An intermediate wiring 62 smaller than the size of 1 is similarly laminated and formed on the lower wiring 61 by metal lift-off. Then, an insulating film 65 such as a nitride film is deposited thereon, and a contact hole 67 smaller than the intermediate wiring 62 is opened by RIE in a portion of the insulating film 65 on the intermediate wiring 62. Further, an upper layer wiring 63 which becomes a transmission line such as a microstrip in the MMIC is formed thereon by electroplating. In this way, the wiring structure 105 is formed.

With the above structure, the lower wiring 61
Even when it is difficult to secure the adhesiveness of the upper wiring, the adhesiveness of the upper wiring 63 is secured by covering the surface of the lower wiring 61 with the intermediate wiring 62 and pressing the intermediate wiring 62 with the insulating film end portion 66. can do. Further, since the size of the intermediate wiring 62 is smaller than the size of the lower wiring 61, the step between the lower wiring 61 and the intermediate wiring 62 has a stepped shape, and the insulating film 65 covers the lower wiring 61 and the intermediate wiring 62. It is possible to improve the sex. As described above, in this embodiment, since the coverage with the insulating film 65 can be improved, the film thickness of the intermediate wiring 62 can be made thicker than the conventional one.
This is particularly effective in the case where the low resistance intermediate wiring is formed on the lower layer wiring to reduce the resistance as compared with the lower wiring single layer as in the third and fourth embodiments.

(Sixth Embodiment) FIG. 7 is a schematic view showing the structure of a wiring structure 106 according to the present invention. The feature of the present invention is as shown in FIG.
The size of the lower layer wiring 71 is smaller than the size of the intermediate wiring 72, and the manufacturing method thereof will be described below.
First, on a semiconductor substrate 74 such as InP, AuGe / Ni /
A lower layer wiring 71 such as an Au ohmic electrode is formed by metal lift-off, and after alloying, an intermediate wiring 72 larger than the size of the lower layer wiring 71 is similarly laminated on the lower layer wiring 71 by metal lift-off. Then, an insulating film 75 such as a nitride film is deposited thereon, and a contact hole 77 smaller than the intermediate wiring 72 is opened by RIE in a portion of the insulating film 75 on the intermediate wiring 72. Further, an upper layer wiring 73, which will be a transmission line such as a microstrip in the MMIC, is formed thereon by electroplating. In this way, the wiring structure 106 is formed.

With the above structure, the lower wiring 71
Even when it is difficult to secure the adhesiveness of the upper wiring, the adhesiveness of the upper wiring 73 is secured by covering the surface of the lower wiring 71 with the intermediate wiring 72 and pressing the intermediate wiring 72 with the insulating film end portion 76. can do. Further, since the size of the lower layer wiring 71 is smaller than that of the intermediate wiring 72, the step formed by the lower layer wiring 71 and the intermediate wiring 72 becomes stepwise, and the lower layer wiring 71 and the intermediate wiring 72 by the insulating film 75 are formed.
The coating property of can be improved. As described above, in this embodiment, since the coverage with the insulating film 75 can be improved similarly to the fifth embodiment, the film thickness of the intermediate wiring 72 can be increased, and the third embodiment and the fourth embodiment can be improved. In particular, it is particularly effective when a low resistance intermediate wiring is formed on the lower layer wiring to reduce the resistance as compared with the lower layer wiring single layer.

In each of the above embodiments, the lower wiring and the intermediate wiring are formed by metal lift-off, but the present invention is not limited to this. For example, after the lower wiring and the intermediate wiring are formed on the upper surface of the substrate by sputtering. Alternatively, another method such as forming into a predetermined shape by etching may be used.
In each of the above embodiments, the contact hole is formed by RIE.
However, the contact hole may be formed by using another method such as wet etching. In each of the above embodiments, the upper layer wiring is formed by electroplating. However, when the film thickness of the upper layer wiring is less than 2 μm, other methods such as electroless plating and lift-off may be used.

In this embodiment, the example in which the wiring structure is applied to the semiconductor substrate has been described, but the present invention may be applied to the wiring structure such as an integrated circuit, and the application target is not limited.

As described above, according to the present invention, the intermediate wiring is formed on the lower wiring, and the upper wiring is brought into contact with the intermediate wiring through the opening of the insulating film formed on the intermediate wiring. By forming at least the opening and the edge thereof, it is possible to secure sufficient adhesion between the intermediate wiring and the upper wiring. Also, since the intermediate wiring can be pressed by the insulating film, the adhesion between the lower layer wiring and the intermediate wiring can be secured,
It is possible to prevent the upper layer wiring and the intermediate wiring from peeling off due to the contact of the probe at the time of wire bonding or the measurement of the electrical characteristics, so that the wiring structure with excellent quality can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic structural diagram showing a configuration of a first embodiment according to the present invention.

FIG. 2 is a schematic diagram showing a configuration of a wiring structure in which no intermediate wiring is provided.

FIG. 3 is a schematic structural diagram showing a configuration of a second embodiment according to the present invention.

FIG. 4 is a schematic structural diagram showing the configuration of a third embodiment according to the present invention.

FIG. 5 is a schematic structural diagram showing the configuration of a fourth embodiment according to the present invention.

FIG. 6 is a schematic structural diagram showing a configuration of a fifth embodiment according to the present invention.

FIG. 7 is a schematic structural diagram showing the configuration of a sixth embodiment according to the present invention.

FIG. 8 shows the case where an AuGe / Ni / Au electrode is formed on an InP substrate and alloying is performed at 360 ° C. for 2 minutes.
The graph which showed the concentration profile in the depth direction from the electrode surface.

[Explanation of symbols]

11 Lower layer wiring 12 Intermediate wiring 13 Upper layer wiring 14 Semiconductor substrate 15 Insulating film 16 Insulating film edge 17 contact holes 100 Semiconductor device wiring structure

Continuation of the front page (56) Reference JP-A-7-226487 (JP, A) JP-A-63-95620 (JP, A) JP-A-59-149062 (JP, A) (58) Fields investigated (Int .Cl. ⁷ , DB name) H01L 21/3205 H01L 21/28 301

Claims (7)

(57) [Claims] 1. A wiring structure for an integrated circuit, comprising: a first wiring formed on a substrate; a second wiring formed on the first wiring; the substrate; and the first wiring. And an insulating film formed to cover the second wiring and having an opening on the second wiring that is smaller than the size of the second wiring, and the second wiring through the opening. To contact
E Bei and a third wiring formed on at least the opening and the edges thereof, the magnitude of the second wire, the size of the first wiring
The wiring structure is characterized by its small size . 2. A wiring structure of an integrated circuit, comprising: a first wiring formed on a substrate; a second wiring formed on the first wiring; the substrate; and the first wiring. And an insulating film formed to cover the second wiring and having an opening on the second wiring that is smaller than the size of the second wiring, and the second wiring through the opening. To contact
E Bei and a third wiring formed on at least the opening and the edges thereof, the magnitude of the first wiring, the size of the second wiring
The wiring structure is characterized by its small size . 3. The substrate is an In-containing semiconductor substrate in which an active layer is provided on at least the upper surface thereof, and the first wiring is an ohmic electrode in ohmic contact with the active layer by heat treatment. Characterized by being
The wiring structure according to claim 1 or 2 . 4. The wiring structure according to claim 1 , wherein the second wiring is made of Au. Wherein said first wiring, wherein the opening of the second wiring and the insulating film, according to claim claim 1, characterized in that formed at both ends under the third wiring 4. The wiring structure according to any one of 4 above. 6. The wiring structure comprises one each of the first wiring, the second wiring, the opening and the third wiring.
A capacitor is formed by arranging the insulating film between the first wiring and the second wiring on one side and the third wiring on the other side. Claim 1
5. The wiring structure according to claim 4 . 7. The opening of the insulating film is formed at both ends on the second wiring, and the third wiring is in contact with the second wiring through the opening. The wiring structure according to claim 1 , wherein the wiring structure is formed and formed on the insulating film so as to intersect with the first wiring and the second wiring.