JP3532007B2 - Integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to GaAs and InP.
, Etc. to an integrated circuit formed on a semi-insulating semiconductor substrate. In particular, the present invention relates to a wiring structure of a microwave integrated circuit (MMIC) that prevents a decrease in reliability and durability due to wire bonding with other elements.

[0002]

2. Description of the Related Art Conventionally, from the viewpoint of effective use of a frequency band, use of radio waves in a high frequency region has been required, and attention has been paid to a microwave band having a frequency of 3 GHz or more and a millimeter wave band having a frequency of 30 GHz or more. . When the frequency becomes higher, the wavelength of the signal becomes shorter, and it is necessary to apply the so-called distributed constant circuit concept in which the length of the wiring of the electric circuit influences the performance of the circuit. Especially, in the millimeter wave region, the wavelength is 1 cm or less, so the circuit itself must be integrated into an IC.
Microwave (millimeter wave) integrated circuits (MMICs) are needed.

The MMIC forms active elements such as passive elements or transistors acting as capacitors and coils on a surface layer of a semi-insulating semiconductor substrate or a semiconductor active layer laminated on the semiconductor substrate, and these elements are formed. It is a circuit in which a transmission line for transmitting a high frequency to be connected is formed on a semiconductor substrate. Transistors operating at high frequencies are required to operate at extremely high speeds, so GaAs or InGa is used as the active layer.
As is used, and a semi-insulating semiconductor substrate suitable for this is GaAs or InP.

The transmission lines used in the MMIC are roughly classified into a microstrip line and a uniplanar line. The microstrip line has a signal line through which a high-frequency signal flows on the front surface and a ground wire on the back surface. Then, among the active elements and passive elements formed on the front surface, the elements that require grounding are connected to the ground line through via holes that penetrate from the front surface to the back surface of the substrate. on the other hand,
The uniplanar line is a line in which both the signal line and the ground line are formed on the surface of the substrate, and is characterized by not requiring a via hole.

Microstrip lines are widely used in MMICs formed on GaAs substrates.
IEICE Technical Report MW94-72 (199
4). Further, it has been reported that the uniplanar line is formed on an InP substrate. For example, the Institute of Electronics, Information and Communication Engineers, IEICE Technical Report ED92-116 (1)
993).

Schematic structural views of these conventional transmission lines are shown in FIGS. 3 and 4. FIG. 3 is an example of a microstrip line. Various elements 303 such as transistors, diodes, and capacitors are formed on a GaAs substrate 304, and the surface of the element 303 and the surface of the substrate 304 on which no element is formed are covered with an insulating film 306. A wiring layer 307 is formed on the insulating film 306, and the wiring layer 307 is a signal line 3 through which a high frequency signal propagates.
It becomes 01. The wiring layer 307 is connected to the element 303 through a contact hole 308 formed in the insulating film 306. As the wiring layer 307, for example, a laminated structure of Ti and Au is generally used. On the other hand, the ground electrode 302
The ground line 311 formed on the back surface of the substrate 304 is connected by a via hole 310.

FIG. 4 shows an example of a uniplanar line. Figure 3
Unlike the microstrip line of the above, the signal line 401 and the ground line 402 are all the insulating film 4 formed on the substrate 404.
It is formed only on 06.

[0008]

In any of the lines, the end portions of the wiring layers constituting the signal line and the ground line shown in the drawing are wire-bonded for connection with an external circuit, It is necessary to press a probe (contact needle) for high-frequency signals for the test. However,
Since the wiring layers that compose the signal lines of the microstrip line, the signal lines of the uniplanar line, and the ground line are formed on the insulating film, their adhesion strength is comparatively weak, and they are pulled by the bonded wire or scraped by the probe. Therefore, there is a problem that the wiring layer is peeled off.

The present invention has been made to solve the above problems, and an object of the present invention is to improve the reliability of an integrated circuit by preventing the wiring layer from peeling during wire bonding or circuit inspection. That is.

[0010]

According to a first aspect of the present invention for solving the above-mentioned problems, a semiconductor active layer for forming a circuit element and another external element are provided on a semi-insulating semiconductor substrate. I in an integrated circuit and the wiring layer is formed to have a pad portion to be subjected to the wire bonding between the semiconductor substrate is a InP substrate, a semiconductor active layer containing no P
nAlAs, InGaAs and other semiconductor layers or those
The wiring layer in the pad portion is bonded to the semiconductor substrate through the reinforcing layer and the semiconductor active layer which have interacted with the semiconductor active layer by the alloying treatment formed on the semiconductor active layer. It is characterized by

[0011]

[0012]

The invention of claim 2 is characterized in that the wiring layer is made of Au or a metal containing Au, and the reinforcing layer is made of AuGe or a metal containing AuGe. Further, the invention of claim 3 is characterized in that the wiring layer is a signal line of a microstrip line, and the invention of claim 4 is a signal line of a uniplanar line and a ground line.

[0014]

The present inventors have noticed that in the conventional integrated circuit, since the pad portion of the wiring layer is formed on the insulating film, the bonding strength of the wiring layer to the substrate is low. In the above invention of claim 1, the reinforcing layer was formed which caused the semiconductor active layer and the interaction (alloy) by alloying the semiconductor active layer, since the bonding wiring layer on the reinforcing layer, wiring The bond strength of the layer to the semiconductor active layer was improved. That is, the reinforcing layer and the semiconductor active layer are firmly bonded by alloying, and since the wiring layer and the reinforcing layer are both metal, the bonding strength between the wiring layer and the reinforcing layer is also improved. As a result, the bonding strength of the wiring layer to the semiconductor substrate via the semiconductor active layer was improved.

[0015]

In particular, when the semi-insulating semiconductor substrate was an InP substrate, the following defects became apparent. That is, AuG
The present inventors have for the first time found that, when a reinforcing layer containing e is directly formed on an InP substrate by an alloying treatment, InP in the substrate is decomposed and In atoms are deposited on the surface of the reinforcing layer. It was concluded that the In deposited on the surface of the reinforcing layer causes the decrease in the adhesion strength with the wiring layer.

Therefore, in order to prevent the precipitation of In on the surface of the reinforcing layer, a semiconductor active layer containing no P is formed on the semiconductor substrate, and the reinforcing layer is alloyed on the semiconductor active layer. Form. As described above, the semiconductor active layer integrally bonded to the semiconductor substrate has a function of preventing In from permeating into the reinforcing layer due to decomposition of InP of the semiconductor substrate during alloying treatment of the reinforcing layer. . Further, if the semiconductor active layer does not contain P, even if it is an In compound, In atoms do not separate during alloying treatment of the reinforcing layer, so In atoms do not precipitate on the surface of the reinforcing layer. . Therefore, the reduction of the bonding strength between the reinforcing layer and the semiconductor active layer is prevented.

When the semiconductor substrate is InP, the semiconductor active layer forming active elements and the like is InAlAs, InGa.
In many cases, As or a laminated structure of both is used. During the process of growing the semiconductor active layer for forming the active element, the semiconductor active layer of the same material may be formed also in the portion corresponding to the pad portion of this wiring layer. .

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on specific embodiments. (First Embodiment) FIG. 1 shows a first embodiment of the present invention, in which the present invention is applied to a uniplanar line on a semi-insulating InP substrate 104. In the figure, a schematic view of the vicinity of an end of a transmission line constituted by a signal line 101 as a wiring layer 107 and a ground line 102 is shown. InAlAs and InGa capable of forming a transistor on the InP substrate 104
An MMIC in which active elements such as transistors and passive elements such as capacitors and resistors are arranged is prepared using a wafer on which an active layer 110 made of an As laminated film is formed. Where M
In the manufacturing process of the MIC, the active layer 110 is left in the form of islands at the end portions of the transmission line, that is, the portions corresponding to the pad portions W1, W2, and W3, as shown in FIGS. I will let you.

A reinforcing layer 109 is formed on the active layer 110 remaining in an island shape, and heat treatment is performed to alloy it. Here, a laminated film of AuGe / Ni / Au was used as the material of the reinforcing layer 109, and heat treatment was performed at 360 ° C. for 2 minutes. Subsequently, the intermediate wiring 105 made of Au is laminated. In this embodiment, the intermediate wiring 105 is formed at the end of the transmission line, that is, the pad portions W1, W2, W3 for the purpose of increasing the mechanical thickness and increasing the mechanical strength, but peeling is prevented. From the original purpose, the intermediate wiring 105 is not always necessary for the pad portions W1, W2, W3 and can be omitted. The reinforcing layer 109 and the intermediate wiring layer 105 can be formed at the same time as the step of forming the ohmic electrodes in the other elements that form the MMIC, and thus no special step is required.

Further, after the surface is covered with the insulating film 106, the elements to be wired and the pad portions W1 and W of the wiring layer 107 are formed.
2, a window is opened in the insulating film 106 corresponding to W3, and a wiring layer 107 made of, for example, Ti / Au is formed. The Ti is used here because it is used as a bias electrode when the wiring layer 107 is formed by electroplating with gold.

Through the above manufacturing process, as shown in the drawing, the wiring layer 1 including the signal line 101 and the ground line 102 is formed.
In the pad portions W1, W2, W3, which are the end portions of 07,
The wiring layer 107 can be firmly bonded to the InP substrate 104 via the reinforcing layer 109 and the semiconductor active layer 110. Thus, in the pad portions W1, W2, and W3, the reinforcing layer 109 and the intermediate wiring 105 that have interacted with the active layer 110.
Further, since the wiring layer 107 is entirely formed by stacking the metals, the bonding strength can be increased as compared with the bonding between the metal and the insulator. Therefore, peeling of the wiring layer 107 can be prevented.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention, which is an example in which a microstrip line is formed on a semi-insulating GaAs substrate 204. In the micro trip line, since the ground electrode 202 is connected to the ground line 211 on the back surface of the substrate 204 via the via hole 210, the adhesion strength of the ground electrode 202 is relatively strong. Therefore,
The present invention is applied to the signal line 201 formed on the surface of the substrate 204.

The basic manufacturing method is the same as that of the first embodiment. The reinforcing layer 209 is formed on the GaAs substrate 204, alloyed, and then the intermediate wiring layer 205 is formed. After that, the insulating film 206 is laminated to form the wiring layer 20 of the insulating film 206.
After opening a window in a portion corresponding to the pad portion of 7, the wiring layer 207 is laminated. As a result, the wiring layer 207 formed on the insulating film 206 is bonded to the intermediate wiring layer 205 at the pad portion W1.

In the case of using the GaAs substrate 204, since the precipitation of In, which is a problem when using the InP substrate 104, does not occur on the surface of the reinforcing layer 209, the wiring layer 2
In the pad portion W1 which is the end portion of 07, it is not necessary to leave the active layer, and the reinforcing layer 209 may be directly bonded to the GaAs substrate 204.

[Brief description of drawings]

FIG. 1 is a sectional view of an integrated circuit showing a first embodiment of the present invention.

FIG. 2 is a sectional view of an integrated circuit showing a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a conventional micro trip line.

FIG. 4 is a sectional view of a conventional uniplanar line.

[Explanation of symbols] 101, 201 ... Signal line 102, 202 ... Ground wire 104, 204 ... Semiconductor substrate 105, 205 ... Intermediate wiring layer 106, 206 ... Insulating film 107, 207 ... Wiring layer 109, 209 ... Reinforcing layer 110 ... Semiconductor active layer

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A 61-171122 (JP, A) JP-A 63-15436 (JP, A) JP-A 59-76437 (JP, A) JP-A 59- 66173 (JP, A) JP-A-59-112654 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21 / 28,21 / 60 H01L 23 / 12-23 / 15

Claims (4)

(57) [Claims] 1. An integrated circuit in which a semiconductor active layer for forming a circuit element and a wiring layer having a pad portion for wire bonding with another external element are formed on a semi-insulating semiconductor substrate. In, the semiconductor substrate is an InP substrate, and the semiconductor active layer does not include P. InAlAs, InG
aAs or other semiconductor layers or their laminated structures
The wiring layer in the pad portion is bonded to the semiconductor substrate via the reinforcing layer and the semiconductor active layer, which have been caused to interact with the semiconductor active layer by an alloying treatment formed on the semiconductor active layer. An integrated circuit characterized by being provided. 2. The integrated circuit according to claim 1 , wherein the wiring layer is made of Au or a metal containing Au, and the reinforcing layer is made of AuGe or a metal containing AuGe. 3. The wiring layer is a signal line of a microstrip line for transmitting a high frequency signal in which a signal line is formed on a front surface of the semiconductor substrate and a ground line is formed on a back surface of the semiconductor substrate. The integrated circuit according to claim 1 . Wherein said wiring layer, according to claim 1, characterized in that the signal line and the ground line of Yunipurena lines for transmitting a high frequency signal which is formed with the signal line ground line both surfaces of said semiconductor substrate Integrated circuit.