JP3523458B2 - High avalanche withstand MOSFET and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the technical field of power MOSFETs, and more particularly, to a power MOSF driving an inductive load.
The present invention relates to a technique for improving the avalanche resistance of ET.

[0002]

2. Description of the Related Art MO, which is one of the insulated gate semiconductor devices
SFET can be driven with low power, can perform high-speed switching operation, and has advantages such as high breakdown resistance against inductive load compared to bipolar transistors, so in recent years, large currents such as switching power supplies, It is used in many devices that require high breakdown voltage.

A circuit for measuring the avalanche breakdown resistance of such a power MOSFET is shown by reference numeral 200 in FIG. 8 (a).

This measuring circuit 200 has an n-channel power
This is a circuit for measuring the avalanche breakdown withstanding capacity of the MOSFET 202. One end of the inductive load 205 is connected to the drain terminal of the n-channel power MOSFET 202, the DC power supply 204 is connected between the other end and the source terminal, and the gate terminal is connected. A pulse power supply 206 is connected between the source terminals via a resistor 207.

When the DC power supply 204 is operated, a DC voltage is applied between the drain terminal and the source terminal, the pulse power supply 206 is activated in that state, and a positive voltage is applied to the gate terminal, the n-channel power MOSFET 202 is turned on. become.

A voltmeter and an ammeter (not shown) are connected to the drain terminal of the n-channel power MOSFET 202, and the drain voltage V _D and the drain current (current flowing through the inductive load 205)
When I _D is measured, the operating state of the MOSFET 202 is
As shown in (b). V _G is the gate voltage.

When the MOSFET 202 is in the OFF state, the drain voltage V _D is the voltage of the DC power source 204, and when it turns from the OFF state to the ON state, it falls to the conduction voltage of the MOSFET 202. After being turned on, the drain current I _D gradually increases. When the gate voltage V _{G is set} to zero (V) when the drain current I _D has risen to the rated current, the MOSFE
T202 changes from the ON state to the OFF state.

At this time, a large counter electromotive force is generated in the inductive load 205, a reverse bias voltage is applied between the drain and source, the drain voltage V _D greatly exceeds the voltage of the DC power source 204, and the drain and source of the MOSFET 202 are An avalanche current flows through.

The MOSFET 202 has a diffusion structure as shown in FIG. 1C, and the drain region 222 is formed by the N ^--type silicon single crystal layer of the silicon substrate 221. The MOSFET 202 includes a p ^{+ type} main diffusion region 22.
4 and p ^- the form of the channel diffusion layer 225, the main diffused region 22
N diffused from the surface 4 and the surface of the channel diffusion layer 225.
^{A + type} source diffusion layer 226, and a gate insulating film 231, a gate electrode film 232, an interlayer insulating film 233, and a source electrode film 234 are formed in this order on the surface thereof.
A drain electrode film 235 is formed on the back surface.

In the MOSFET 202, the source diffusion layer 226 and the main diffusion layer 224 are short-circuited by the source electrode film 234, and the channel diffusion layer 225 is electrically conductive with the source electrode film 234 via the main diffusion region 224. It is configured to be placed in position.

Since the breakdown voltage of the pn junction formed by the N ⁻ layer of the silicon substrate 221 which is the drain region and the channel diffusion layer 225 is low, the MOSFET 202 changes from the ON state to the OFF state.
When the high voltage is applied to the channel diffusion layer 225, the pn junction breaks down and the avalanche current 230 is generated.
Flowing in.

Since the source diffusion layer 226 is diffused on the channel diffusion layer 225, an avalanche current 230 is generated.
When flowing in the channel diffusion layer 225, the latent resistance 2 sandwiched between the source diffusion layer 226 and the drain region 222 is
Although passing through the portion 40, the latent resistance 240 has a large resistance value, so that the potential difference between the end portion of the channel diffusion layer 225 and the source electrode 234 tends to increase due to the flow of the avalanche current 230.

On the other hand, in this MOSFET 202, a parasitic NP having the drain region 222 as a collector, the channel diffusion layer 225 as a base, and the source diffusion layer 226 as an emitter.
Although the N-transistor 241 is formed, the potential difference between the channel diffusion layer 225 and the source electrode 234 caused by the flow of the avalanche current 230 causes the parasitic NPN.
The polarity is such that the base-emitter of the transistor 241 is forward-biased, and when the potential difference becomes large enough to allow the base current to flow, the parasitic NPN transistor 241 turns on.
I will do N.

The parasitic NPN transistor 241 is turned on.
However, when the collector current flows, the drain region 22
A large current instantaneously flows from 2 to the source diffusion layer 226.

In the power MOSFET, a rectangular cell 228 is generally formed by a main diffusion layer 224 and a channel diffusion layer 225 as shown in FIG. 10 showing a plane and a cross section taken along line MM, and a rectangular cell 228 is formed on the surface of a silicon substrate 221. , The cells 228 are arranged in an island shape, and the parasitic NPN transistor 241 is formed over the entire circumference of the channel diffusion layer 225 of each cell 228.

In this case, each channel diffusion layer 225 is formed by diffusion from the rectangular window portion, and the pn junction formed with the drain region 222 is at the four corners 241 of each cell 228 when viewed from the cross section. Spherical connection,
The four side portions 242 form a cylindrical joint.

Since the breakdown voltage of the spherical junction portion of the pn junction is lower than the breakdown voltage of the cylindrical junction, the MOSFET 2
When 02 turns from ON to OFF, the spherical bonding portion breaks down and an avalanche current flows in that portion. for that reason,
The four corners of the parasitic NPN transistor 241 are turned on, current concentrates on the spherical junction, and the four corners 241 are destroyed.

[0018]

SUMMARY OF THE INVENTION The present invention was created in order to solve the above-mentioned disadvantages of the prior art, and an object thereof is to provide a MOSFET having a high avalanche breakdown resistance.

[0019]

In order to solve the above-mentioned problems, the invention according to claim 1 has a semiconductor substrate and a drain region formed of the semiconductor substrate, and the conductivity is different from that of the drain region. Type main diffusion layers are separated from the semiconductor substrate surface and are diffused in an island shape, and channel diffusion layers of the same conductivity type as the main diffusion layers are diffused around the respective main diffusion layers to form the drain regions. Source diffusion layers of the same conductivity type are diffused from the surfaces of the main diffusion layers and the channel diffusion layers, and a voltage is applied to the gate electrode film provided on the channel diffusion layers to invert the surface of the channel diffusion layers. A MOSFET configured to allow a current to flow between the drain region and each of the source diffusion layers,
An avalanche breakdown inducing layer having the same conductivity type as the drain region and a higher impurity concentration than the drain region is provided in the drain region between the cylindrical junction portions of the pn junction formed by the channel diffusion layers and the drain region. Is provided in front
The impurity concentration in the avalanche breakdown inducing layer is
The position where the impurity concentration in the region is reduced to twice the
The diffusion depth is 2.5 × 10 ^-6 m or more,
It is characterized by

The invention according to claim 2 is the MO according to claim 1.
In the SFET, the surface concentration of the avalanche breakdown inducing layer is 10 times or more the concentration of the drain region.

According to a third aspect of the invention, a semiconductor substrate and
And a drain region composed of a semiconductor substrate,
The main diffusion layer having a conductivity type different from that of the drain region is
The same conductivity type as the main diffusion layer, diffused from the surface of the conductive substrate
Channel diffusion layer is diffused around each of the main diffusion layers.
And a source diffusion layer having the same conductivity type as the drain region.
Diffuse from the surface of each of the main diffusion layers and each of the channel diffusion layers
And a gate electrode film provided on the channel diffusion layer
Voltage is applied to the surface to invert the surface of the channel diffusion layer.
Current between the drain region and each of the source diffusion layers
Multiple cells spaced apart from each other configured to allow
However, the cells are formed in a square shape, and the cells are arranged in a matrix.
The MOSFET located in the same area as the drain region.
The conductivity type is higher in impurity concentration than the drain region.
Having a plurality of Lanche breakdown inducing layers, each of the avalanche inducement layers
The raised layer is formed to have a length substantially equal to one side of each cell,
The channel diffusion layer and the drain region of each cell,
Between the cylindrical joint portions of the pn junction formed by
It is arranged in parallel to each of the cells in the center of the in-region,
The avalanche inducing layer causes the cha of each cell to
Pn junction formed by the drain diffusion layer and the drain region
Breakdown voltage of a cylindrical junction is that of a spherical junction
It is characterized by the following .

According to a fourth aspect of the present invention, a semiconductor substrate and
And a drain region composed of a semiconductor substrate,
The main diffusion layer having a conductivity type different from that of the drain region is
The same conductivity type as the main diffusion layer, diffused from the surface of the conductive substrate
Channel diffusion layer is diffused around each of the main diffusion layers.
And a source diffusion layer having the same conductivity type as the drain region.
Diffuse from the surface of each of the main diffusion layers and each of the channel diffusion layers
And a gate electrode film provided on the channel diffusion layer
Voltage is applied to the surface to invert the surface of the channel diffusion layer.
Current between the drain region and each of the source diffusion layers
Multiple cells spaced apart from each other configured to allow
However, the cells are formed in a square shape, and the cells are arranged in a row.
MOs that are arranged side by side and staggered in the vertical direction
SFET , which has the same conductivity type as the drain region,
Avalanche breakdown with higher impurity concentration than the rain region
Each of the avalanche inducing layers has a plurality of initiating layers.
Formed by the channel diffusion layer and the drain region of the cell
In the drain region between the cylindrical junctions of the pn junction
The center position between the facing parts of each cell
Placed parallel to each of the cells
A channel inducing layer of each cell and
Cylindrical junction of pn junction formed with the drain region
The breakdown voltage of the part is kept below the breakdown voltage of the spherical junction.
It is characterized by being

When the MOSFET has the above structure, the breakdown voltage of the cylindrical junction portion of the pn junction formed by the channel diffusion layer and the drain region can be reduced.

According to the above-described structure of the present invention, when a MOSFET is formed by using a semiconductor substrate as a drain region, a main diffusion layer having a conductivity type different from that of the drain region and a channel diffusion layer having the same conductivity type as the main diffusion layer are formed. And a source diffusion layer having the same conductivity type as the drain region are diffused from the semiconductor substrate surface, and when a voltage is applied to the gate electrode provided on the channel diffusion layer to invert the channel diffusion layer surface, A current can be passed between the drain region and the source diffusion layer.

When the load connected to this MOSFET is inductive, the pn formed by the drain region and the channel diffusion layer is formed by the electromotive force generated in the inductive load when the MOSFET turns from the ON state to the OFF state. The junction undergoes avalanche breakdown, causing an avalanche current to flow through the MOSFET in the OFF state.

Generally, the main diffusion layer of the power MOSFET is diffused from the rectangular window portion, and a large number of them are independently arranged in an island shape in the semiconductor substrate, and the channel diffusion layer is
It is provided in contact with each main diffusion layer and has a substantially constant width around the main diffusion layer.

Therefore, the pn junction formed by the channel diffusion layer and the drain region becomes a cylindrical junction at the side portion and a spherical junction at the corner portion. When the breakdown voltage of the pn junction formed by the same diffusion layer is compared, the breakdown voltage of the spherical junction portion of the pn junction is lower than the breakdown voltage of the cylindrical junction portion, so that the avalanche current is generated by the electromotive force of the inductive load. When the current flows, the breakdown of the pn junction is concentrated in the spherical junction portion, and the current is concentrated in the spherical junction portion, and the four corners of the channel region are destroyed.

In the MOSFET of the present invention, the breakdown voltage of the cylindrical junction portion of the pn junction formed by the channel diffusion layer and the drain region is set to be equal to or lower than the breakdown voltage of the spherical junction portion. Avalanche breakdown occurs in a cylindrical junction portion having a larger area than that of, and a current flows in that portion, so that the breakdown resistance of the MOSFET is improved.

In order to make the breakdown voltage of the cylindrical junction portion lower than the breakdown voltage of the spherical junction portion, for example, the same conductivity type as that of the drain region is provided between the cylindrical junction portions of the cells in the drain region. It is possible to provide an avalanche breakdown inducing layer having an impurity concentration higher than that of the drain region.
In this case, if the avalanche breakdown inducing layer is not provided between the spherical junction portions of the drain region, the expansion of the depletion layer at the cylindrical junction portion is suppressed, and the breakdown voltage at that portion is lowered.

This will be described with reference to FIGS. 7A and 7B. As shown in FIG. 7A, an avalanche breakdown inducing layer is formed in the drain region between the cylindrical junctions formed by the channel diffusion layers. When provided, a reverse bias voltage is applied to the pn junction formed by the channel diffusion layer and the drain region, and when the depletion layer spreads, the depletion layer is directed toward the avalanche breakdown inducing layer, and the cell A ₁ and the cell Although it extends from A ₂ and into the drain region, it becomes difficult to extend in the avalanche breakdown inducing layer, the electric field strength at that portion increases, and avalanche breakdown easily occurs, so that the breakdown voltage decreases.

On the other hand, if the avalanche breakdown inducing layer is not provided between the spherical junction portions, the extension of the depletion layer in that portion is not suppressed and the breakdown voltage does not change.

When the avalanche breakdown inducing layer is not provided as in the prior art, the depletion layer extending from the adjacent cells B ₁ and B ₂ into the drain region is formed as shown in FIG. 7B. , And they come into contact with each other at an intermediate position of the cylindrical joint portion and integrally spread with each other toward the back surface of the substrate. When the depletion layers contact each other, the end of the depletion layer does not exist on the surface of the drain region, the depletion layer ends easily extend downward, and the electric field strength hardly increases on the surface of the drain region. Therefore,
Avalanche breakdown does not easily occur on the surface of the drain region.

On the other hand, since the distance between the channel diffusion layers is large between the opposing spherical junctions, even if the depletion layer of the cylindrical junction is in contact, it is not in contact with the spherical junction, and the drain region surface is depleted. The layer ends are present. In that state, since the electric field strength at the edge of the depletion layer tends to be high, the breakdown voltage of the spherical junction is generally lower than the breakdown voltage of the cylindrical junction. Therefore, if the depletion layer does not come into contact with the cylindrical junction portion, or if the depletion layer does not extend downward even if it comes into contact, the breakdown voltage of the cylindrical junction portion can be reduced.

When the junction breaks down and an avalanche current flows in the MOSFET, the current concentrates only on the broken spherical junction. In the MOSFET as a whole, the area of the spherical junction is smaller than the area of the cylindrical junction. Therefore, if only the spherical junction yields, avalanche breakdown is likely to occur.

On the other hand, if the breakdown voltage of the cylindrical junction is made lower than the breakdown voltage of the spherical junction and the avalanche current is allowed to flow through the cylindrical junction, the current density in the MOSFET is reduced, so that the avalanche current is reduced. Breakage resistance is improved.

In this case, it is not necessary that the breakdown voltage of all the cylindrical junctions be lower than the breakdown voltage of the spherical junctions. It is sufficient to disperse the avalanche current to such an extent that the avalanche current is dispersed and is not destroyed.

Further, the breakdown voltage of the cylindrical junction portion may not be lower than the breakdown voltage of the spherical junction portion. If the breakdown voltage of the cylindrical junction is lowered to near the breakdown voltage of the spherical junction, both the spherical junction and the cylindrical junction will break down, and the flowing avalanche current will be dispersed. Will improve.

In the present invention, between the cylindrical junction portion of the pn junction formed by each channel diffusion layer and the drain region,
By providing an avalanche breakdown inducing layer having a higher concentration than that of the drain region and suppressing the spread of the depletion layer on the surface of the drain region, the breakdown voltage of the cylindrical junction portion is lowered.

The relationship between the surface concentration of the avalanche breakdown inducing layer and the avalanche breakdown voltage is shown in the graph of FIG. The vertical axis represents the breakdown voltage, and the horizontal axis represents the concentration. The surface concentration of the avalanche breakdown inducing layer is represented by the magnification of the concentration of the drain region. In FIG. 9, the diffusion depth is 2 μm, 2.5 when the diffusion depth is set at a position where the impurity concentration of the avalanche breakdown inducing layer is reduced to twice the impurity concentration of the drain region.
Shown are three avalanche breakdown-inducing layers of μm and 3 μm.

As can be seen from this graph, the higher the surface concentration of the avalanche breakdown inducing layer, the more effective it is. If the surface concentration of the avalanche breakdown inducing layer is 10 times or more that of the drain region, the breakdown voltage of the cylindrical junction will not be concentrated by the avalanche current. Can be reduced to

In the three graphs of FIG. 9, the distance between adjacent cylindrical joint portions is made constant and the diffusion depth of the avalanche breakdown inducing layer is changed.
Since the avalanche breakdown inducing layer and the cylindrical junction are close to each other, the breakdown voltage becomes lower as the diffusion depth becomes deeper.
In this graph, it can be seen that 2.5 μm (2.5 × 10 ⁻⁶ m) or more is effective.

[0042]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described together with manufacturing steps with reference to the drawings. Reference numeral 51 in FIG.
It is a silicon semiconductor substrate and is formed by depositing an N ⁻ epitaxial layer on an N ⁺ single crystal substrate. A primary oxide film 52 made of a silicon thermal oxide film is formed on the entire surface of the surface of the silicon substrate 51 (N ⁻ epitaxial layer side) (in this figure and the following figures,
A thin film such as a silicon thermal oxide film formed on the back surface is omitted.)

Next, through a photolithography process and an etching process, a large number of square windows 53 are formed at predetermined positions on the primary oxide film 52 at equal intervals (FIG. 9B), and the primary oxide film is formed. Using 52 as a mask, boron is implanted by ion implantation and thermal diffusion is performed to form a p ⁺ -type main diffusion layer 54 (FIG. 7C). Then, the primary oxide film 52 is removed to expose the surface of the N ⁻ epitaxial layer (drain region) on the surface of the silicon substrate 51 and the surface of the main diffusion layer 54 (FIG. 3D).

A resist film 55 is formed on the surface of the main diffusion layer 54, and a rectangular window 56 is formed between the opposite sides of each main diffusion layer 54 by a photolithography process to expose the N ^- epitaxial layer at that portion. Phosphorus is implanted by ion implantation using the film 55 as a mask to form an n ⁺ -type impurity layer 57 (FIG. 2E).

After removing the resist film 55, the impurity layer 5 is formed.
7 is thermally diffused to form an avalanche breakdown inducing layer 58,
Then, a silicon oxide film is formed by thermal oxidation to form a gate insulating film 59 ((f) in the figure). The concentration of the avalanche breakdown inducing layer 58 is higher than the impurity concentration of the N ⁻ layer.

Next, a gate electrode film 60 made of a highly conductive polysilicon film is formed on the surface of the gate insulating film 59, windows 61 and 67 are formed through a photolithography process and an etching process, and the gate insulating film is formed. 59 and gate electrode film 6
0 is patterned, and at the same time, the surface of each main diffusion layer 54 and the surface of each avalanche breakdown inducing layer 58 are exposed ((h) in the same figure).

The window portion 61 has a square shape larger than the surface of the main diffusion layer 54, and the N ⁻ epitaxial layer surface 52 around the main diffusion layer 54 is exposed in a square ring shape. In that state, the patterned gate electrode film 60
The N ^- epitaxial layer 5 exposed by implanting boron by ion implantation using the mask as a mask
2 When p-type impurities are introduced into the surface and thermal diffusion is performed, a p ⁻ -type channel diffusion layer 63 having a lower concentration than the impurity concentration of the main diffusion layers 54 is formed around each main diffusion layer 54 (( Figure 3
(i)). At this time, the channel diffusion layer 63 enters under the gate insulating film 59 by lateral diffusion.

Next, a patterned resist film 64 is formed on the surface of the main diffusion layer 54 and the channel diffusion layer 63 is exposed by the window portion 65 provided in the resist film 64 (see FIG. (j)) Phosphorus is implanted by ion implantation to form the impurity layer 66 ((k) in the figure), and after removing the resist film 64, thermal diffusion is performed to form the source diffusion layer 69. By diffusion, the channel diffusion layer 63 is formed under the gate insulating film 59.
And the source diffusion layer 69 enter ((l) in the same figure).

The diffusion process is completed as described above, and the drain region 72 is formed by the N ⁻ layer of the silicon substrate 51.

FIG. 5 is a plan view showing the state of FIG. 3 (l) as a sectional view taken along the line AA. The main diffusion layers 54 have the same size and are diffused from the square-shaped window portions 53 that are arranged parallel to each other at equal intervals, and the main diffusion layers 54 are arranged in islands at equal intervals.

Further, since the square ring-shaped exposed portions 62 of the N ⁻ layer are made to have substantially the same width, the widths of the channel diffusion layers 63 diffused from the portions are also substantially equal. . Therefore, the cells 80 composed of the main diffusion layers 54 and the channel diffusion layers 63 are also arranged in an island shape at equal intervals.

A gate electrode film 59 is formed in a lattice pattern between the cells 80, and the avalanche breakdown inducing layer 5 is formed.
8 is arranged in the center between the cells 80. The length of the avalanche breakdown inducing layer 58 is substantially the same as the length of one side of each cell 80.

The gate insulating film 59 and the gate electrode film 60 on the surface of each avalanche breakdown inducing layer 58 are removed in order to prevent the gate input capacitance from increasing.

From the state shown in FIG. 3 (l), PS is applied to the surface.
A G film is formed on the entire surface and patterned to provide a window 69,
An inter-layer insulation film 68 is formed ((m) in the figure).

Window portion 69 provided in the interlayer insulating film 68
The surface of the source diffusion layer 69 on the surface of the main diffusion layer 54 and the main diffusion layer 54 on which the source diffusion layer 69 is not formed
When the source wiring film 70 made of an aluminum thin film is formed on the surface of the source diffusion layer 69 and the main diffusion layer 54, the source diffusion layer 69 and the main diffusion layer 54 are short-circuited, and the MO of one example of the present invention is exposed.
The SFET 2 is formed ((n) in the figure: the protective film on the surface of the source wiring film 70 is omitted). A drain electrode film 71 made of a metal thin film is formed on the back surface.

In this MOSFET 2, the N ⁻ layer is the drain region 72, the source wiring film 70 is grounded, a positive voltage is applied to the drain electrode film 71, and a positive voltage equal to or higher than the threshold voltage is applied to the gate wiring film 60. When applied, the surface of the p ⁻ type channel diffusion layer 63 is inverted to n ⁺ , the drain region 72 and the source diffusion layer 69 are electrically connected, and a current can flow.

In this MOSFET 2, as can be seen from FIG. 5 which is a plan view of FIG. 3 (l), the window portion 53 (the portion of the main diffusion layer 54 into which the impurities are introduced) is formed in a square shape (FIG. 1 (b)). ),
A channel diffusion layer 63 provided around each main diffusion layer 54.
Are diffused from the square window portion 61 larger than the surface of the main diffusion layer 54. Therefore, the pn junction formed by each channel diffusion layer 63 and the drain region 72 forms a spherical junction at the four corners and a cylindrical junction at the four sides.

The avalanche breakdown inducing layer 58 is formed in each cell 8
The cylindrical junction portion 92 of the pn junction formed by the channel diffusion layer 63 and the drain region 72, which is arranged in parallel with each cell 80 in the center of 0, causes avalanche breakdown as uniformly as possible and causes current concentration. It is supposed not to.

Next, another MOSFET manufacturing method of the present invention will be described. In this manufacturing method, the steps shown in FIGS. 1A to 1D are the same, and the same thin film, the same diffusion layer, and the like as those in the above-described embodiment are designated by the same reference numerals.

After forming the main diffusion layer 54 as shown in FIG. 1D, a gate insulating film 59 and a gate electrode film 60 are formed in this order on the silicon substrate 51 whose surface is exposed (see FIG. 4). (p)), and then, a photolithography process and an etching process are performed to pattern the gate insulating film 59 and the gate electrode film 60, and a window portion is formed on the surface of the N ⁻ epitaxial layer (drain region) between the main diffusion layers 54. 76, and also
The window portion 77 is formed on the surface of the main diffusion layer 54 ((q) in the figure).

The shape of the window 77 on the surface of the main diffusion layer 54 is
The main diffusion layer 5 has a square shape larger than that of the main diffusion layer 54.
Along with the four surfaces, the surface of the N ^- epitaxial layer at a portion indicated by reference numeral 62 around the four surfaces is exposed. In addition, the window portion 76 has a rectangular shape whose longitudinal direction is along each side between the opposing sides of each main diffusion layer 54.

Next, a resist film is formed on the entire surface and patterned, leaving the resist film formed on the surface of the window portion 77 on the main diffusion layer 54, and leaving the window portion 76 on the N ^- epitaxial layer.
The resist film formed on the surface is removed. At this time, in the resist film on the surface of the gate electrode film 60 forming the window portion 76, the portion around the window portion 76 is removed.

Thus, using the patterned resist film 75 as a mask, phosphorus is implanted by ion implantation to form an impurity layer 57 on the surface of the silicon substrate 51 (FIG. 7 (r)). At this time, in the window portion 76 on the surface of the N ⁻ epitaxial layer, the gate electrode film 60 serves as a mask to form the n ⁺ type impurity layer 57.

Next, after removing the resist film 75, thermal diffusion is performed to form an avalanche breakdown inducing layer 58 (FIG. 7 (s)). This state is the same as that of FIG. 2 (h), and thereafter, boron is implanted around the main diffusion layer 54 to form the channel diffusion layer 63 by thermal diffusion (FIG. 3 (i)),
After that, the MOSFET 2 is formed through the same manufacturing process as the process shown in FIG. 3 described above (FIG. 3 (n)).

In the MOSFET 2 described above, the main diffusion layer 54
When the cells 80 formed of the channel diffusion layer 63 and the channel diffusion layer 63 are arranged in an island shape, they are arranged in an array as shown in FIG. 5, but FIG. 3 (l) is a sectional view taken along line BB. As shown in the plan view of FIG. 6, even in the case where the cells 80 are arranged in parallel in an alternating manner, in the center between the opposite sides of each cell 80,
If the avalanche breakdown inducing layer 58 is provided in parallel with each side, the breakdown voltage of the cylindrical junction portion 92 of the channel diffusion layer 63 is reduced, and the avalanche current is not concentrated and flows in the spherical junction portion 91. The breakdown resistance of the MOSFET can be improved.

4 and 5, the avalanche breakdown inducing layer is not provided between the spherical junction portions 91 of the respective channel diffusion layers 63, and the spherical junction portions 91 are not provided.
It is necessary to prevent the breakdown voltage of the device from decreasing.

The avalanche breakdown inducing layer 58 described above is used.
Has been formed by independently providing the step of diffusing the impurity layer 57, but the impurity layer 57 can be diffused when the silicon thermal oxide film is formed later or when the source diffusion layer 69 is diffused. It is also possible to omit the independent diffusion step of the impurity layer 57.

[0068]

EFFECT OF THE INVENTION Since the current due to avalanche breakdown does not flow concentratedly to the spherical joint portion, the breakdown resistance is high.
MOSFET can be obtained.

[Brief description of drawings]

1A to 1D are views for explaining an example of a manufacturing process of a MOSFET of the present invention.

2 (e) to (h): Diagrams for explaining the subsequent manufacturing process.

FIG. 3 (i) to (n): diagrams for further explaining the subsequent manufacturing process.

4 (p) to (s): a diagram for explaining a part of another manufacturing process.

FIG. 5 is a plan view of an example of the MOSFET of the present invention.

FIG. 6 is a plan view of another example of the MOSFET of the present invention.

FIG. 7A is a diagram for explaining the principle of improving the breakdown resistance of the MOSFET of the present invention. FIG. 7B is a diagram for explaining the reason that the breakdown resistance of the MOSFET of the prior art is low.

FIG. 8 (a): Circuit for measuring breakdown strength of MOSFET (b): Current / voltage waveform when a MOSFET having an inductive load turns from ON to OFF (c): Avalanche breakdown of MOSFET Figure

FIG. 9 is a graph showing the relationship between surface concentration and avalanche breakdown voltage.

FIG. 10 is a plan view of a prior art MOSFET.

[Explanation of symbols]

2 ... MOSFET 51 ... Semiconductor substrate 54 ... Main diffusion layer 58 ... Avalanche breakdown induction layer 60 ... Gate electrode film 63 ... Channel diffusion layer 69 ... Source diffusion layer 72 ... Drain region 91 ... Spherical junction Part 92 ... Cylindrical joint

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 652

Claims (4)

(57) [Claims] 1. A main diffusion layer having a semiconductor substrate and a drain region formed of the semiconductor substrate, the main diffusion layer having a conductivity type different from that of the drain region is separated from the surface of the semiconductor substrate and diffuses in an island shape. A channel diffusion layer having the same conductivity type as the main diffusion layer is diffused around each main diffusion layer, and a source diffusion layer having the same conductivity type as the drain region is each main diffusion layer and each channel diffusion layer. When a voltage is applied to the gate electrode film which is diffused from the surface and is provided on the channel diffusion layer and the surface of the channel diffusion layer is inverted, a current can flow between the drain region and each source diffusion layer. A configured MOSFET, wherein a drain region between a cylindrical junction portion of a pn junction formed by each of the channel diffusion layers and the drain region has the same conductivity type as the drain region, A high impurity concentration avalanche breakdown inducing layer is provided than the drain region, the impurity concentration of the avalanche breakdown inducing layer is the drain
Diffusion depth at the position where the impurity concentration in the drain region is doubled
, The diffusion depth is 2.5 × 10 ^-6 m or more.
MOSFET, characterized by being. 2. The MOSFET according to claim 1 , wherein the surface concentration of the avalanche breakdown inducing layer is 10 times or more the concentration of the drain region. 3. A semiconductor substrate, and the semiconductor substrate.
A main diffusion layer having a conductivity type different from that of the drain region.
The channel diffusion layer diffused from the surface of the semiconductor substrate and having the same conductivity type as the main diffusion layer is
A source diffusion layer diffused around each main diffusion layer and having the same conductivity type as the drain region
The diffusion from the surface of each main diffusion layer and each channel diffusion layer
Is, voltage to the gate electrode film provided on the channel diffusion layer
When the surface of the channel diffusion layer is inverted by applying
Apply a current between the drain region and each of the source diffusion layers.
A plurality of spaced apart cells configured to
The cells are formed in a square shape, and the cells are arranged in a matrix.
A MOSFET having the same conductivity type as the drain region,
Also has multiple avalanche breakdown-inducing layers with high impurity concentration.
The avalanche inducing layer has a length of one side of each cell.
And the channel diffusion layer of each of the cells.
And a cylindrical contact of a pn junction formed by the drain region
A pair of cells is formed in the center of the drain region between the junctions.
Are arranged in parallel with each other, and the avalanche inducing layer causes
Pn junction formed by the drain diffusion layer and the drain region
Breakdown voltage of a cylindrical junction is that of a spherical junction
MOSFET, characterized in that it is below. 4. A semiconductor substrate, and the semiconductor substrate.
A main diffusion layer having a conductivity type different from that of the drain region.
The channel diffusion layer diffused from the surface of the semiconductor substrate and having the same conductivity type as the main diffusion layer is
A source diffusion layer diffused around each main diffusion layer and having the same conductivity type as the drain region
The diffusion from the surface of each main diffusion layer and each channel diffusion layer
Is, voltage to the gate electrode film provided on the channel diffusion layer
When the surface of the channel diffusion layer is inverted by applying
Apply a current between the drain region and each of the source diffusion layers.
A plurality of cells that are spaced apart from each other and are formed in a square shape, and the cells are arranged in a horizontal row.
MOSFETs that are stacked and staggered in the vertical direction
A is, with the same conductivity type as the drain region, than the drain region
More have a high avalanche E surrender inducing layer an impurity concentration higher
The avalanche inducing layer is connected to the channel of each cell.
Of the pn junction formed by the diffusion layer and the drain region.
The drain region between the cylindrical joints,
In each of the cells at the central position between the opposite sides of the
Parallel to each other, the avalanche inducing layer causes
Pn junction formed by the drain diffusion layer and the drain region
Breakdown voltage of a cylindrical junction is that of a spherical junction
MOSFET, characterized in that it is below.