JP3529635B2 - Self-destructive semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a physical security technique for tampering with memory contents of a semiconductor integrated circuit having a function of storing and processing important information with high confidentiality, and particularly to an IC (Integrated Circuit) card. thin structure suitable for mounting on the thin semiconductor device and the like
The present invention relates to a semiconductor device equipped with the power supply source .

[0002]

2. Description of the Related Art Semiconductor integrated circuits (I)
In order to analyze the function, operating method, circuit method, circuit pattern, stored data, etc. of the integrated circuit of the semiconductor device in which C) is formed, it has been conventionally provided in the semiconductor device as shown in FIG. Electrode pad 7 (7 for external connection
There is a method of connecting an exploration power supply to -1 to 7-8), supplying an electric signal, and measuring an input / output signal of a terminal signal with an IC tester or the like.

To analyze them, a shape recognition device such as an optical microscope is used to observe the circuit block configuration and the circuit pattern itself from the surface of the semiconductor device, and one step further, using an electron beam tester or the like. Electrode pad 7
There is a method of observing a potential signal that does not appear on the wiring inside the integrated circuit. Therefore, in the current IC card 13, it is possible to open and dissect the IC module 11, read the information inside the IC chip 12, and analyze the contents of the memory to tamper, which is a problem from the perspective of security. .

FIG. 10 shows a contact type I currently used.
FIG. 1 shows a schematic configuration example of the C card 13, in which (a) is a plan view showing a circuit block arrangement in a semiconductor integrated circuit mounted on the IC card 13, (b) is a sectional view, and (c) is a sectional view. 8] is a sectional view showing an example of mounting an IC module. The IC card 13 includes a card body made of a plastic material having the same size as that of the credit card, and the IC module 11.

As shown in FIG. 10 (c), as a replacement of the conventional magnetic card, an IC module 11 composed of an IC chip 12 and a contact electrode base is hot in an IC card 13 having a card thickness of 0.76 mm. It is mounted by a melt adhesive 34. The contact electrode base is formed on the glass epoxy substrate 36 by the contact type IC card 13.
The copper foil of the contact pattern 35 corresponding to the electrode is printed.

The IC module 11 has a glass epoxy substrate 36 having a contact pattern 35 formed thereon, and an I
The C chip 12 is die-bonded, the external connection electrode pad 7 and each contact pattern 35 are wire-bonded by the gold wire 37, and then sealed by the mold resin 38.

As shown in FIG. 10A, the IC chip 1
Above 2 is a data memory (EEPROM or ferroelectric memory) that stores particularly important information such as an encryption code and an authentication code and that is a non-volatile memory capable of electrically writing and collectively erasing a plurality of bits of data. Body memory device or the like) 14, a peripheral circuit 15 including a voltage booster circuit for writing / erasing the same, a read-only program memory (composed of ROM or the like) 16 in which a predetermined control program is stored, A central processing unit (CPU) that reads out a control program stored in the program memory 16, performs processing according to the control program, and controls arithmetic operations and rewriting of data stored in the nonvolatile memory.
A random access memory (RAM) 18, which is a volatile memory for temporarily storing data, and a security authentication microprocessor (MPU) 19 are formed. A data bus and electrode wiring (not shown) for supplying power are provided around these.

Further, a reader separate from the IC card 13
In order to supply an electric signal and a driving voltage from the writer to the IC chip 12, a total of eight external connection electrode pads 7 made of metal such as aluminum are formed in the vicinity of the ends of the two opposite sides of the IC chip 12. Has been done. Therefore, the electrical signal is exchanged with the outside of the chip by the external connection electrode pad 7 on the IC chip 12 through the contact pattern 35 on the card surface. When reading or writing an electric signal from the outside, cryptographic processing of the electric signal is performed by the microprocessor 19 for authentication or cryptographic processing to enhance security.

Particularly, the data memory 14 in the IC chip 12 stores important data such as a protocol necessary for communication, a number code for authentication, and a password necessary for security. Therefore, from the viewpoint of preventing forgery and falsification of the IC card, these codes and data, as well as information such as circuit blocks and circuit patterns constituting the semiconductor device, are prevented from being read by a third party. There is a need.

However, in the conventional semiconductor device as shown in FIG. 10, the circuit block is started by the optical observation from the top, the functional element circuit, the data memory 14, the program memory 16, and the authentication microprocessor 19 are included. The arrangement can be seen, and in addition, the contents of the memory device can be easily read out by the probing measurement using the electron beam, and the authentication microprocessor 1
It was possible to cause 9 to run out of control by trigger, causing it to malfunction and skipping the authentication process itself.

Therefore, as a method for solving the above problems, the authors proposed a self-destruction type semiconductor device having a built-in thin power source (Japanese Patent Application No. 10-110527).
FIG. 11 shows a basic circuit block configuration diagram of the self-destruction type semiconductor device. Semiconductor integrated circuit 1 on semiconductor substrate 9
In addition, as shown in FIG. 10 described above, the data memory 14 and the program memory 1 necessary for the original IC card function are included.
6, central processing unit 17, random access memory 1
8. An authentication microprocessor 19 is formed, but it is omitted here.

In this configuration, in addition to the above configuration, a destruction circuit that destroys memory information or a destruction circuit in which a fuse / anti-fuse is provided in the signal wiring path is added as the destruction circuit 2, and the semiconductor substrate is further added. A breakdown capacitor 3, a control circuit or element 4, and a voltage change detection circuit 5 are formed on the circuit 9. Then, the terminal 10 whose terminal voltage is constantly monitored by the voltage change detection circuit 5
Further, a thin power supply source 6 (in the current lithium primary battery, a voltage of 3.6 V and a thickness of 0.1 mm) is connected and arranged.

As the power source for driving the destruction circuit 2, the electric charge accumulated in the large-capacity destruction capacitor 3 formed on the semiconductor substrate 9 is used. In the normal operation state, a power supply source 6 is connected to the capacitor 3 through a control circuit or an element 4, and the output voltage of the power supply source 6 is monitored by the voltage change detection circuit 5 at any time. There is. 12 and 13 show the basic structure of the self-destruction type semiconductor device described above. FIGS. 12 and 13 (a) are plan views, and FIG. 13 (b) is a sectional view in the case of FIG. 13 (a). Is.

The semiconductor substrate 9 on which the IC chip 12 having the self-destructing function is formed is, in addition to the eight electrode pads 7 necessary for the operation as the IC card 13, the electrode pad 10 for connecting to the power supply source 6. Are newly added (contact pairs). FIG. 14A shows a power supply source 6
14B is a sectional view taken along the line AA of FIG. 14A, FIG. 14C is a sectional view taken along the line BB of FIG. 14A, and FIG. It is the CC sectional view taken on the line of (a).

As shown in FIG. 14, the thin power supply source 6 includes a positive electrode collector / terminal plate 21, a positive electrode 22, and a solid electrolyte 2.
3, a negative electrode 24, and a negative electrode current collector / terminal plate 25 are laminated, and the periphery thereof is heat-sealed with a sealing material 26. As a method of mounting the power supply source 6, as shown in FIG. 12, it is possible to dispose the power supply source 6 in parallel with the IC chip 12.

However, from the viewpoint of security of preventing optical surface observation, as shown in FIG.
It is desirable to mount it on the surface of the IC chip 12 on the element formation side via the adhesive film 20. The connection lead 28 of the power supply source 6 and the power supply source connection electrode pad 10 on the semiconductor substrate 9 are spot-welded by an ordinary ultrasonic wire bonding method or laser welding, that is, locally for several seconds 2 seconds.
It is electrically connected by heating to 50 ° C.

With the above arrangement, a third party can
When the power supply source 6 is disconnected for the purpose of tampering with the chip 12, the voltage change detection circuit 5 detects the voltage change, and the control circuit or element 4 which is turned on by the detection signal from the voltage change detection circuit 5. The power of the destruction capacitor 3 is applied to the destruction circuit 2 via the. Therefore, the memory information of the semiconductor integrated circuit 1 to be tampered with is destroyed.

By the way, in the case of mounting the power supply source 6 as shown in FIGS. 12 and 13, two power supplies of the self-destruction circuit are supplied through the positive electrode lead and the negative electrode lead 28 of the thin power supply source 6. It is connected to the source connection electrode pad 10. However, with such a connection method, the electrode pad 10 for connecting the power supply source and the connection lead 28 can be easily understood by a third party. The third party naturally connects another power supply source that generates the same voltage as the power supply source 6 in parallel with the power supply source 6, and then optically shields the surface of the IC chip 12 on the element formation side. The power supply 6 will be removed. In the case of being dissected by such a method, the power supply source 6 is removed while the voltage change detection circuit 5 does not detect the voltage change, so that there is a problem that the self-destruction mechanism does not operate.

[0019]

As described above, FIGS.
In the conventional self-destruction type semiconductor device shown in FIG. 14, the IC is connected via the positive electrode lead and the negative electrode lead 28 of the power supply source 6.
The chip 12 is connected to the power supply source connection electrode pad 10. However, in such a connection method, when another power supply source that generates the same voltage as the power supply source 6 is connected in parallel with the power supply source 6 and then the power supply source 6 is removed, the self-destruction mechanism operates. However, there is a problem that the analysis of the IC chip 12 cannot be prevented.

Therefore, when the power supply source 6 is mounted on the surface of the IC chip 12 on the element formation side, the connection lead 2 is used.
8 and the power supply source connection electrode pad 10 must be invisible from the outside. For this purpose, the connecting lead 2
8 is a positive electrode collector / terminal plate 21 and a negative electrode collector / terminal plate 2
It is necessary to connect to the power supply source connection electrode pad 10 without pulling it out of the plane of 5. However, the electrode pad 10 for connecting the power supply source is directly connected to the positive electrode current collector / terminal plate 21 or the negative electrode current collector / terminal plate 25 by ultrasonic wire bonding (locally above 200 ° C.) or solder. It is not possible. The reason is that the solid electrolyte 23 made of the polymer in the current power supply source 6 is used.
Is decomposed when exposed to a high temperature exceeding 100 ° C., and therefore the positive electrode current collector / terminal plate 2 forming the power supply source 6 is formed.
This is because it is not possible to adopt a connection method that directly heats No. 1 or the negative electrode current collector / terminal plate 25. In addition, since the IC card is used in a severe environment, the non-heated connection method by "fitting" or "sandwiching" has low mechanical strength, and electrical connection reliability cannot be obtained.

The present invention has been made to solve the above problems, and when the important part of the semiconductor integrated circuit is optically shielded by the power supply source, the power supply source is heated to deteriorate the battery life. Secures the tampering of the memory contents of the semiconductor integrated circuit by realizing the electrical connection between the power supply source and the semiconductor integrated circuit without making the electrical connection between the power supply source and the semiconductor integrated circuit invisible. It is an object of the present invention to provide a self-destruction type semiconductor device which can be prevented.

[0022]

Further, a semiconductor integrated circuit in which a semiconductor memory element and a central processing element for processing data stored in the memory element are formed on the same semiconductor substrate, and a power supply source for self-destruction are provided. with the self-destroying semiconductor device, as claimed in claim 1, said semiconductor current
At least part of the memory information of the product circuit is destroyed or reduced.
Even if some of the signal wiring is broken, self-destruction
Destruction circuit (2) to destroy and self-destruction by this destruction circuit
Destruction capacitor that accumulates electric charge for destruction
(3), the first power source connection terminal and the second power source
The voltage between the terminals for connecting the power supply source is monitored and
And a voltage change detection circuit (5) that outputs a detection signal.
Power is supplied through the power supply source connection terminal during normal operation
From the voltage change detection circuit by connecting the source and the destruction capacitor
When a detection signal is output, disconnect the above connection to destroy it.
Circuit or element connecting the capacitor for destruction and the destruction circuit
(4) are respectively provided on the semiconductor substrate, and the power supply source (6a) is the first current collector (21) having the smaller area of the positive electrode current collector and the negative electrode current collector. A connection lead (28a) on the surface, and the first current collector is mounted on the element surface of the semiconductor substrate so as to face the semiconductor integrated circuit. The connection lead and the element surface of the semiconductor substrate The first power supply source connection terminal (10a) formed on the side is joined to obtain an electrical connection with the first current collector, and at the same time, the second current collector having the larger area ( 25) A second power supply source connection terminal (10b) formed in the peripheral portion including the metal thin film (29) covered so as to cover the power supply source and two opposing sides on the element surface side of the semiconductor substrate. And are joined together to obtain an electrical connection with the second current collector. As described above, not only the optical shielding by the power supply source (6a) but also the element surface of the semiconductor substrate can be optically shielded by the coating metal thin film (29) covering the entire power supply source (6a). . Moreover, by sandwiching the connection lead (28a) of the power supply source with the semiconductor substrate and the power supply source mounted thereon, it is possible to make the position where the connection lead is formed optically invisible. As a result, a third party for tampering with the semiconductor device connects another power supply source that generates the same voltage as the power supply source (6a) in parallel with the power supply source (6a) and shields it from the semiconductor substrate. It is possible to prevent removal of the power supply source (6a) for. Further, when connecting the connection lead (28a) and the first power supply source connecting terminal (10a), a spot welding method such as an ultrasonic wire bonding method or a laser welding method is used to perform the spot welding. However, if the connecting lead (28a) is pressed from above by a metal rod that serves as a heat sink and is brought into pressure contact with the first power supply source connecting terminal (10a), the high heat at the time of spot welding is radiated from the heat sink to generate power. It can be non-conductive to the source (6a). The destruction circuit 2 stores in the destruction capacitor.
Applying the accumulated charge to at least one word line.
By, the partial data stored in the non-volatile memory element
Erase bits to destroy memory contents. Also, destruction times
Path (2) is a partial signal wiring path of the semiconductor integrated circuit.
Or antifuse
This fuse or antifuse has a destruction capacitor
By applying the charge accumulated in the
Destroy the path. The control circuit or element (4) is a capacitive termination
One or more semiconductor devices or micromechanics
It consists of a switch. Voltage change detection circuit (5)
Is a series of a first capacitor, a second capacitor, and a first resistor.
The connection terminal voltage applied to both ends of this
Voltage division that is divided and output from the connection point of the 1st and 2nd capacitors
And the voltage division output of this voltage divider is connected to the gate electrode.
The source electrode with a capacitor or
Field effect transistor to which a dynamic capacitor is connected,
And the drain electrode of this field effect transistor.
And a voltage change detection unit including a second resistor connected in series.
Therefore, in the steady state, the voltage-divider section causes
The voltage at which the transistor turns off is divided and output, and the connection terminal voltage is low.
Depending on the bottom, the voltage divided output from the field effect transistor
Field-effect transistor
Destruction capacitor or drive capacity depending on
The charge from the shutter is supplied to the second resistor,
The detection signal is output according to the rise of the end voltage. And the book
According to the invention, the first power supply source connection terminal and the second power supply terminal are connected.
A voltage change detection circuit (5) is provided between the power source connection terminals, and
The voltage between the children is constantly monitored. Memory contents of semiconductor integrated circuit
In order to falsify the metal thin film (29, 29
a) is completely removed from the semiconductor substrate, or
Connection lead (28a) and first power supply source connection terminal
When the connection with (10a) is removed, the voltage change detection
Voltage drop is detected by path (5). This detection signal
The control circuit or element (4) is turned on, and the destruction circuit
(2) and the destruction capacitor (3) are connected. to this
Causes the charge accumulated in the capacitor (3) to be destroyed
It is applied to (2). Therefore, the collection that is about to be tampered with
Some wiring of the product circuit or essential memory data is destroyed
Therefore, tampering is impossible.

Further, a semiconductor integrated circuit in which a semiconductor memory element and a central processing element for processing data stored in the memory element are formed on the same semiconductor substrate, and a power supply source for self-destruction are provided. with the self-destroying semiconductor device, as claimed in claim 2, said semiconductor current
At least part of the memory information of the product circuit is destroyed or reduced.
Even if some of the signal wiring is broken, self-destruction
Destruction circuit (2) to destroy and self-destruction by this destruction circuit
Destruction capacitor that accumulates electric charge for destruction
(3), the first power source connection terminal and the second power source
The voltage between the terminals for connecting the power supply source is monitored and
And a voltage change detection circuit (5) that outputs a detection signal.
Power is supplied through the power supply source connection terminal during normal operation
From the voltage change detection circuit by connecting the source and the destruction capacitor
When a detection signal is output, disconnect the above connection to destroy it.
Circuit or element connecting the capacitor for destruction and the destruction circuit
And (4) on the semiconductor substrate, and the power supply source (6b) has connection leads (28a, 28a, 28b) on both surfaces of the positive electrode current collector (21) and the negative electrode current collector (25). 28b)
And a first current collector (21) having a smaller area of the positive electrode current collector and the negative electrode current collector is mounted on the element surface of the semiconductor substrate so as to face the semiconductor integrated circuit. ,
The connection lead (28a) of the first current collector and the first power supply source connection terminal (10) formed on the element surface side of the semiconductor substrate.
a) and a metal thin film covered with a second current collector (25) having a larger area so as to cover the power supply source, while being electrically connected to the first current collector. (29a) and second
Second power supply source connection terminal (10b) formed on the peripheral portion including the metal thin film and the connection lead (28b) of the current collector, and including two opposing sides on the element surface side of the semiconductor substrate.
And are joined together to obtain an electrical connection with the second current collector. As described above, not only the optical shielding by the power supply source (6b) but also the element surface of the semiconductor substrate can be optically shielded by the coating metal thin film (29a) covering the entire power supply source (6b). . Moreover, by sandwiching the connection lead (28a) of the power supply source with the semiconductor substrate and the power supply source mounted thereon, it is possible to make the position where the connection lead is formed optically invisible. Thereby, a third party for falsification of the semiconductor device connects another power supply source that generates the same voltage as the power supply source (6b) in parallel with the power supply source (6b),
It is possible to prevent the shielding power supply source (6b) from being removed from the semiconductor substrate. Also, the connection lead (28
When connecting a) and the first power supply source connection terminal (10a), a spot welding method such as an ultrasonic wire bonding method or a laser welding method is used, and the connection lead ( 28a) is pressed from above with a metal rod serving as a heat sink, and the first power supply source connection terminal (10
By making contact with a) by pressure, high heat at the time of spot welding can be dissipated from the heat sink and not conducted to the power supply source (6b). Further, since the connection lead (28b) is provided on the second current collector (25) and is joined to the coating metal thin film (29a), the electrical connection on the negative electrode side can be made more reliable. You can

Further, as described in claim 3 , the connection lead is so arranged that its horizontal position does not go out of the plane of the first and second current collectors.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION [First Embodiment] Next, an embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a circuit block configuration diagram of a self-destruction type semiconductor device showing a first embodiment of the present invention, FIG. 2A is a plan view showing an arrangement configuration example of the self-destruction type semiconductor device of FIG.
2B is a plan view of a single IC chip of the self-destruction type semiconductor device of FIG. 1, FIG. 2C is a sectional view taken along line AA of FIG.
2D is a sectional view taken along line BB of FIG.
The same components as those in FIGS. 0 to 14 are designated by the same reference numerals.

On the semiconductor substrate 9a, as the semiconductor integrated circuit 1 necessary for the original IC card function, a nonvolatile data memory (EEPROM or ferroelectric memory) storing particularly important information such as an encryption code and an authentication code. Body memory device) 14 and a peripheral circuit 15 including a voltage booster circuit for writing / erasing the same, a read-only program memory (composed of a ROM etc.) 16, a central arithmetic processing for performing arithmetic and control Part (CPU) 17, random access memory (RAM) 1 as a memory for temporary storage
8. Security authentication microprocessor (MP
U) 19 is formed.

In the present invention, in addition to the above configuration, as the destruction circuit 2, a destruction circuit for destroying memory information or a destruction circuit in which a fuse / anti-fuse is provided in the signal wiring path is added on the semiconductor substrate 9a. In addition, a destruction capacitor 3, a control circuit or element 4 and a voltage change detection circuit 5 are added. In this way, the self-destructive IC chip 12a is formed.

Here, the destruction circuit 2 will be described with reference to a specific example. For example, when a flash EEPROM is used as the data memory 14, a voltage of 12 to 15 V is required to erase the memory information, and an erasing booster circuit that generates such a high voltage is used as the data memory. It is formed as 14 peripheral circuits 15.

When the current lithium primary battery is used as the power supply source 6a, the output voltage is 3.6 V and the thickness is 0.1 mm. In this case, the power supply sources 6a are connected in series and several layers are stacked to generate a required voltage, and the electric power is used to accumulate charges in the destruction capacitor 3. The power supply source 6a is not limited to a lithium battery, but may be a paper battery or the like.

In the flash EEPROM, when a voltage of 12 to 15 V is applied in a pulsed manner to a word line composed of a control gate composed of two-layer polysilicon, electrons are injected from the substrate into the capacitively coupled floating gate electrode. And all bits are rewritten as “1” or “0”. In this way, the memory information can be destroyed.

When a ferroelectric memory device is used as the data memory 14, the voltage for erasing is as low as about 5V, so that electric charges are accumulated from two or more power supply sources 6a connected in series. It is also possible to configure the destruction circuit 2 more simply, such as by directly connecting the large-capacity destruction capacitor 3.

In any case, in the present invention, the electric charge accumulated in the large-capacity destruction capacitor 3 formed on the semiconductor substrate 9a is used as a power supply source for driving the destruction circuit 2. Destruction capacitor 3, a thermal oxide film formed on a semiconductor substrate 9a a (Si0 ₂₎ a structure to be used as an insulating film, it is desirable to have a large capacity. In the case of the thermal oxide film, it is possible to use the characteristics such as its leak current being extremely small, and it is possible to store a large amount of electric charge in the capacitor 3 by the thin power supply source 6a having a low energy density, and further, the energy consumption due to the leak is required. Because it can be reduced.

FIG. 3 (a) is a plan view of the power supply source 6a, FIG. 3 (b) is a sectional view taken along line AA of FIG. 3 (a), and FIG. 3 (c) is B- of FIG. 3 (a). It is a B line sectional view. As shown in FIG. 3, the thin power supply source 6a for accumulating electric charge in the destruction capacitor 3 includes a positive electrode collector / terminal plate 21, a positive electrode 22,
The solid electrolyte 23, the negative electrode 24, and the negative electrode current collector / terminal plate 25 are formed into a laminated structure, and the periphery thereof is heat-sealed with a sealing material 26.

In this power supply source 6a, there is no connection lead 28 that is drawn out from the in-plane of the positive electrode current collector / terminal plate 21 and the negative electrode current collector / terminal plate 25, and the positive electrode current collector / terminal plate. The connection lead 28a made of a metal foil or a metal thin film is joined to the surface 21 of FIG.

As can be seen from FIG. 3, the positive electrode current collector / terminal plate 21 is made smaller in vertical and horizontal dimensions than the negative electrode current collector / terminal plate 25, and the end surface of the power supply source 6a is a metal sheet. It is designed so that it does not cause a short-circuit accident, etc. In the present embodiment, the positive electrode current collector / terminal plate (first current collector) has a small area to prevent a short circuit.
The connection lead 28a is provided on the 21 side.

The connecting lead 28a can be pulled out from any position on the positive electrode collector / terminal plate 21. However, the position is an IC equipped with the power supply source 6a.
It is necessary to take it so as to match the position of the electrode pad 10a for connecting the power supply source, which will be described later, on the chip 12a.

Further, as will be described later, by sandwiching the connection lead 28a between the IC chip 12a and the power supply source 6a mounted thereon, the formation position of the connection lead 28a can be made optically invisible. The position of the connection lead 28a in the horizontal direction (the direction parallel to the paper surface in FIG. 3A) should not extend outside the surface of the positive electrode current collector / terminal plate 21.

The power supply source 6a supplies power to the destruction circuit 2, the destruction capacitor 3, the control circuits to the elements 4, and the voltage change detection circuit 5, and the semiconductor integrated circuit 1 excluding the destruction circuit 2 The external connection electrode pad 7-1.
Power is supplied from the outside through the power supply terminal of 7-8.

For the power supply source 6a as described above, I
The semiconductor substrate 9a on which the C chip 12a is formed has an IC
In addition to the eight external connection electrode pads 7 (7-1 to 7-8) necessary for operation as a card, an electrode pad (first power supply source connection terminal) for connecting to the positive electrode of the power supply source 6a. ) 10a is additionally provided, and a plurality of electrode pads (second power supply source connecting terminals) 10b for connecting to the negative electrode of the power supply source 6a are further provided in two opposite rows.

The voltage change detection circuit 5 constantly monitors the voltage between the power supply source connecting electrode pads 10a and 10b, that is, the output voltage of the power supply source 6a. The control circuit or element 4 has a switch that receives the detection signal output from the voltage change detection circuit 5 as a control input, and this switch does not output the detection signal from the voltage change detection circuit 5 in normal operation. In the state, the NC side shown in FIG. 1 is selected.

As a result, the positive electrode of the power supply source 6a is connected to one end of the destruction capacitor 3 through the connection lead 28a, the power supply source connection electrode pad 10a, and the switch of the control circuit or the element 4 in the normal operation state. To be done. The negative electrode of the power supply source 6a is connected to the other end of the destruction capacitor 3 via a coating metal thin film 29 and a power supply source connection electrode pad 10b described later. Note that, in FIG. 1, the electrode pad 10b for connecting the power supply source is connected to the semiconductor substrate 9
Although all wirings are commonly connected in a, it is sufficient if only one of the pads 10b is an original electrode pad connected to the voltage change detection circuit 5, the destruction capacitor 3 and the destruction circuit 2. Yes, the others may be dummy pads.

Here, a method of mounting the self-destruction type semiconductor device of this embodiment will be described. First, bumps made of gold (Au) or the like are formed on the external connection electrode pads 7-1 to 7-8 on the IC chip 12a. Next, by spot welding such as ultrasonic wire bonding or laser welding,
Electrode pad 10a for connecting power supply source on C chip 12a
And the connection lead 28a of the power supply source 6a are electrically connected.

In order to realize such electrical connection, the surface of the IC chip 12a (semiconductor substrate 9a) on the element formation side (paper surface in FIG. 2B) and the positive electrode collector / terminal of the power supply source 6a. The power supply source connection electrode pad 10a and the connection lead 28a are brought into contact with each other by facing the plate 21, and then the contact point is irradiated with laser light to connect with the power supply source connection electrode pad 10a. Lead 2
Spot welding with 8a.

As described above, the connection lead 28a is made of a metal foil or a metal thin film and therefore has flexibility. Therefore, the electrode pad 10a and the connection lead 28a can be brought into contact with each other while the power supply source 6a is slightly tilted from the horizontal so that the power supply source connecting electrode pad 10a can be seen, and this contact point is visible. Laser irradiation may be performed in such a state.

At this time, if the connection lead 28a is pressed against the electrode pad 10a by pressing the connection lead 28a from above with a metal rod serving as a heat sink only during the spot welding, the high heat at the time of spot welding is radiated from the heat sink to generate electric power. It may not conduct to the supply source 6a. As a result, it is possible to avoid the conventional problem that the solid electrolyte 23 in the power supply source 6a undergoes a chemical reaction due to heating during connection processing, which deteriorates battery life and the like.

After spot welding the electrode pad 10a for connecting the power supply source and the connection lead 28a, the power supply source 6a
Is mounted on the surface of the IC chip 12a on the element formation side by the adhesive film 20. By mounting the power supply source 6a, it is possible to prevent optical surface observation of the IC chip 12a.

Next, the power supply source connecting electrode pad 10b on the IC chip 12a and the negative electrode collector / terminal plate 25 of the power supply source 6a are electrically connected. In order to realize such electrical connection, first, of the power supply source connection electrode pads 10b formed on the IC chip 12a and arranged in two columns, one of the columns on the left side or the right side is connected. The electrode pads 10b and one end of the coating metal thin film 29 made of aluminum foil or the like are brought into contact with each other, and then laser light is irradiated to these contact points to form one row of the electrode pads 10b and the coating metal thin film 29. Spot weld one end.

Subsequently, a covering metal thin film 29 is stretched to cover the power supply source 6a, the other end of the covering metal thin film 29 is brought into contact with the other row of the electrode pads 10b, and these contact points are set. Then, the other row of the electrode pads 10b and the other end of the coating metal thin film 29 are spot-welded with the laser beam.

In this manner, the coating metal thin film 29 is fixed to the IC chip 12a. The negative electrode collector / terminal plate 25 of the power supply source 6a has a covering metal thin film 29 over the entire area thereof.
Since it is in contact with the electrode pad 10b for connecting the power supply source and the negative electrode current collector / terminal plate 2 through the metal thin film 29 for coating.
And 5 are electrically connected.

By adopting such a mounting structure, I
The electrical connection between the C chip 12a and the power supply source 6a can be surely made, and the mechanically weak and reliable connection which is a concern in the conventional non-heating processing connection method by "fitting" or "sandwiching" is required. Low electrical connections can be avoided.

In addition to the optical shielding by the power supply source 6a, the surface of the IC chip 12a on the element formation side can be optically shielded by the coating metal thin film 29 covering the entire power supply source 6a. Moreover, the power supply source 6a
The connection lead 28a at least on the positive electrode side is invisible in the electrical connection between the IC chip 12a and the IC chip 12a.

As a result, a third party whose purpose is tampering with the IC chip 12a is to connect another power supply source that generates the same voltage as the power supply source 6a in parallel with the power supply source 6a.
It is possible to prevent the shield power supply source 6a from being removed from the IC chip 12a.

Next, the external connection electrode pads 7-1 to 7-8 of the IC chip 12a are connected to the contact patterns corresponding to the electrode terminals of the IC card by gold wires, as in the case of FIG. In this way, the mounted IC module is sealed with a mold resin and mounted in a plastic case of the IC card with a hot melt adhesive.

Next, the self-destruction mechanism of the self-destruction type semiconductor device of this embodiment will be described. A third party whose purpose is tampering with the IC chip 12a is to first remove the IC module from the plastic case and then remove the mold resin with a chemical agent. And IC chip 1
In order to perform observation from the element surface side of 2a, the coating metal thin film 29 and the power supply source 6a are removed.

However, in order to remove the power supply source 6a, it is necessary to completely remove the coating metal thin film 29 from the IC chip 12a, or at least part of it, and to connect the connection lead 28a and the power supply source. The connection with the electrode pad 10a must be removed. At this time, the coating metal thin film 29 is completely removed from the IC chip 12a (or the connection between the coating metal thin film 29 and the original electrode pad 10b which is not a dummy pad is removed), or the connection lead 28a and the power supply. When the connection with the source connection electrode pad 10a is removed, the voltage change detection circuit 5 detects the voltage change.

When the voltage change detection circuit 5 detects a voltage change and outputs a detection signal, this detection signal is given to the control circuit or the control input of the switch in the element 4. As a result, the switch in the control circuit or the element 4 is switched to the NO side in FIG. 1 connecting the destruction capacitor 3 and the destruction circuit 2, and the power of the destruction capacitor 3 is applied to the destruction circuit 2. In this way, the self-destruction mechanism is activated and the memory information of the semiconductor integrated circuit 1 is destroyed.

The memory destruction level at this time is determined by simply disconnecting the fuse or antifuse built in the signal wiring path in the integrated circuit from the level at which the memory information is simply erased according to the voltage of the power supply source 6a. It is possible that the semiconductor integrated circuit 1 itself is destroyed.

For example, assuming that one thin lithium primary battery is used as the power supply source 6a, the destruction capacitor 3
The output voltage due to the charges accumulated in the output voltage is about 3.6 V at most, and the destruction circuit 2 executes only the erasing of some memory information. In this case, important confidential information is erased, so the bit information of the memory cannot be leaked to a third party. However, the IC chip 12a that can operate normally remains. The IC chip 12a can be reused if necessary bit information is acquired by another system's fraudulent act and newly written.

In order to avoid the reuse of the IC chip 12a, it is necessary to surely destroy the semiconductor integrated circuit 1 that has been tampered with. In this case, a plurality of thin lithium primary batteries are connected in series and used as the power supply source 6a, so that the output voltage due to the charges accumulated in the destruction capacitor 3 is increased by 3.6V × the number of battery stages, and By supplying an electric current to the destruction circuit 2 formed of a fuse and an anti-fuse portion provided in the integrated circuit 1, some signal wiring of the semiconductor integrated circuit 1 is irreversibly destroyed, thereby
Avoid reuse of the chip 12a.

The current lithium primary battery is used as a power source 6a.
When the IC chip 12a is used as a
Since the battery thickness is 5 mm and the battery thickness is 0.1 mm, under the condition that the IC card thickness does not exceed 0.76 mm, five layers of lithium secondary batteries are stacked as the power supply source 6a (3.6 × 5).
= 18 V), the total is 0.55 mm (= 0.1 mm x
5 + 0.05 mm).

When the power capacity of the power supply source 6a is insufficient, the power capacity is increased by expanding the planar shape of the power supply source 6a in the vertical direction of FIG. It is possible.

[Second Embodiment] FIG. 4A is a plan view showing an arrangement configuration example of a self-destruction type semiconductor device showing a second embodiment of the present invention, and FIG. 4B is the self-destruction. 4C is a plan view of a single IC chip of the semiconductor device of FIG.
4A is a sectional view taken along line AA in FIG. 4A, and FIG. 4D is B in FIG.
4B is a cross-sectional view taken along the line B, and FIG. 4E is a cross-sectional view taken along the line C-C in FIG. 4A. The same components as those in FIGS. 1 to 3 are denoted by the same reference numerals.

Also in the present embodiment, the circuit block configuration of the self-destruction type semiconductor device is the same as that of FIG. FIG. 5 shows a sectional view of the power supply source 6b used in place of the power supply source 6a of the first embodiment, taken along line BB in FIG. 3 (a).

Like the power supply source 6a, the power supply source 6b of the present embodiment also has a positive electrode collector / terminal plate 21 and a positive electrode 2.
2, solid electrolyte 23, negative electrode 24, negative electrode current collector and terminal plate 2
It is formed by the laminated structure of No. 5, and the periphery is heat-welded and sealed by the sealing material 26. In this power supply source 6b, a connection lead 28a made of a metal foil or a metal thin film is joined to the positive electrode collector / terminal plate 21, and a connection made of a metal foil or a metal thin film is made to the negative electrode collector / terminal plate 25. The lead 28b is joined.

Similar to the first embodiment, the connection lead 28
The horizontal position of a is arranged so as not to be out of the plane of the positive electrode current collector / terminal plate 21 and the power supply source connection electrode pad 10a on the IC chip 12b on which the power supply source 6b is mounted. It is arranged to match the position. Also,
In the example of FIGS. 4 and 5, the connection leads 28a and 28b are arranged at the same horizontal position, but it is not necessary that they are at the same location, and it goes without saying that they may be provided at the required locations. .

For such a power supply source 6b, an IC
In the chip 12b, as in the first embodiment, the data memory 14, the peripheral circuit 15, the program memory 16, the central processing unit 17, the random access memory 18, the MPU.
19, destruction circuit 2, destruction capacitor 3, control circuit or element 4, voltage change detection circuit 5, external connection electrode pads 7-1 to 7-8, power supply source connection electrode pad 10a,
10b is formed.

Here, a method of mounting the self-destruction type semiconductor device of this embodiment will be described. First, bumps made of gold or the like are formed on the external connection electrode pads 7-1 to 7-8 on the IC chip 12b. Next, the power supply source connection electrode pad 10a on the IC chip 12b and the connection lead 28a of the power supply source 6b are electrically connected by spot welding such as an ultrasonic wire bonding method or a laser welding method.

In order to realize such an electrical connection, the surface of the IC chip 12b on the element formation side (paper surface in FIG. 4B) and the positive electrode current collector / terminal plate 2 of the power supply source 6b.
1 facing each other, the electrode pad 1 for connecting the power supply source
0a and the connection lead 28a are brought into contact with each other, and the contact point is irradiated with a laser to spot-weld the power supply source connection electrode pad 10a and the connection lead 28a.

As in the case of the first embodiment, by using a metal rod which serves as a heat sink, it is possible to dissipate high heat at the time of spot welding from the heat sink so as not to conduct it to the power supply source 6b. Then, the power supply source 6b is an IC
The chip 12b is mounted on the surface of the chip 12b on which the element is formed by the adhesive film 20.

Next, the power supply source connection electrode pad 10b on the IC chip 12b and the connection lead 2 of the power supply source 6b.
8b is electrically connected. In order to realize such an electrical connection, first, the connection lead 28 is formed by spot welding such as an ultrasonic wire bonding method or a laser welding method.
b and the metal thin film 29a for coating which consists of aluminum foil etc. are joined. In this case, the coating metal thin film 29a serves as a heat sink to avoid heating the power supply source 6b.

Next, of the power supply source connecting electrode pads 10b arranged in two rows on the IC chip 12b, the electrode pad 10b on one of the left or right side and one end of the covering metal thin film 29a are connected. Then, a laser is applied to these contact points to spot weld one row of the electrode pads 10b and one end of the coating metal thin film 29a.

Then, the covering metal thin film 29a is extended so as to cover the power supply source 6b, and the other end of the covering metal thin film 29a is brought into contact with the other row of the electrode pads 10b.
A laser is applied to these contact points to make the electrode pad 10b.
The other row and the other end of the coating metal thin film 29a are spot-welded.

Thus, the coating metal thin film 29a is fixed to the IC chip 12b, and the power supply source connecting electrode pad 10b and the connection lead 28b of the power supply source 6b are electrically connected via the coating metal thin film 29a. It

The operation of the self-destruction mechanism of the self-destruction type semiconductor device of this embodiment is the same as that of the first embodiment. That is, the metal thin film 29a for coating is the IC chip 12
b) (or the connection between the metal thin film 29a for coating and the original electrode pad 10b that is not a dummy pad is removed) or the connection lead 28a.
When the connection between the power supply source connection electrode pad 10a and is disconnected, the self-destruction mechanism is activated.

In the first embodiment, among the electrical connections on the negative electrode side, the negative electrode collector / terminal plate 25 and the coating metal thin film 29 are included.
The connection with and depends on the contact of both. On the other hand, in the present embodiment, the connection lead 28b is provided on the negative electrode collector / terminal plate 25, and this is provided with the metal thin film 29 for coating.
Since it is spot-welded with a, the electrical connection on the negative electrode side can be made more reliable.

In the first and second embodiments, the connection leads 28a and 28b are joined to the positive electrode current collector / terminal plate 21 and the negative electrode current collector / terminal plate 25. Since the heating is performed before assembling the power sources 6a and 6b, that is, when the current collector is a single body, heating during processing of the power sources 6a and 6b does not pose a problem.

In the first and second embodiments, the small-area first current collector (the positive electrode current collector / terminal plate 21) is opposed to the surface of the IC chips 12a and 12b on the element formation side. ,
This is to prevent a short circuit accident due to contact between both the positive electrode collector / terminal plate 21 and the negative electrode collector / terminal plate 25 and the coating metal thin films 29, 29a.

[Third Embodiment] Next, a third embodiment of the present invention will be described with reference to FIG. In the present invention, the output voltage of the power supply sources 6a and 6b must be constantly monitored by the voltage change detection circuit 5.
However, when a thin lithium battery is mounted as the power supply sources 6a and 6b, the capacity density is 1.5 mAh / cm.
Since it is as small as about ² (one-stage cell, 0.1 mm), the battery life becomes extremely short in a circuit configuration in which a large current is constantly supplied.

Therefore, it is an essential condition for the configuration of the voltage change detection circuit 5 to have a circuit configuration of capacitive coupling so as not to include a leak route in a current route related to its operation. FIG. 6 shows an example of such a capacitive coupling voltage change detection circuit. In this embodiment, a MOS field effect transistor is used as the voltage change detection element.

The output voltage of the power supply sources 6a and 6b is divided by the voltage dividing capacitors C ₁ and C ₂ and the resistor R ₁ ,
It is input to the gate of the voltage change detection transistor 31 from the connection point of the voltage dividing capacitors C ₁ and C ₂ . Since the power consumption of the voltage change detection transistor 31 is very small, the voltage accumulated in the destruction capacitor 3 can be used as its drive voltage, or a large capacity provided separately from the destruction capacitor 3 can be used. The voltage stored in the driving capacitor may be used.

A third party whose purpose is to falsify the IC card is to remove the coating metal thin film 2 from the IC chips 12a and 12b.
9, 9a is completely removed (or the connection between the metal thin film 29, 29a for coating and the original electrode pad 10b which is not a dummy pad is removed), or the connection lead 2
When the connection between 8a and the electrode pad 10a for connecting the power supply source is removed, the voltage divided by the capacitance set in the vicinity of the threshold voltage of the transistor 31 fluctuates, whereby the transistor 31 is turned on. In response to this, a current flows between the source and drain of the transistor 31 and the resistance R ₂
A voltage drop occurs between the terminals. This voltage drop is output as a detection signal to the control circuit or the element 4 via the post-stage amplifier circuit 33.

[Fourth Embodiment] Next, a fourth embodiment of the present invention will be described with reference to FIG. Since the capacity of the thin power supply sources 6a and 6b to be mounted is limited, it is desirable that the switch in the control circuit or the element 4 consume as little power as possible. Usually, this switch is generally a semiconductor switch configured by combining transistors, but in this case, reducing power consumption due to subthreshold current leakage at the time of turning off is a major issue.

In the present invention, as such a switch with low power consumption, it is also possible to use a micromechanical switch which is a kind of micromechanical element having a movable part and which opens and closes contacts by utilizing electrostatic attraction. . FIG. 7 shows an example of a micromechanical switch that opens and closes contacts by such electrostatic attraction. In the figure, (a) is a sectional view,
(B) is a plan view.

As shown in FIG. 7A, the movable suction electrode 47 is installed on the micromechanical switch through the support beam 48 and the connection electrode 49a. When no voltage is applied to the fixed suction electrode 50, the movable contact electrode 51
Is pressed against the fixed contact electrodes 52b and 52c by the elastic force (upward) of the support beam 48.

As a result, the COMM input terminal 53 is electrically connected to the output 2 terminal 54b. The fixed contact electrode 52
b and 52c are supported by the contact electrode supporting portion 55, and are electrically connected to the COMM input terminal 53 and the output 2 terminal 54b via the connecting electrodes 49b and 49c, respectively. The movable contact electrode 51 is electrically insulated from the support beam 48 by the insulating film 57 and mechanically fixed to the support beam 48.

When a voltage is applied from the movable contact operation power supply terminal 56 to the fixed suction electrode 50, the support beam 48 is generated by the electrostatic attraction acting between the fixed suction electrode 50 and the movable suction electrode 47.
Goes down. Then, the movable contact electrode 51 becomes the fixed contact electrode 5
2b, 52c away from the fixed contact electrode 52 on the opposite side
It is pressed against the a and 52d sides. As a result, the COMM input terminal 53 is connected to the output 1 terminal 5 via the movable contact electrode 51.
Conducts with 4a.

When the voltage application to the fixed attraction electrode 50 is stopped, the movable contact electrode 51 moves upward due to the elastic force of the support beam 48. As a result, the movable contact electrode 51 is pressed again toward the fixed contact electrodes 52b and 52c, and the COMM
The input terminal 53 is electrically connected to the output 2 terminal 54b. In this way, the current path is switched by the micromechanical switch.

Regarding connection with other circuits, the detection signal output of the voltage change detection circuit 5 is connected to the movable contact operation power supply terminal 56, and one end of the destruction capacitor 3 is connected to the COMM.
Connect to the input terminal 53, connect one end of the destruction circuit 2 to the output 1 terminal 54a, and connect the electrode pad 10a to the output 2 terminal 54b.
Connect to.

[Fifth Embodiment] Next, a fifth embodiment of the present invention will be described with reference to FIG. In the present invention, the configuration of the destruction circuit 2 is important to avoid reuse of the IC chip 12a. In the present invention, the function of the integrated circuit is surely destroyed by destroying a part of the circuit including the fuse or the antifuse by using the electric power stored in the destruction capacitor 3.

As a circuit to be destroyed, as shown in FIG. 8, a read circuit of a ROM boot circuit, which is the most important in the operation of the IC chips 12a and 12b, can be considered as an example. In FIG. 8A, the decoder input / output line portion of the address signal of the read circuit, for example, the signal lines C _A0 , C _A1 ,
An antifuse 39 is provided in a part of C _A2 , C _A3 , R _A0 , R _A1 , R _A2 , and R _A3 to configure the destruction circuit 2.

FIG. 8B shows a plane pattern diagram of the cell structure in each cell portion. The input / output of the row decoder 40 is
This is carried out through the polysilicon word line forming the gate electrode of the cell transistor forming each of the cells 100 to 133, and the bit line 43 (B ₀ , B ₁ , B ₂ , B ₃ ) are running. Here, the signal input / output line R _A1 of the gate G _R1 of the row decoder 40
An anti-fuse 39 (marked with "x" in the figure) made of a thin oxide film is provided in the portion.

9A and 9B show the structure of the antifuse. FIG. 9A is a plane pattern diagram and FIG. 9B is AA '.
FIG. As shown in FIG. 9B, a device isolation insulating film (LOCOS) 46 is usually formed on a P-type Si semiconductor substrate.
The polysilicon word line 42 while being insulated by
Runs. In the antifuse 39, the element isolation insulating film 46 is not partially formed, but a thin gate oxide film 39a is formed therein, and then phosphorus is implanted at a high concentration to provide an N + diffusion layer 45, which is used as a ground. .

N + insulated by the gate oxide film 39a
When a voltage is applied to the polysilicon word line 42 running on the diffusion layer 45 from the large-capacity destruction capacitor 3 in which the electric charge from the power supply source 6a is accumulated, the gate oxide film 39a is dielectrically destroyed, and the word line 42 is formed. Short to the board. As a result, all the cells (cells 101, 111, 111) addressed by the row decoder 40 using this word line 42 are
121, 131) cannot be read, and reading of the ROM is surely blocked.

The thickness of the gate oxide film 39a is 8
nm is 20 MV / cm for dielectric breakdown
A very high electric field is required. In this case, the voltage required for destruction is 16V, and when a thin lithium secondary battery is used as the power supply sources 6a and 6b, 3.6V × 5 stages = 18.
Since it is V, four to five stages are connected in series and arranged, and this power is stored in the large-capacity destruction capacitor 3, whereby sufficient destruction power can be obtained.

Alternatively, a part of the polysilicon word line 42 operating as the signal input / output line R _A1 may be thinned to serve as a fuse.
That is, a large current is caused to flow through the signal line from the large-capacity destruction capacitor 3 that has accumulated electric charges, and the thinned portion of the polysilicon wiring is scattered by heat melting. Thus
It is also possible to break the read circuit of the ROM boot circuit by breaking the fuse portion provided in the middle of the signal input / output line R _A1 .

[0097]

According to the present invention, as described in claim 1, one of the positive electrode current collector and the negative electrode current collector having the smaller surface area or the positive electrode current collector and the negative electrode current collector having the smaller area. By providing the connection lead on the surface of the current collector, it is possible to make this electrical connection invisible when connecting to the power supply source connection terminal of the semiconductor integrated circuit.

Further, as described in claim 2, the connection lead is provided on the surface of the first current collector having the smaller area of the positive electrode current collector and the negative electrode current collector of the power supply source, A power supply source is mounted on the element surface of the semiconductor substrate so that the first current collector faces the semiconductor integrated circuit, and the connection lead and the first power supply source connection terminal formed on the element surface side of the semiconductor substrate. And a metal thin film covering the second current collector having a larger area so as to cover the power supply source and a peripheral portion including two opposing sides on the element surface side of the semiconductor substrate. By joining with the second power supply source connection terminal, not only the power supply source optically shields but also the device surface of the semiconductor substrate is optically shielded by the coating metal thin film that covers the entire power supply source. be able to. Moreover, by sandwiching the connection lead of the power supply source between the semiconductor substrate and the power supply source mounted on the semiconductor substrate, the electrical connection portion between the connection lead and the first power supply source connection terminal can be invisible from the outside. Can be This can prevent a third party from connecting another power supply source that generates the same voltage as the power supply source in parallel with the power supply source and removing the shielding power supply source from the semiconductor substrate. It is possible to reliably prevent falsification of the memory contents of the semiconductor integrated circuit. Further, when the connection lead and the first power supply source connection terminal are connected to each other, the connection lead is pushed by the metal rod serving as a heat sink so as to be pressed against the first power supply source connection terminal. Heating to the source can be reduced and deterioration of battery life due to heating can be avoided.

Further, as described in claim 3, a connection lead is provided on both surfaces of the positive electrode current collector and the negative electrode current collector of the power supply source, and the connection lead is provided between the positive electrode current collector and the negative electrode current collector. A power supply source is mounted on the element surface of the semiconductor substrate so that the first current collector having the smaller area faces the semiconductor integrated circuit, and the connection lead of the first current collector and the element surface side of the semiconductor substrate are mounted. Connection between the formed first power supply source connection terminal and the second current collector, which covers the power supply source on the second current collector having the larger area so as to cover the power supply source By connecting the leads to each other and the metal thin film to the second power supply source connection terminal formed in the peripheral portion of the semiconductor substrate, including the two sides facing each other on the element surface side, an optical power supply source is used. Of the semiconductor substrate by the metal thin film for covering not only the static shielding but also the whole power supply source It can be shielded optically the.
Moreover, the connection lead of the first current collector of the power supply source is sandwiched between the semiconductor substrate and the power supply source mounted thereon, so that the connection lead and the first power supply source connection terminal are electrically connected. The part can be hidden from the outside. This can prevent a third party from connecting another power supply source that generates the same voltage as the power supply source in parallel with the power supply source and removing the shielding power supply source from the semiconductor substrate. It is possible to reliably prevent falsification of the memory contents of the semiconductor integrated circuit. Also, the first
When connecting the connection lead of the current collector and the first power supply source connection terminal, or when connecting the connection lead of the second current collector and the metal thin film, a metal rod that serves as a heat sink is used By doing so, heating to the power supply source can be reduced, and when connecting the metal thin film and the second power supply source connection terminal, heat is concentrated at both ends of the metal thin film,
It is possible to avoid deterioration of battery life due to heating.

Further, as described in claim 4, by providing the destruction circuit, the destruction capacitor, the voltage change detection circuit and the control circuit or element on the semiconductor substrate, it is attempted to falsify the memory contents of the semiconductor integrated circuit, Whether the metal thin film is completely removed from the semiconductor substrate (or the connection between the metal thin film and the original second power supply source connection terminal that is not the dummy pad is removed), or the connection lead of the first current collector When the connection with the first power supply source connection terminal is removed, the self-destruction mechanism is activated and some wiring or memory information of the semiconductor integrated circuit is destroyed. It can be surely prevented.

[Brief description of drawings]

FIG. 1 is a circuit block configuration diagram of a self-destruction type semiconductor device showing a first embodiment of the present invention.

2A and 2B are a plan view and a cross-sectional view showing an arrangement configuration example of the self-destruction type semiconductor device of FIG.

3A and 3B are a plan view and a cross-sectional view of a power supply source of the self-destruction type semiconductor device of FIG.

FIG. 4 is a plan view and a cross-sectional view showing an arrangement configuration example of a self-destruction type semiconductor device showing a second embodiment of the present invention.

5 is a cross-sectional view of a power supply source of the self-destructive semiconductor device of FIG.

FIG. 6 is a circuit diagram showing a configuration example of a voltage change detection circuit showing a third embodiment of the present invention.

7A and 7B are a cross-sectional view and a plan view showing a configuration example of a control circuit or an element showing a fourth embodiment of the present invention.

FIG. 8 is an explanatory diagram showing a configuration example of a destruction circuit using an antifuse showing a fifth embodiment of the present invention.

FIG. 9 is an explanatory diagram showing a configuration example of an antifuse.

FIG. 10 is an explanatory diagram showing a configuration example of a general IC card.

FIG. 11 is a circuit block configuration diagram of a conventional self-destruction type semiconductor device.

12 is a plan view showing an arrangement configuration example of the self-destruction type semiconductor device of FIG.

13A and 13B are a plan view and a cross-sectional view showing an arrangement configuration example of the self-destruction type semiconductor device of FIG.

14A and 14B are a plan view and a cross-sectional view of a power supply source of the self-destruction type semiconductor device of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 2 ... Destruction circuit, 3 ... Destruction capacitor, 4 ... Control circuit or element, 5 ... Voltage change detection circuit,
6a, 6b ... Power supply source, 7-1 to 7-8 ... External connection electrode pad, 9a, 9b ... Semiconductor substrate, 10a, 10b
... Power supply source connection electrode pads, 12a, 12b ... IC
Chip, 14 ... Data memory, 15 ... Peripheral circuit, 16 ...
Program memory, 17 ... Central processing unit, 18 ... Random access memory, 19 ... Authentication microprocessor, 20 ... Adhesive film, 21 ... Positive electrode current collector / terminal plate,
22 ... Positive electrode, 23 ... Solid electrolyte, 24 ... Negative electrode, 25 ... Negative electrode collector and terminal plate, 26 ... Encapsulating material, 28a, 28b ... Connection lead, 29, 29a ... Metal thin film for coating.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H01L 27/04 H01L 27/04 U (72) Inventor Masahisa Masahisa 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Nihon Telegraph and Telephone Corporation (56) Reference JP-A-2-71345 (JP, A) JP-A-3-262697 (JP, A) JP-A-2000-58760 (JP, A) JP-A-11-328036 (JP , A) JP 11-306786 (JP, A) JP 11-233096 (JP, A) JP 58-51460 (JP, A) JP 5-88986 (JP, A) 4-8363 (JP, U) Actual development Sho 63-32454 (JP, U) Actual development Hei 5-20164 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06K 19/00 -19/08 G11C 5/14 G06F 12/14 H01L 27/04 H01L 21/822

Claims (3)

(57) [Claims] 1. A semiconductor memory device and a memory device
Same as the central processing element that processes the stored data
The semiconductor integrated circuit formed on the conductor substrate and self-destruction
Self-destroying semiconductor device having a power supply source for performing
At least part of the memory information of the semiconductor integrated circuit is destroyed.
Breaking or breaking at least some signal wiring
And a destructive circuit that self-destructs , and this destructive circuit accumulates electric charges for self-destruction.
A destructive capacitor, the first power supply source connection terminal and the second power supply source connection
The voltage between the connecting terminals is monitored and the detection signal is sent according to the voltage drop.
Voltage change detection circuit that outputs the signal and the power supply source connection terminal during normal operation.
Is a voltage change detection circuit connected to the power supply and the destruction capacitor?
If a detection signal is output from the
Control circuit or element for connecting destruction capacitor and destruction circuit
On the semiconductor substrate, and the power supply source is an area of the positive electrode current collector and the negative electrode current collector.
Has a connecting lead on the surface of the smaller first collector,
So that the first current collector faces the semiconductor integrated circuit
It is mounted on the element surface of the semiconductor substrate, and is formed on the element surface side of the connection lead and the semiconductor substrate.
The first current collector is joined to the power supply source connection terminal of No. 1
And make an electrical connection with and cover the power supply on the second collector with the larger area.
The metal thin film covered with the cover faces the element surface side of the semiconductor substrate.
For connecting a second power supply source formed in the peripheral part including two sides
Join the terminals to obtain an electrical connection with the second current collector
A self-destroying semiconductor device characterized by the above. 2. A semiconductor integrated circuit in which a semiconductor memory element and a central processing element for processing data stored in the memory element are formed on the same semiconductor substrate, and a power supply source for self-destruction. In the self-destruction type semiconductor device having , at least a part of the memory information of the semiconductor integrated circuit is destroyed.
Breaking or breaking at least some signal wiring
And a destructive circuit that self-destructs , and this destructive circuit accumulates electric charges for self-destruction.
A destructive capacitor, the first power supply source connection terminal and the second power supply source connection
The voltage between the connecting terminals is monitored and the detection signal is sent according to the voltage drop.
Voltage change detection circuit that outputs the signal and the power supply source connection terminal during normal operation.
Is a voltage change detection circuit connected to the power supply and the destruction capacitor?
If a detection signal is output from the
Control circuit or element for connecting destruction capacitor and destruction circuit
Respectively on the semiconductor substrate, and the power supply source is a surface of both the positive electrode current collector and the negative electrode current collector.
Of the positive electrode current collector and the negative electrode current collector,
The first current collector having the smaller area is mounted on the element surface of the semiconductor substrate so as to face the semiconductor integrated circuit, and the connection lead of the first current collector and the element surface side of the semiconductor substrate are provided. The formed first power supply source connection terminal is joined to obtain an electrical connection with the first current collector, and the power supply source is provided on the second current collector having the larger area. Contact the metal thin film covered so as to cover the connection lead of the second current collector.
And the metal thin film and the second power supply source connection terminal formed on the peripheral portion of the semiconductor substrate, including the two sides facing each other on the element surface side, are joined to each other, and the electrical connection with the second current collector is achieved. Self-destruction type semiconductor device characterized by obtaining a physical connection. 3. A self-destroying semiconductor according to claim 1 or 2.
In the device , the horizontal position of the connection lead is the first and the first position.
2. A self-destruction type semiconductor device, characterized in that the current collector does not go out of the plane .