JP3535797B2 - Method for manufacturing monolithic integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a high frequency monolithic integrated circuit used in a wireless device / terminal in the microwave to millimeter wave band.

[0002]

2. Description of the Related Art Active devices such as FETs and passive elements such as resistors, capacitors and inductors are provided on a semiconductor substrate such as gallium arsenide (GaAs) or silicon (Si) in a semiconductor integrated circuit manufacturing process (hereinafter referred to as a semiconductor process). MMIC (monolithic microwave / millimeter wave integrated circuit), which is manufactured in a batch and integrally by means of attention as a core technology of high frequency hardware, has been introduced to PHS, PCN, Wireless WAN / LAN etc. since 1990. It is supposed to be done. The technological progress of MMIC will contribute to the future development of the information sharing society,
With the expansion of the wireless communication market, there is a strong demand for further miniaturization, higher integration, and lower cost of MMICs.

FIG. 17 is a diagram showing a conventional method for manufacturing a monolithic integrated circuit (or MMIC).
First, in consideration of the required device characteristic specifications 100, the entire device is divided into functional blocks (amplifier, mixer, oscillator, etc.), and each functional circuit specification 101 is determined. Next, an active device that satisfies the operating frequency, band, characteristics, etc. included in each functional circuit specification 101 is selected.

Here, in the conventional method for manufacturing a monolithic integrated circuit shown in FIG. 17, since all the manufacturing steps including the active device to the wiring step are configured by one manufacturer (or enterprise), Determining the active device means selecting the semiconductor process 102. A circuit design 103 is performed using the characteristic parameters of the selected active device, and a circuit simulator or the like operating in a computer system determines whether the designed circuit configuration satisfies the functional circuit specification 101. If the circuit configuration is not satisfied, the active device or circuit is determined. Changed the configuration, functional circuit specification 101
The circuit design 103 is repeated so that

When a functional circuit (for example, an amplifier) satisfying the functional circuit specification 101 is obtained, the actual circuit pattern design 104 is performed. At this time, the design rule peculiar to the semiconductor process 102 based on the reliability standard and the constraint condition in the manufacturing process is observed and the patterning is performed so as to match the circuit diagram obtained by the circuit design 103 to the maximum extent.

Here, in the case where an error occurs in the circuit diagram obtained by the circuit design 103 and the equivalent circuit diagram laid out by the pattern design 104, the functional circuit specification 1
01 is satisfied, and if not satisfied, the circuit pattern and the circuit configuration are changed, and the pattern design 104 or the circuit design 103 is performed so as to satisfy the functional circuit specification 101.
And the pattern design 104 are repeated. Further, in the case of reducing the circuit area, the coupling between the passive elements or between the wirings becomes a circuit pattern that cannot be ignored. Therefore, the circuit design 103 is performed using the analysis result of the electromagnetic field simulator operating in the computer system. Repeatedly, the functional circuit specification 101 is satisfied.

When a circuit pattern satisfying the functional circuit specification 101 is obtained, the circuit pattern is data-converted using software or the like operating in a computer system, and this data is used to perform the photomask 1 necessary for a semiconductor process.
Create 05. Next, a monolithic integrated circuit is manufactured on a semiconductor substrate by manufacturing 106 using a semiconductor process using the photomask 105. In the semiconductor manufacturing 106, active devices, passive elements such as resistors, capacitors and inductors, and wiring are manufactured collectively and integrally.

On-wafer evaluation 107 is performed to determine whether the manufactured monolithic integrated circuit matches the characteristics simulated by the circuit design 103 or the pattern design 104. As a result of the on-wafer evaluation 107, the manufactured functional circuit has specifications 10
If the condition 1 is not satisfied, the cause is analyzed and the manufacturing process 106 by the semiconductor process and the on-wafer evaluation 107 are repeated using the circuit pattern (104), the circuit configuration change (103), and the like.

On-wafer evaluation 107 specifies functional circuit specification 10
When 1 is satisfied, the wafer is diced to assemble the functional circuits into individual pieces, the diced chips are assembled 108 on the mounting substrate, and the test / evaluation 109 is performed again. In the test / evaluation 109, it is determined whether the assembled functional circuit satisfies the functional circuit specification 101. If the functional circuit is not satisfied, the cause is analyzed, and the assembly 108 is repeatedly corrected. When the assembled functional circuit satisfies the functional circuit specification 101, the monolithic integrated circuit is completed (delivered) 111 through reliability evaluation 110.

In the conventional method for manufacturing a monolithic integrated circuit shown in FIG. 17, active devices and passive elements such as resistors, capacitors and inductors can be manufactured collectively and integrally by the same semiconductor process, which results in miniaturization of the circuit. Economicalization can be achieved by the effect of mass production. In addition, when there are already developed circuit libraries using the same active device, it is possible to utilize them or make partial corrections to improve the design efficiency in the circuit design 103. Further, it is possible to improve the efficiency of the pattern design 104 by using the accumulated circuit pattern library. However, in the conventional method for manufacturing a monolithic integrated circuit, it is difficult to separate the active device and the wiring (interconnection) technology because the structure of the monolithic integrated circuit is planar.

FIG. 18 is a plan view of a first conventional monolithic integrated circuit. Substrate 20 made of semiconductor
An active element 201 such as a transistor and an FET, a resistor 202, a passive circuit element such as a capacitor 203 and an inductor 204, and a transmission line 205 are formed on one surface (main surface) of 0, and a functional circuit (for example, an amplifier) is configured by this. There is.

In the first conventional monolithic integrated circuit shown in FIG. 18, since the transmission line 205 is a microstrip line composed of the semiconductor substrate 200 and the ground conductor formed on the back surface (sub surface) of the substrate 200, the transmission line 205 The characteristic parameters of (1) depend on the substrate 200 as well as the active device. In the semiconductor process for manufacturing the first conventional monolithic integrated circuit, the transmission line 205 and the inductor 20
The electrode metal of the active element 201 may be formed using the wiring metal of No. 4. Therefore, since the active device process and the wiring process are closely related to each other, it is difficult to separate them, and it is possible to set a general-purpose interface (manufacturing process) capable of separating the manufacturing process of the active device and the wiring process. Have difficulty.

There is also a method of dividing the device process and the wiring process area in a plane, but the active element 2
01 and the resistor 202 are arranged in advance, the degree of freedom in forming the wiring conductor (that is, the degree of freedom in design) is not limited, and it is necessary to prepare a region for forming the wiring conductor. , Generate a useless area on the substrate.
Further, in the first conventional monolithic integrated circuit, the arrangement of each element in a circuit (for example, an amplifier, a mixer, an oscillator, etc.) having an individually required function is different, and a photomask required in a semiconductor process is required. Was also required individually for each functional circuit.

In the usual semiconductor process for monolithic integrated circuits, about 10 photomasks and manufacturing time of about 2 months are required for forming active elements, and more than half or 2 photomasks required for the whole semiconductor process are required. / 3
The above time is spent for forming active elements. Therefore, in the case of low-volume, high-mix production, the photomask occupies a large proportion of the manufacturing cost, resulting in a high cost and a long manufacturing time.

Further, in the first conventional monolithic integrated circuit shown in FIG. 18, since the active element and the passive element are arranged in a plane, there is a limit to the high density wiring. That is, in a planar arrangement, the effective efficiency (circuit element occupied area / chip area) does not exceed 100%. In order to increase the density of the circuit layout, it is necessary to design in consideration of the amount of coupling between each element, and the designer needs advanced design technology.

As a method for solving the above-mentioned problems, a technique has recently been reported for realizing a monolithic integrated circuit by laminating a dielectric thin film on a semiconductor substrate and forming a transmission line or the like using the dielectric thin film. ing. Further, by forming the dielectric thin film into a multi-layer structure or a three-dimensional structure, high integration and high density of the passive circuit are realized, which promotes drastic miniaturization and high integration of the MMIC.

FIG. 19 shows a second conventional monolithic integrated circuit utilizing a dielectric thin film (US Pat. No. 5,739,5).
(Specification No. 60). In FIG. 19, a set of an active element 201, a capacitor electrode 206, and a resistance element 202 is formed in an array on one surface (main surface) of a semiconductor substrate 200, and a ground conductor 220 is formed via a dielectric film 210. The dielectric film 230 having a thickness of 1 μm or more is formed on the ground conductor 220, the wiring 240 is formed on the dielectric film 230, and the through hole 221 and the active element 201 on the substrate 200 are the holes 211 of the dielectric film 210. , Ground conductor 220
Are connected through the opening 222 to form a functional circuit.

Here, the opening 222 is formed on the active element 201 or the like used in the circuit. Second shown in FIG.
In the conventional monolithic integrated circuit, the arrangement of the active elements 201 and the like on the semiconductor substrate 200 can be determined in advance, so that the semiconductor substrate (photomask) can be shared by various functional circuits. It is possible to reduce the manufacturing cost and the development time even in the case of low-volume, high-mix production.

Further, since the unused active elements 201 and the like are covered with the ground conductor 220 on the surface, it is possible to perform wiring and the like on the unused elements, so that it is necessary to prepare an area for wiring. In addition, the area of the semiconductor substrate can be effectively used. In addition, the dielectric film 230
By forming the wiring 240 and the wiring 240 in a multi-layer structure, a passive circuit can be formed with high density and high integration, and the circuit can be downsized.

Further, when the dielectric film 230 is sufficiently thin, the line width of the wiring 240 is narrow, so that parasitic capacitance and parasitic inductance due to the wiring pattern layout, coupling and crosstalk caused by the crossing or proximity of the circuit elements, etc. Since the influence can be almost ignored, most of the advanced design skills required by the designer in circuit layout can be eliminated. Further, the characteristic parameter of the wiring 240 formed on the ground conductor 220 via the dielectric film 230 is as follows.
Since it is determined by the dielectric film 230 formed on the substrate 20, it does not depend on the type of device or the substrate material.

Further, even when a plurality of active elements or the like are previously arranged on the surface of the substrate, the wiring 240 can be arranged above the active elements by covering the unused active elements or the like with the ground conductor 220. Therefore, the chip area can be effectively used. That is, in a monolithic integrated circuit in which a dielectric thin film is laminated on a semiconductor substrate and a transmission line or the like is formed by using this dielectric thin film, it can be electrically and structurally (horizontal) separated by the ground conductor 220, and It becomes possible to divide the ground conductor 220 into an active device process and a wiring process by using the interface manufacturing process.

[0022]

However, as shown in FIG.
In the conventional method for manufacturing a monolithic integrated circuit shown in FIG. 1, since it is consistently manufactured by the semiconductor process of the same manufacturer or enterprise, it is necessary to carry out the circuit design and layout according to the process rule of the semiconductor process. Therefore, it is difficult for a designer to freely combine an excellent active device with a high-density wiring (or interconnection) process to design and lay out a circuit.

In other words, in the manufacturing (development) of a monolithic integrated circuit up to now, a designer designs a circuit having desired characteristics in accordance with the characteristics of an active device, and manufactures a monolithic integrated circuit based on the data. (Development) The semiconductor manufacturing process-led manufacturing method is adopted. As a result,
A company or group that manufactures (develops) active devices requires continuous development of a wide variety of active devices. This causes an increase in the semiconductor process cost, resulting in a serious problem in reducing the cost of the monolithic integrated circuit.

Further, with the recent development of multimedia communication, the demand for high-speed and wide-band wireless communication has risen, and as the carrier frequency becomes higher, the multi-layer or three-dimensional wiring (interconnection) technology fulfills. Roles are becoming increasingly important. However, in the case of pursuing high integration of an LSI or the like, it is inevitable to reduce the wiring size and increase the number of wiring layers. There are many technical problems left in the wiring process to realize these, and a large amount of investment and manpower are required also in the development of an excellent wiring (interconnection) process.

On the other hand, along with the miniaturization and high integration of LSI packages centering on Si devices, high-density packaging technology by flip chips for mounting face-down of pair chips directly on the substrate has been actively developed. . There are several methods such as Au stud bump method and solder ball bump method in the flip chip mounting method. However, since the bonding pitch of the flip chip mounting is larger than the wire bonding pitch, it is necessary to rearrange the wire bonding pads. , It is necessary to move to the flip-chip pad so that it can be used for flip-chip mounting. At present, the flip-chip mounting has a large bonding pitch of about 0.2 mm and is used only in the low frequency region where the delay amount of the delay line due to the rearrangement of the pads can be ignored.

However, around 2012, the pitch size is about 0.05 mm, and it is expected that flip mounting can be performed without rearranging the pads (SIA: Semi).
1997 edition by conductor industry association
Assembly & Packaging Roadmap). in this case,
Since the delay amount of the rearrangement wiring can be neglected, it is considered that flip-chip mounting becomes common also in the microwave / millimeter wave MMIC.

The present invention has been made in view of the above problems, and it is an object of the present invention to design a monolithic integrated circuit using a laminated structure of thin film dielectric films, which is mainly desired by a designer. An object of the present invention is to provide a low-cost and high-performance manufacturing method for a monolithic integrated circuit by combining an active device and a desired wiring (interconnection) process.

[0028]

In order to achieve such an object, the present invention provides a semiconductor substrate having a surface on which a plurality of active elements and passive elements are formed,
A first dielectric film formed on the active element and the passive element, and one or more windows and a cover portion formed on the first dielectric film, the window including the active element and the cover section. A selective ground conductor plate formed on the active element and the passive element in the passive element, and the cover portion covering the unused active element and the passive element in the active element and the passive element, and the selective ground conductor plate A second dielectric film formed thereon; a wiring layer formed on the film of the second dielectric film; and connecting means for connecting the active element and the passive element to be used to the wiring layer. In the method of manufacturing a Morrisic integrated circuit, the entire device is divided into functional blocks in consideration of the required device characteristic specifications, and active devices and wiring layers suitable for each functional circuit specification are selected and each semiconductor process is selected. Circuit design A design step to be performed, a step of designing a circuit pattern of the designed circuit configuration to create a photomask to be used in a semiconductor process, and a first semiconductor process using a photomask up to the selective ground conductor plate of the photomask And a step of forming the selective ground conductor plate and forming the selective ground conductor plate by a second semiconductor process using a photomask after the selective ground conductor plate. It is characterized by that.

The invention according to claim 2 is the first
After forming the selective grounding conductor plate by the semiconductor process described above, after covering the entire surface of the wafer with the first passivation film, a part or all of the first passivation film is removed by the second semiconductor process. To do.

The invention described in claim 3 is the same as claim 1
Alternatively, in the invention described in Item 2, the wiring layer is a multilayer wiring layer, and the first bonding pad is formed by the uppermost wiring.

The invention according to claim 4 is the invention according to claim 1, 2 or 3, wherein one or more wiring layers are formed between the semiconductor substrate and the selective ground conductor plate. It is characterized by that.

As described above, the inventions according to claims 1 to 4 manufacture (develop) active elements (transistors and FETs).
Since the manufacturing (development) of the interconnection technology for forming the wiring layer and the wiring layer can be divided into different manufacturers (or companies), the process development cost and investment risk of each manufacturer (or company) can be distributed. Can be reduced. In addition, since each manufacturer (or company) involved in the production and development of a monolithic integrated circuit (MMIC) can specialize in the development of active devices and the development of interconnection technology, strategic devices and high-density wiring can be used. It can be developed in a shorter period than before.

Further, even in a company that does not have a manufacturing process of active elements, it is necessary to develop an interconnection technology with a much smaller investment than device development and to enter a monolithic integrated circuit (MMIC) development which can be expected to have great marketability. Is possible. In addition, the circuit designer can design a high-frequency circuit by combining a device having desired characteristics with a desired wiring (interconnection) technology, which greatly improves the degree of freedom in design and also the market needs. It is possible to develop a high-performance MMIC tailored to.

As a result, the development of the monolithic integrated circuit (MMIC) led by the designer can be realized, so that the cost reduction and the shortening of the development period of the monolithic integrated circuit (MMIC) are drastically promoted. In addition, since the photomask manufactured from the circuit data is divided and used by manufacturers (or corporations) who manufacture active devices and wiring, information is kept secret even in the strategic functional circuit as compared with the conventional method. .

The invention described in claim 5 is the same as claim 3
Alternatively, in the invention described in item 4, the entire device is divided into functional blocks in consideration of the required device characteristic specifications, and an active device, a wiring layer, and a second bonding pad suitable for each functional circuit specification are manufactured. A step of performing a circuit design by selecting the semiconductor process, a step of designing a circuit pattern of the designed circuit configuration to produce a photomask used in the semiconductor process,
A step of performing steps up to the formation of the selective ground conductor plate by a first semiconductor process using the photomask up to the selective ground conductor plate; and a photomask from the selective ground conductor plate to the first bonding pad. Using the second semiconductor process to perform the fabrication process after the selective ground conductor plate,
Rearranging the first bonding pad on a second bonding pad at a different position using a photomask after the first bonding pad, and then forming a third dielectric film on the entire surface of the wafer; A window of a third dielectric film is provided on the second bonding pad, and the step of connecting the solder ball formed on the third dielectric film to the second bonding pad. To do.

The invention according to claim 6 is the same as claim 5
In the invention described in (3), the manufacturing process after the first bonding pad is performed by a third semiconductor process using a part or all of the photomask after the first bonding pad. Is.

The invention described in claim 7 is the same as claim 5
Alternatively, in the invention of claim 6, after the first bonding pad is formed by the second semiconductor process, the entire surface of the wafer is covered with a second passivation film, and then the third bonding pad is formed.
Part or all of the second passivation film is removed by the semiconductor process of (1).

As described above, in the inventions according to claims 5 to 7, since the flip chip mounting bonding bumps are manufactured, the monolithic integrated circuit (MMIC) chip can be directly mounted face down on the substrate. If the pitch size of the flip chip mounting bonding bumps is comparable to that of wire bonding,
Since it is not necessary to perform the rearrangement wiring, the process steps (cost) are reduced. Further, when the third dielectric film is made of resin or the like, it functions as an airtight seal, so that the reliability of the monolithic integrated circuit (MMIC) can be improved. Further, after the solder balls are mounted, by performing a dicing process for dividing the chips into individual chips at the wafer level, automatic flip chip mounting becomes possible.

The invention described in claim 8 is the same as in claim 1.
In the invention described in any one of 1 to 7, the first
Part of information on active and passive elements manufactured by the semiconductor process, information on wiring manufactured by the second semiconductor process, and information on relocation wiring and ball bumps manufactured by the third semiconductor process. Alternatively, all of them are stored in a computer system, and the circuit design and the pattern design are performed by using the received information of the computer system.

The invention described in claim 9 is the same as that of claim 8.
In the invention described in (3) above, in the computer system, information on active elements and passive elements manufactured by a plurality of semiconductor processes, information on a wiring layer manufactured by a plurality of semiconductor processes, and information on a wiring layer manufactured by a plurality of semiconductor processes. Part or all of the information on the layout wiring and the ball bumps is stored, and part or all of the information can be deleted or updated.

As described above, in the inventions according to claims 8 to 9, since the library data of the active device and the high frequency wiring required for the design are stored in the computer system or the software operating in the computer, the monolithic integrated circuit is stored. It is possible to realize high-speed design and reduce development cost. As a result, if the process design rule is stored in software and the function to automatically check after pattern design is added, it is possible to eliminate human error in pattern design and improve pattern design. Can be achieved. In addition, by storing the library data of the developed monolithic integrated circuit in software and reusing it, the circuit design and pattern design can be greatly shortened.

The invention according to claim 10 is the invention according to any one of claims 1 to 9, wherein a part or all of the photomask up to the selective grounding conductor plate in the photomask. A manufacturing process is performed by the first semiconductor process using, the manufactured active element is measured, a circuit is designed by using the information obtained by the measurement, and the designed circuit configuration is designed as a circuit pattern. The photomask necessary for the rest of the semiconductor process is formed, and the first mask is formed.
The monolithic integrated circuit is manufactured by using the semiconductor process and the second semiconductor process or only the second semiconductor process.

As described above, according to the tenth aspect of the present invention, the characteristics of the active device or the like used before the wiring process is clarified, and the circuit design considering the deviation of the device characteristics due to the manufacturing process of the active element is performed. A monolithic integrated circuit (MMIC) that is possible and has less error between design and actual measurement
Can be realized.

The invention according to claim 11 is the invention according to any one of claims 1 to 10, wherein a plurality of active elements and a plurality of resistors having different resistance values are provided on the semiconductor substrate. A master array in which master cells configured of at least one of capacitors having different resistance values are arranged in a matrix, and the entire device is divided into functional blocks in consideration of the required device characteristic specifications,
It is characterized in that each semiconductor process for manufacturing an active device and a wiring layer suitable for each functional circuit specification and the master array composed of the active device are selected for circuit design.

As described above, according to the eleventh aspect of the present invention, since a part of the active device process can be carried out in parallel with or prior to the circuit design or the pattern design, the development period of the monolithic integrated circuit can be greatly shortened. . Further, when the existing master array is used, it is possible to use the photomask that has already been formed, so that the process cost can be reduced.

According to a twelfth aspect of the present invention, in the invention according to any one of the first to eleventh aspects, respective semiconductor processes for manufacturing active devices and wiring layers suitable for required functional circuit specifications. Selecting a circuit pattern, designing a circuit pattern of the designed circuit configuration to create a photomask used in a semiconductor process, and using a photomask up to the selected ground conductor plate of the photomask. A step of forming the selective grounding conductor plate by a first semiconductor process, and a manufacturing step of the selective grounding conductor plate and subsequent steps by a second semiconductor process using a photomask after the selective grounding conductor plate. And performing steps.

According to a thirteenth aspect of the present invention, in the invention according to any one of the first to twelfth aspects, an existing photomask is used to form the selective ground conductor plate by the first semiconductor process. The second step is performed.
The monolithic integrated circuit is manufactured on the semiconductor substrate by performing the manufacturing process after the selective grounding conductor plate by the semiconductor process of 1.

According to a fourteenth aspect of the present invention, in the invention according to any one of the first to thirteenth aspects, the steps up to the formation of the selective ground conductor plate are performed by the first semiconductor process, A manufacturing process after the selective grounding conductor plate is performed by a second semiconductor process, a monolithic integrated circuit is manufactured on a semiconductor substrate, and the manufactured semiconductor substrate is diced to separate the functional circuits into individual pieces. It is a feature.

According to a fifteenth aspect of the invention, in the invention according to any one of the first to fourteenth aspects, the semiconductor substrate is a compound semiconductor substrate.

[0050]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a diagram showing a first embodiment of a method for manufacturing a monolithic integrated circuit according to the present invention. First, in consideration of the required device characteristic specifications 100, the entire device is divided into functional blocks, and each functional circuit specification 101 is determined. Next, the active device process 120 and the wiring process 121 which can satisfy the operating frequency, the band, the characteristic, etc. included in each functional circuit specification 101 are selected. A circuit design 103 is performed using the characteristic parameters of the selected active device and the characteristic parameters of the transmission line, the inductor, etc. that can be formed in the wiring process, and the designed circuit configuration determines the functional circuit specifications 101 by a circuit simulator or the like operating in the computer system. Determine if you are satisfied.

If the specification 101 is not satisfied, the active device, transmission line parameters, circuit configuration, etc. are changed, and the circuit design 103 is repeated so as to satisfy the functional circuit specification 101. When a functional circuit (for example, an amplifier) satisfying the functional circuit specification 101 is obtained, the actual circuit pattern design 1
Do 04. At this time, the design rule specific to the active device process 120 and the design rule specific to the wiring process 121 based on the reliability standard and the constraint condition on the manufacturing process are respectively observed, and the circuit diagram obtained by the circuit design 103 is maximized. Pattern to match.

Here, when an error occurs in the circuit diagram obtained by the circuit design 103 and the equivalent circuit diagram laid out by the pattern design 104, the functional circuit specification 1
01 is satisfied, and if not satisfied, the circuit pattern (104), the circuit configuration is changed (103), etc., and the pattern design 104 is performed so as to satisfy the functional circuit specification 101.
Alternatively, the circuit design 103 and the pattern design 104 are repeated. Further, in the case of reducing the circuit area, the coupling between the wirings may become a non-negligible pattern. Therefore, the circuit design 103 is repeated using the analysis result of the electromagnetic field simulator operating in the computer system.
Satisfy the functional circuit specifications 101.

If necessary, the device process 120 and the wiring process 121 are changed so that the circuit design 1
03 and pattern design 104 are repeated. Functional circuit specifications 1
When a circuit pattern satisfying 01 is obtained, the circuit pattern is data-converted using software or the like operating in a computer system, and the photomask 105 necessary for the device process 122 and the wiring process 123 is created using this data.

Next, of the photomasks 105, after the manufacturing process 122 using the photomask 105 up to the selective ground conductor plate, the manufacturing process 122 is performed using the photomask 105 after the selective ground conductor plate. Step 123 is performed to fabricate a monolithic integrated circuit on the semiconductor substrate. On-wafer evaluation of whether the manufactured monolithic integrated circuit matches the characteristics simulated by the circuit design 103 or the pattern design 104.
7. As a result of the on-wafer evaluation 107, when the manufactured functional circuit specification 101 is not satisfied, the cause is analyzed, the circuit pattern 104, the circuit configuration change 103, etc. are performed, and the manufacturing 122 by the device process, the manufacturing 123 by the wiring process, the on-wafer evaluation. Repeat 107.

On-wafer evaluation 107, functional circuit specification 10
When 1 is satisfied, the wafer is diced to assemble the functional circuits into individual pieces, the diced chips are assembled 108 on the mounting substrate, and the test / evaluation 109 is performed again. In the test / evaluation 109, it is determined whether the assembled functional circuit satisfies the functional circuit specification 101. If the functional circuit is not satisfied, the cause is analyzed, and the assembly 108 is repeatedly corrected. When the assembled functional circuit satisfies the functional circuit specification 101, the monolithic integrated circuit is completed (delivered) 111 through reliability evaluation 110.

FIG. 2 is a sectional view showing a monolithic integrated circuit manufactured by the first embodiment of the method for manufacturing a monolithic integrated circuit of the present invention shown in FIG. In FIG. 2, a plurality of active elements 2, capacitor base electrodes 3, and resistance elements 4 are formed on one surface (main surface) of a semiconductor substrate 1, and a ground conductor 20 and the ground conductor 2 are provided via a dielectric film 10.
The conductors 20a and 20b which are not connected to 0 are formed.
Here, a thin film capacitor (MIM capacitor) is formed by the capacitor base electrode 3 and the ground conductor 20, and the capacitor base electrode 3 and the conductor 20b.

A dielectric film 30 having a thickness of 1 μm or more is formed on the ground conductor 20, and the wiring 4 is formed on the dielectric film 30.
0 is formed, and is connected to the electrode 2a of the active element 2, the base electrode 3 for capacitor, and the electrode 4a of the resistance element 4 on the substrate 1 through the through hole 50, the conductor 20a, and the through hole 11 penetrating the dielectric film 10. And a functional circuit is configured. In the monolithic integrated circuit shown in FIG. 2, the ground conductor 20 is a selective ground plate, the ground conductor 20 (including the conductors 20a and 20b simultaneously formed) is manufactured by a device process, and after the formation of the dielectric film 30. The manufacturing process is performed by a wiring process.

As described above, in the first embodiment of the method for manufacturing a monolithic integrated circuit according to the present invention, manufacturing of active devices (transistors and FETs) and manufacturing of interconnection technology for forming wiring layers are performed by different companies. Since it can be divided into (or groups), circuit designers can freely combine desired active devices and desired wiring (interconnection) processes, and low cost and high performance monolithic integrated circuits that meet market needs. It will be possible to develop.

As a result, the MMIC development led by the designer can be realized, so that the cost reduction and the shortening of the development period of the MMIC are drastically promoted. In addition, since the devices in the wiring part are only transmission lines and inductors formed on the thin-film dielectric film, it is easier to create a library and the existing developed circuit can be re-created without changing the active elements compared to the conventional one. It can be used or changed. Therefore, if the specifications can be met by changing only the wiring, an existing photomask or a wafer manufactured by an active device process can be used, so that the development cost can be reduced.

Further, since active device development and wiring technology development, which are continuously required in strategic monolithic integrated circuit development, can be divided, process development costs and investment risks of each manufacturing company (or group) can be dispersed and reduced. Is possible. Further, since each company (or group) involved in MMIC production can specialize in the development of active devices and interconnection technology, it is possible to develop pioneering devices and high-density wiring in a shorter period than before. .

Further, even a company that does not have a manufacturing process for active devices can develop an interconnection technology with much less investment than the development of active devices, and can enter the MMIC development which is expected to have great marketability. . In addition, photomasks made from circuit data are companies (or groups) that make active devices and wiring.
Since the information is divided into two and used, the information is kept secret even in the strategic functional circuit as compared with the conventional one.

Further, as shown in FIG. 3, after the selective ground conductor plate (here, the ground conductor 20) is formed by the manufacturing 122 by the active device process, the whole surface of the wafer is covered with the passivation film 23 by the same process, and thereafter, In the manufacturing 123 by the wiring process, a part or all of the passivation film 23 is removed, and the dielectric film 30 is removed.
May be formed. In this case, the wafer can be protected at the time of transfer between different processes, and at the same time, the wafer manufactured by the active device process manufacturing 122 can be stored for a long time and the wiring process can be performed at any time.

FIG. 4 is a sectional view of a monolithic integrated circuit manufactured by the method for manufacturing a monolithic integrated circuit according to the first embodiment of the present invention. As shown in FIG. 4, the dielectric film 3 laminated on the selective ground conductor plate (20).
0 may have a multi-layer structure in which wiring conductors (40, 41, 42, 43) are formed in or on the dielectric film 30. In FIG. 4, the same components as those in FIG. 2 are designated by the same reference numerals.

Compared to the monolithic integrated circuit shown in FIG.
Wiring can be formed at a high density by utilizing a multilayer structure, and a monolithic integrated circuit can be realized in a small size and a high degree of integration. The upper and lower wirings, the selective ground conductor plate 20, the active element 2 formed on the semiconductor substrate 1, the capacitor base electrode 3, and the resistance element 4 are through holes (50, 51,
52). By using a polyimide resin or BCB (bisbenzocyclobutene) resin as the dielectric film 30, a multilayer film having high flatness can be realized by low temperature treatment.

Further, in FIG. 4, a pad 40p for wire bonding may be formed by the uppermost wiring conductor. In this case, a monolithic integrated circuit (MMI
C) Since the chip is mounted on a mounting (package) substrate to form a module, the mounting cost can be reduced.
Further, by covering the chip with the airtight sealing resin, the reliability of the monolithic integrated circuit (MMIC) can be improved.

FIG. 5 is a sectional view of a monolithic integrated circuit manufactured by the method for manufacturing a monolithic integrated circuit according to the first embodiment of the present invention. As shown in FIG. 5, another multilayer dielectric film (22a, 22b) is formed on the dielectric film 10, and a plurality of wiring layers (14,
15) may be formed. In FIG. 5, the same components as those in FIG. 2 are designated by the same reference numerals.

In this case, since the passive circuit electrically isolated from the wiring formed by using the dielectric film 30 and having a short delay amount can be formed, it is possible to easily realize the mixed mounting of the digital circuit and the analog circuit. Becomes The upper and lower wirings, the selective ground conductor plate 20, the active element 2 formed on the semiconductor substrate 1, the capacitor base electrode 3, and the resistance element 4 are connected through through holes (11, 12, 13).

(Second Embodiment) FIG. 6 is a diagram showing a second embodiment of the method for manufacturing a monolithic integrated circuit according to the present invention. In FIG. 6, the same parts as those in FIG. 1 are designated by the same reference numerals.

In FIG. 2, first, in consideration of the required device characteristic specifications 100, the entire device is divided into functional blocks, and each functional circuit specification 101 is determined. An active device process 120 and a wiring process 121 that can satisfy the operating frequency, band, characteristics, etc. included in each functional circuit specification 101 are selected. A circuit design 103 is performed using the characteristic parameters of the selected active device and the characteristic parameters of the transmission line, the inductor, etc. that can be formed in the wiring process, and the designed circuit configuration conforms to the resin circuit specification 101 by a circuit simulator operating in the computer system. Determine if you are satisfied.

In the case of flip-chip mounting, the bonding process is selected 124 prior to the circuit design 103, if necessary, and then the circuit design 103 is performed to determine whether the designed circuit configuration satisfies the functional circuit specification 101. If the specification 101 is not satisfied, the active device, transmission line parameters, circuit configuration, etc. are changed, and the circuit design 103 is repeated so as to satisfy the functional circuit specification 101. When a functional circuit (for example, an amplifier) satisfying the functional circuit specification 101 is obtained, the actual circuit pattern design 104 is performed.

At this time, the design rule specific to the active device process 120, the design rule specific to the wiring process 121, and the design rule specific to the bonding process 124 based on the reliability standard and the constraint condition on the manufacturing process are respectively observed, and the circuit. Patterning is performed so as to match the circuit diagram obtained in the design 103 as much as possible. Here, patterning is performed so as to match the circuit diagram obtained by the circuit design 103 as much as possible.

Here, when an error occurs between the circuit diagram obtained by the circuit design 103 and the equivalent circuit diagram laid out by the pattern design 104, the functional circuit specification 1
01 is satisfied, and if not satisfied, the circuit pattern (104), the circuit configuration is changed (103), etc., and the pattern design 104 is performed so as to satisfy the functional circuit specification 101.
Alternatively, the circuit design 103 and the pattern design 104 are repeated. Further, in the case of reducing the circuit area, the coupling between the wirings may become a non-negligible pattern. Therefore, the circuit design 103 is repeated using the analysis result of the electromagnetic field simulator operating in the computer system.
Satisfy the functional circuit specifications 101.

If necessary, the device process 120, the wiring process 121, and the bonding process 124 are changed to change the circuit design 103 and the pattern design 10.
Repeat 4. When a circuit pattern satisfying the functional circuit specification 101 is obtained, the circuit pattern is data-converted using software or the like that operates in a computer system, and this data is used to generate a photomask 105 necessary for the device process 122 and the wiring process 123. create. For flip-chip mounting, the mask required for the bonding process, that is, relocation wiring from the wire bonding pad of the monolithic integrated circuit to the bonding pad for flip-chip mounting, formation of solder ball metal posts, formation of hermetic sealing resin A photomask 105 for a manufacturing process relating to the formation of solder balls is formed.

The mask required for the bonding process does not have to be formed at the same time as the photomask required for the device process 122 and the wiring process 123. After the on-wafer evaluation 107 of the monolithic integrated circuit, the circuit design 103 and the pattern design 104 are performed. You may create after performing. Next, of the photomasks 105, after a manufacturing process 122 using the photomasks 105 up to the selective ground conductor plate, a wiring process is performed using the photomasks 105 up to the wire bonding pads after the selective ground conductor plate. Manufacturing 123 is performed to manufacture a monolithic integrated circuit on a semiconductor substrate.

In the case where the flip-chip mounting is not performed, the manufacturing 125 by the bonding process is not performed, and if the functional circuit specification 101 is satisfied by the on-wafer evaluation 107, then the first embodiment of the method for manufacturing a monolithic integrated circuit according to the present invention is performed. It is manufactured by the same flow as in FIG.

On the other hand, in the case of flip-chip mounting, after the manufacturing 123 by the wiring process, the manufacturing 125 by the bonding process is performed using the photomask 105 after the wire bonding pad. After that, in order to divide the functional circuit manufactured by the manufacturing 125 by the bonding process into individual pieces, the wafer is diced, and the diced chips are assembled on the mounting substrate 108, tested,
Evaluation 109 is performed.

In the test / evaluation 109, it is determined whether or not the assembled functional circuit satisfies the functional circuit specification 101. If not, the cause is analyzed, and the assembly 108 is repeatedly corrected. When the assembled functional circuit satisfies the functional circuit specification 101, the monolithic integrated circuit is completed (delivered) 111 through reliability evaluation 110.

FIG. 7 is a sectional view of a monolithic integrated circuit manufactured according to the second embodiment of the method of manufacturing a monolithic integrated circuit of the present invention shown in FIG. Note that FIG.
2 that are the same as those in FIG. 2 are denoted by the same reference numerals.

A plurality of active elements 2, base electrodes 3 for capacitors, and resistance elements 4 are formed on one surface (main surface) of the semiconductor substrate 1, and the ground conductor 20 and the ground conductor 2 are provided via the dielectric film 10.
The conductors 20a and 20b which do not connect 0 are formed.
Here, a thin film capacitor (MIM capacitor) is formed by the capacitor base electrode 3 and the ground conductor 20, and the capacitor base electrode 3 and the conductor 20b.

Dielectric films 30 having a thickness of 1 μm or more are laminated in multiple layers on the ground conductor 20, and wirings (40, 41, 42, 43) are formed in or on the dielectric film 30. , Through hole 50 or through holes 51, 52
Through hole 1 penetrating through conductor 20a and dielectric film 10
1 is connected to the electrode 2a of the active element 2 on the substrate 1, the base electrode 3 for a capacitor, and the electrode 4a of the resistance element 4 on the substrate 1 to form a functional circuit.

A wire bonding pad 40p is formed simultaneously with the wiring 40 on the uppermost dielectric film 30a. Further, the dielectric film 60b is formed on the dielectric film 30a, the wiring 40, and the pad 40p, and the dielectric film 60b is formed.
The rearrangement wiring 70 is formed thereon, the dielectric film 60b is opened, and the pad 40p and the rearrangement wiring 70 are connected. Further, the dielectric film 60a is formed on the dielectric film 60b, the dielectric film 60a at the bonding pad position for flip chip mounting is opened, and the solder ball 72 is formed on the upper part thereof, and the solder ball 72 is a post metal. Rearrangement wiring 7 via 71
Connected to 0.

In the monolithic integrated circuit shown in FIG. 7, the ground conductor 20 is the selective ground plate and the pad 4
0p is a wire bonding pad, and the ground conductor 20
The manufacturing up to (including the conductors 20a and 20b simultaneously formed) is performed by a device process, and the manufacturing steps from the formation of the dielectric film 30 to the wiring 40 (including the pad 40p) are performed by the wiring process. The manufacturing process is performed by a bonding process.

According to the above second embodiment, the same effect as that of the first embodiment of the present invention can be obtained. Further, since the flip chip mounting bonding bump balls are manufactured, the MMIC chip can be directly mounted face down on the substrate. When the pitch size of the flip chip mounting bonding bumps is about the same as that of the wire bonding, it is not necessary to perform the rearrangement wiring, and the process steps (costs) are reduced.

Further, when the dielectric film 60 is made of resin or the like, it functions as an airtight seal, so that the reliability of the MMIC can be improved. Further, after the solder balls are mounted, by performing a dicing process for dividing the chips into individual chips at the wafer level, automatic flip chip mounting becomes possible.

Further, the same effect can be obtained even if the monolithic integrated circuit is manufactured by a semiconductor process of a manufacturer or a corporation which has different device processes, wiring processes and bonding processes. Further, the wiring process and the bonding process or the device process and the bonding process may be semiconductor processes of the same manufacturer or enterprise.

Further, as shown in FIG. 8, the uppermost layer wiring (here, the wiring 40) is produced by the manufacturing 123 by the wiring process.
Then, the passivation film 61 is formed by the same process.
The dielectric film 60 may be formed by covering the entire surface of the wafer with, and then removing part or all of the passivation film 61 in the manufacturing 125 by the bonding process.
In this case, the wafer can be protected at the time of delivery between different processes, and at the same time, the wafer manufactured in the manufacturing 123 by the wiring process can be stored for a long time and the bonding process can be performed at any time.

(Third Embodiment) FIG. 9 is a diagram showing a third embodiment of the method for manufacturing a monolithic integrated circuit according to the present invention. In FIG. 9, the same parts as those in FIG. 1 are designated by the same reference numerals.

In FIG. 9, first, in consideration of the required device characteristic specifications 100, the entire device is divided into functional blocks and each functional circuit specification 101 is determined. Next, the active device process 120 and the wiring process 1 that can satisfy the operating frequency, band, characteristics, etc. included in each functional circuit specification 101.
At the same time as selecting each item 21, the software 130 operating in the computer system is activated to read the characteristic parameters of the selected active device and the characteristic parameters of the transmission line, the inductor, etc. that can be formed in the wiring process from the accumulated data of the software 130. Circuit design 10
Do 3. Then, the circuit is simulated by the software 130 or another software to determine whether the designed circuit configuration satisfies the functional circuit specification 101.

If the specification 101 is not satisfied, the active device, transmission line parameters, circuit configuration, etc. are changed (read again), and the circuit design 103 is repeated so as to satisfy the functional circuit specification 101. When a functional circuit (for example, an amplifier) satisfying the functional circuit specification 101 is obtained, the actual circuit pattern design 104 is performed. At this time, the active device process 12 based on the reliability standard or the constraint condition in the manufacturing process is used.
0 circuit design rules and wiring process 121 design rules, and circuit design 1
Patterning is performed so as to match the circuit diagram obtained in step 03 with the maximum.

Here, when an error occurs in the circuit diagram obtained by the circuit design 103 and the equivalent circuit diagram laid out by the pattern design 104, the functional circuit specification 1
01 is satisfied, and if not satisfied, the circuit pattern (104), the circuit configuration is changed (103), etc., and the pattern design 104 is performed so as to satisfy the functional circuit specification 101.
Alternatively, the circuit design 103 and the pattern design 104 are repeated. Further, in the case of reducing the circuit area, the coupling between the wirings may become a non-negligible pattern. Therefore, the circuit design 103 is repeated using the analysis result of the electromagnetic field simulator operating in the computer system.
Satisfy the functional circuit specifications 101.

If necessary, the device process 120 and the wiring process 121 are changed so that the circuit design 1
03 and pattern design 104 are repeated. Functional circuit specifications 1
When a circuit pattern satisfying 01 is obtained, the circuit pattern is converted into data using software 130 or another software, and this data is used to perform the photomask 10 required for the device process 122 and the wiring process 123.
Create 5. Next, in the photomask 105,
After manufacturing 122 by a device process using the photomask 105 up to the selective ground conductor plate, manufacturing 123 by a wiring process is performed using the photomask 105 after the selective ground conductor plate to manufacture a monolithic integrated circuit on a semiconductor substrate. To do.

On-wafer evaluation 107 is performed to determine whether the manufactured monolithic integrated circuit matches the characteristics simulated by the circuit design 103 or the pattern design 104. As a result of the on-wafer evaluation 107, the manufactured functional circuit has specifications 10
When 1 is not satisfied, the cause is analyzed and the circuit pattern 1
04, circuit configuration change 103, etc. to perform device process manufacturing 122, wiring process manufacturing 123,
The on-wafer evaluation 107 is repeated.

Functional circuit specification 10 in on-wafer evaluation 107
When 1 is satisfied, the wafer is diced to assemble the functional circuits into individual pieces, the diced chips are assembled 108 on the mounting substrate, and the test / evaluation 109 is performed again. The functional circuit assembled in the test / evaluation 109 is the functional circuit specification 101.
Is satisfied, and if not satisfied, the cause is analyzed, and the assembly 108 is repeatedly corrected. When the assembled functional circuit satisfies the functional circuit specification 101, the monolithic integrated circuit is completed (delivered) 111 through reliability evaluation 110.

FIG. 10 is a diagram showing an image of a method of manufacturing the monolithic integrated circuit of the present invention in the third embodiment shown in FIG. The software 130 operating in the computer system includes a library in which a plurality of device process parameters and a plurality of wiring parameters are stored. The designer selects an active device process and a wiring process, and at the same time, a library relating to the selected process. Read the data.

Next, the circuit design function provided in the software 130 configures the functional circuit using the read library data, and the characteristic of the functional circuit is calculated by the built-in circuit simulator. Next, the designed circuit is patterned by the layout function of the software 130, and the characteristics of the functional circuit are verified using the pattern designed parameters. Once the characteristics are verified, software 1
The data conversion function provided in 30 converts the data into a stream file format or the like to create a photomask.

Next, after manufacturing by a device process using a photomask up to the selective ground conductor plate, manufacturing is performed by a wiring process using a photomask after the selective ground conductor plate, and monolithically integrated on the semiconductor substrate. Make a circuit. When the characteristics of the manufactured monolithic integrated circuit do not satisfy the specifications, software 130 is used for redesign.

According to the above third embodiment, the same effect as that of the first embodiment of the present invention can be obtained. In addition, the library data of active devices and high-frequency wiring required for the design is stored in the computer system or software running on the computer, so that the design speed of the monolithic integrated circuit can be increased and the development cost can be reduced. To realize. As a result, if the process design rule is stored in software and the function to automatically check after pattern design is added, it is possible to eliminate human error in pattern design and improve pattern design. Can be achieved. In addition, by storing the library data of the developed monolithic integrated circuit in software and reusing it, the circuit design and pattern design can be greatly shortened.

(Fourth Embodiment) FIG. 11 is a diagram showing a fourth embodiment of the method for manufacturing a monolithic integrated circuit according to the present invention. In FIG. 11, the same parts as those in FIG. 1 are designated by the same reference numerals.

In FIG. 11, first, in consideration of the required device characteristic specifications 100, the entire device is divided into functional blocks and each functional circuit specification 101 is determined. Next, the active device process 120 and the wiring process 1 that can satisfy the operating frequency, band, characteristics, etc. included in each functional circuit specification 101.
21 are selected respectively. The circuit design 103 is performed by using the initial characteristic parameters of the selected active device and the characteristic parameters of the transmission line and the inductor which can be formed by the wiring process.
And the designed circuit configuration is changed to a functional circuit specification 10 by a circuit simulator or the like that operates in a computer system.
Determine if 1 is satisfied.

If the specification 101 is not satisfied, the active device, transmission line parameters, circuit configuration, etc. are changed, and the circuit design 103 is repeated so as to satisfy the functional circuit specification 101. A functional circuit that satisfies the functional circuit specification 101 (for example,
Once the amplifier is obtained, the actual circuit pattern design 104
I do. At this time, the design rule specific to the active device process 120 and the design rule specific to the wiring process 121 based on the reliability standard and the constraint condition on the manufacturing process are respectively observed, and the circuit diagram obtained by the circuit design 103 is maximized. Pattern to match.

Here, when an error occurs in the circuit diagram obtained by the circuit design 103 and the equivalent circuit diagram laid out by the pattern design 104, the functional circuit specification 1
01 is satisfied, and if not satisfied, the circuit pattern (104), the circuit configuration is changed (103), etc., and the pattern design 104 is performed so as to satisfy the functional circuit specification 101.
Alternatively, the circuit design 103 and the pattern design 104 are repeated. Further, in the case of reducing the circuit area, the coupling between the wirings may become a non-negligible pattern. Therefore, the circuit design 103 is repeated using the analysis result of the electromagnetic field simulator operating in the computer system.
Satisfy the functional circuit specifications 101.

If necessary, the device process 120 and the wiring process 121 are changed so that the circuit design 1
03 and pattern design 104 are repeated. Functional circuit specifications 1
When a circuit pattern satisfying 01 is obtained, the circuit pattern is data-converted using software or the like operating in a computer system, and a part or all of the photomask required for the device process 122 is first created using this data. (105).

Next, using the created photomask 105, after the manufacturing process 122 by the device process, the active device characteristics are measured 126 on the wafer. When the obtained active device characteristics are equal to the initial characteristic parameters, the remaining photomask used in the device process 122 and the photomask used in the wiring process are created as necessary, and after the manufacturing process 122 in the device process is performed. A manufacturing process 123 is performed by a wiring process using the photomask 105 after the selective grounding conductor plate to manufacture a monolithic integrated circuit.

If the characteristics of the active device according to the on-wafer evaluation 126 are different from the initial parameters, the characteristic data is read into the circuit simulator operating in the computer system (127), the circuit is designed again, and the wiring parameters are changed. . Then, the changed wiring parameters and the like are converted into data, a mask necessary for the process is created 105, and a monolithic integrated circuit is manufactured through manufacturing by the wiring process or the device process and the wiring process.

Next, on-wafer evaluation 107 is performed to determine whether the manufactured monolithic integrated circuit matches the characteristics simulated by the circuit design 103 or the pattern design 104. As a result of the on-wafer evaluation 107, when the manufactured functional circuit specification 101 is not satisfied, the cause is analyzed, the circuit pattern 104, the circuit configuration change 103, etc. are performed, and the manufacturing 122 by the device process, the manufacturing 123 by the wiring process, the on-wafer evaluation. Repeat 107. When the functional circuit specifications 101 are satisfied in the on-wafer evaluation 107, the wafer is diced in order to separate the functional circuits into individual pieces, and the diced chips are assembled 108 on the mounting substrate and again tested / evaluated 109.

In the test / evaluation 109, it is determined whether the assembled functional circuit satisfies the functional circuit specification 101. If not, the cause is analyzed, and the assembly 108 is repeatedly corrected. When the assembled functional circuit satisfies the functional circuit specification 101, the monolithic integrated circuit is completed (delivered) 111 through reliability evaluation 110.

According to the above fourth embodiment, the same effect as that of the first embodiment of the present invention can be obtained. In addition, the characteristics of the active devices used before the wiring process are clarified, allowing circuit design considering the deviation of device characteristics due to the manufacturing process of active elements, and monolithic integration with less error between the design and actual measurement values. It becomes possible to realize a circuit. Further, since the characteristics of only the device process can be evaluated by the on-wafer evaluation 126, it is possible to easily isolate the defect due to the device process and the wiring process.

(Fifth Embodiment) FIG. 12 shows a fifth embodiment of the method for manufacturing a monolithic integrated circuit according to the present invention. In FIG. 12, the same parts as those in FIG. 1 are designated by the same reference numerals.

In FIG. 12, first, considering the required device characteristic specifications 100, the entire device is divided into functional blocks, and each functional circuit specification 101 is determined. Next, the active device process 120 that can satisfy the operating frequency, band, characteristics, etc. included in each functional circuit specification 101 is selected, and the master array using the selected active device is selected 128. Here, the master array is an array in which master cells each composed of a plurality of active devices, a plurality of resistors having different resistance values, and at least one of a plurality of capacitors having different resistance values are arranged in a matrix. As a similar conventional technology, there is a gate array technology in the LSI manufacturing (Kotaro Kato, "Basics of LSI Technology", Telecommunications Association, 1992). The master array may be composed of a plurality of different master cells.

Next, the wiring process 121 is selected, the circuit design 103 is performed using the characteristic parameters of the selected active device and the characteristic parameters of the transmission line, the inductor, etc. that can be formed by the wiring process, and the circuit operating in the computer system is selected. A simulator or the like determines whether the designed circuit configuration satisfies the functional circuit specification 101.

If the specification 101 is not satisfied, the active device, master array, transmission line parameters, circuit configuration, etc. are changed, and the circuit design 103 is repeated so as to satisfy the functional circuit specification 101. When a functional circuit (for example, an amplifier) satisfying the functional circuit specification 101 is obtained, the actual circuit pattern design 104 is performed. At this time, the active device process 12 based on the reliability standard or the constraint condition in the manufacturing process is used.
0 circuit design rules and wiring process 121 design rules, and circuit design 1
Patterning is performed so as to match the circuit diagram obtained in step 03 with the maximum.

Here, when an error occurs in the circuit diagram obtained by the circuit design 103 and the equivalent circuit diagram laid out by the pattern design 104, the functional circuit specification 1
01 is satisfied, and if not satisfied, the circuit pattern and the circuit configuration are changed, and the pattern design 104 or the circuit design 103 is performed so as to satisfy the functional circuit specification 101.
And the pattern design 104 are repeated. Further, in the case of reducing the circuit area, the coupling between the wirings may become a non-negligible pattern. Therefore, the circuit design 103 is repeated using the analysis result of the electromagnetic field simulator operating in the computer system. Satisfy the functional circuit specifications 101.

If necessary, the device process 120 and the wiring process 121 are changed so that the circuit design 1
03 and pattern design 104 are repeated. If the selected master array is new, a circuit design 10
3 or pattern design 104, in parallel with or in advance of the device process, a part or all of the photomask used for manufacturing the master array is created 129, and the manufacturing 122 by the device process is performed.

On the other hand, in the case of utilizing the existing master array, the manufacturing 122 is performed by the device process using the prepared photomask. When a circuit pattern satisfying the functional circuit specification 101 is obtained, the circuit pattern is converted into data using software operating in a computer system, and this data is used to perform the device process 122.
Then, a photomask 105 required for the wiring process 123 is created. In the case where the master array has already been manufactured, only the necessary mask is created 105, and after the manufacturing process 122 by the device process using the photomask 105 up to the selective ground conductor plate, the photomask after the selective ground conductor plate is used. A manufacturing process 123 is performed by a wiring process using 105 to manufacture a monolithic integrated circuit.

On-wafer evaluation 107 is performed to determine whether the manufactured monolithic integrated circuit matches the characteristics simulated in the circuit design 103 or the pattern design 104. As a result of the on-wafer evaluation 107, the manufactured functional circuit specification 101
If not satisfied, analyze the cause and analyze the circuit pattern 10
4. The circuit configuration change 103 and the like are performed, and the device process manufacturing 122, the wiring process manufacturing 123, and the on-wafer evaluation 107 are repeated. On-wafer evaluation 107
When the functional circuit specifications 101 are satisfied in step 1, the wafer is diced to assemble the functional circuits into individual pieces, and the diced chips are assembled on the mounting substrate 108, and the test / evaluation 1 is performed again.
09.

In the test / evaluation 109, it is judged whether the assembled functional circuit satisfies the functional circuit specification 101. If not, the cause is analyzed, and the assembly 108 is corrected repeatedly. When the assembled functional circuit satisfies the functional circuit specification 101, the monolithic integrated circuit is completed (delivered) 111 through reliability evaluation 110.

According to the fifth embodiment described above, the same effect as that of the first embodiment of the present invention can be obtained. Also, the circuit design 103
Since the master array can be manufactured by an active device process in parallel with or prior to the pattern design 104, the development period of the monolithic integrated circuit can be significantly shortened. Further, when the existing master array is used, it is possible to use the photomask that has already been formed, so that the process cost can be reduced.

(Sixth Embodiment) FIG. 13 is a diagram showing a sixth embodiment of the method for manufacturing a monolithic integrated circuit according to the present invention. 13, the same parts as those in FIG. 1 are designated by the same reference numerals.

In FIG. 13, first, the active device process 120 is considered in consideration of a required (functional) circuit specification 131 (for example, a high-power amplifier or a front end unit) corresponding to an existing or commercial wireless communication service.
And the wiring process 121 are selected. The circuit design 103 is performed using the characteristic parameters of the selected active device and the characteristic parameters of the transmission line and the inductor that can be formed by the wiring process, and the designed circuit configuration satisfies the circuit specifications 131 by the circuit simulator operating in the computer system. Determine whether to do.

If the circuit specification 131 is not satisfied, the active device, transmission line parameters, circuit configuration, etc. are changed, and the circuit design 103 is repeated so as to satisfy the circuit specification 131. When a circuit satisfying the circuit specifications 131 is obtained, the actual circuit pattern design 104 is performed. At this time, a design rule unique to the active device process 120 and the wiring process 12 based on the reliability standard and the constraint condition in the manufacturing process.
While complying with the design rules of 1 respectively,
Patterning is performed so as to match the circuit diagram obtained by the circuit design 103 as much as possible.

Here, when an error occurs in the circuit diagram obtained by the circuit design 103 and the equivalent circuit diagram laid out by the pattern design 104, the circuit specifications 131
Is determined, and if not satisfied, the circuit pattern (104), the circuit configuration is changed (103), etc., and the pattern design 104 or the circuit design 103 and the pattern design 104 are repeated so as to satisfy the circuit specification 131. Further, in the case of reducing the circuit area, the coupling between the wirings may become a non-negligible pattern. Therefore, the circuit design 103 is repeated using the analysis result of the electromagnetic field simulator operating in the computer system. Satisfy the circuit specifications 131.

If necessary, the device process 120 and the wiring process 121 are changed so that the circuit design 1
03 and pattern design 104 are repeated. Circuit specifications 131
When a circuit pattern satisfying the above conditions is obtained, the circuit pattern is converted into data using software or the like operating in a computer system, and this data is used to perform the photomask 10 required for the device process 122 and the wiring process 123.
Create 5. Next, in the photomask 105,
After manufacturing 122 by a device process using the photomask 105 up to the selective ground conductor plate, manufacturing 123 by a wiring process is performed using the photomask 105 after the selective ground conductor plate to manufacture a monolithic integrated circuit on a semiconductor substrate. To do.

On-wafer evaluation 107 is performed to determine whether the manufactured monolithic integrated circuit matches the characteristics simulated in the circuit design 103 or the pattern design 104. As a result of the on-wafer evaluation 107, the manufactured functional circuit specification 101
If not satisfied, analyze the cause and analyze the circuit pattern 10
4. The circuit configuration change 103 and the like are performed, and the device process manufacturing 122, the wiring process manufacturing 123, and the on-wafer evaluation 107 are repeated. On-wafer evaluation 107
If the circuit specifications 131 are satisfied in step S1, the wafer is diced to assemble the functional circuits into individual pieces, and the diced chips are assembled on the mounting substrate 108, and the test / evaluation 109 is performed again.
To do.

It is judged whether the functional circuit assembled in the test / evaluation 109 satisfies the circuit specification 131. If not, the cause is analyzed, and the assembly 108 is repeatedly corrected. When the assembled functional circuit satisfies the circuit specifications 131, the monolithic integrated circuit is completed (delivered) 111 after reliability evaluation 110. In FIG. 13, all or part of the monolithic integrated circuit manufactured through the manufacturing 123 by the wiring process may be immediately diced and tested / evaluated.

According to the above sixth embodiment, the same effect as that of the first embodiment of the present invention can be obtained. In addition, monolithic integrated circuits used in various wireless communication systems and devices can be rapidly developed or manufactured.

(Seventh Embodiment) FIG. 14 is a diagram showing a seventh embodiment of the method for manufacturing a monolithic integrated circuit according to the present invention. In FIG. 14, the same parts as those in FIG. 1 are designated by the same reference numerals.

In FIG. 14, first, in consideration of a required (functional) circuit specification 131 (for example, a high-power amplifier or a front end unit) corresponding to an existing or commercialized wireless communication service, it has already been developed or Active device process 120 and wiring process 12 with proven track record
Select 1 respectively. The circuit design 103 is performed using the characteristic parameters of the selected active device and the characteristic parameters of the transmission line and the inductor that can be formed by the wiring process, and the designed circuit configuration satisfies the circuit specifications 131 by the circuit simulator operating in the computer system. Determine whether to do.

When the circuit specifications 131 are not satisfied, the circuit configuration and the like are changed, and the circuit design 103 is repeated so as to satisfy the circuit specifications 131. When a circuit satisfying the circuit specifications 131 is obtained, the actual circuit pattern design 104 is performed. At this time, the design rule specific to the active device process 120 and the design rule specific to the wiring process 121 based on the reliability standard and the constraint condition on the manufacturing process are respectively observed, and the circuit diagram obtained by the circuit design 103 is maximized. Pattern to match.

Here, when an error occurs in the circuit diagram obtained by the circuit design 103 and the equivalent circuit diagram laid out by the pattern design 104, the circuit specification 131
Is determined, and if not satisfied, the circuit pattern (104), the circuit configuration is changed (103), etc., and the pattern design 104 or the circuit design 103 and the pattern design 104 are repeated so as to satisfy the circuit specification 131.

Further, when the circuit area is miniaturized, the coupling between the wirings may be a pattern that cannot be ignored. Therefore, the circuit design 103 is performed by using the analysis result of the electromagnetic field simulator operating in the computer system. Is repeated to satisfy the circuit specification 131. Circuit specifications 131
When a circuit pattern satisfying the above conditions is obtained, the circuit pattern is converted into data using software or the like operating in a computer system, and this data is used to perform the photomask 10 required for the device process 122 and the wiring process 123.
Create 5.

Then, of the photomasks 105, after the manufacturing process 122 using the photomasks 105 up to the selective grounding conductor plate, the manufacturing process 122 using the photomasks 105 after the selective grounding conductor plate is performed by the wiring process. Step 123 is performed to fabricate a monolithic integrated circuit on the semiconductor substrate. On-wafer evaluation of whether the manufactured monolithic integrated circuit matches the characteristics simulated by the circuit design 103 or the pattern design 104.
7.

As a result of the on-wafer evaluation 107, when the manufactured functional circuit does not satisfy the specification 101, the cause is analyzed and the circuit pattern 104, the circuit configuration change 103, etc. are performed, and the manufacturing 122 by the device process and the manufacturing by the wiring process are performed. 123, the on-wafer evaluation 107 is repeated.
When the circuit specifications 131 are satisfied in the on-wafer evaluation 107, the wafer is diced to assemble the functional circuits into individual pieces, and the diced chips are assembled on the mounting substrate 10
8. Test / evaluate 109 again.

In the test / evaluation 109, it is determined whether the assembled functional circuit satisfies the circuit specification 131. If not, the cause is analyzed, and the assembly 108 is repeatedly corrected.
When the assembled functional circuit satisfies the circuit specifications 131, the monolithic integrated circuit is completed (delivered) 111 after reliability evaluation 110. In FIG. 13, all or part of the monolithic integrated circuit manufactured through the manufacturing 123 by the wiring process may be immediately diced and tested / evaluated.

According to the above seventh embodiment, the same effect as that of the sixth embodiment of the present invention can be obtained. In addition, monolithic integrated circuits used in various wireless communication systems and devices can be rapidly developed or manufactured. In FIG. 13, since the active device process 120 and the wiring process 121 which have already been developed or manufactured are used, the assembled functional circuit is completed (delivered) 111 without performing the test / evaluation 109 and the reliability evaluation 110. Is also good.
In this case, it is possible to reduce the number of test steps performed until the wireless communication system or device is realized, and thus it is possible to reduce the manufacturing cost and the period of the wireless communication system or device.

(Eighth Embodiment) FIG. 15 is a diagram showing a first embodiment of the method for manufacturing a monolithic integrated circuit according to the present invention. In FIG. 15, the same parts as those in FIG. 1 are designated by the same reference numerals.

In FIG. 15, a monolithic integrated circuit satisfying a required (functional) circuit specification 131 (for example, a high-power amplifier or a front end section) corresponding to an existing or commercialized wireless communication service has already been designed / designed. The flow chart shows the manufacturing method after development and verification of reliability evaluation. The company (or group) that designed / developed a monolithic integrated circuit received an order for a (functional) circuit from a company (or group) that integrates a wireless communication system or device 132 (simultaneously with circuit specification 1
31 is given), and then a selective ground conductor plate is manufactured by manufacturing 122 by a device process using a photomask that has already been manufactured, and then manufacturing 123 by a wiring process is performed to manufacture a monolithic integrated circuit on a semiconductor substrate. To do.

In order to divide the manufactured monolithic integrated circuit into individual pieces, the wafer is diced, and the diced chips are assembled 108 on the mounting substrate and tested / evaluated 109. In the test / evaluation 109, it is determined whether the assembled functional circuit satisfies the circuit specifications 131. If the functional circuit is not satisfied, the cause is analyzed, and the assembly 108 is repeatedly corrected. When the assembled functional circuit satisfies the circuit specification 131, the assembled functional circuit is delivered to the company (or group) in which it was generated.

According to the above eighth embodiment, the same effect as that of the first embodiment of the present invention can be obtained. Further, it is possible to rapidly and mass-produce monolithic integrated circuits used for various wireless communication services and the like. In FIG. 15, all or part of the assembled functional circuit may be delivered directly. In this case, the company (or group) that integrates the wireless communication system or device can perform the test / evaluation as the system or device and reduce the test process until the whole system or device is realized. It is possible to reduce the manufacturing cost and period of the system or device.

Also, in FIG. 15, the company (or group) that integrates the wireless communication system or device and the company (or group) that designs / develops the monolithic integrated circuit may be the same company (or group).

(Ninth Embodiment) FIG. 16 is a diagram showing a second embodiment of the method for manufacturing a monolithic integrated circuit according to the present invention. 16 that are the same as those in FIG. 1 are designated by the same reference numerals.

In FIG. 16, a monolithic integrated circuit satisfying a required (functional) circuit specification 131 (for example, a high-power amplifier or a front end section) corresponding to an existing or commercialized wireless communication service has already been designed / designed. The flow chart shows the manufacturing method after development and verification of reliability evaluation. The company (or group) that designed / developed the monolithic integrated circuit received an order for the functional circuit from the company (or the group) that integrates the wireless communication system or device 132 (simultaneously with the functional circuit specification 1
31 is given), and then a selective ground conductor plate is manufactured by manufacturing 122 by a device process using a photomask that has already been manufactured, and then manufacturing 123 by a wiring process is performed to manufacture a monolithic integrated circuit on a semiconductor substrate. To do. In order to divide the manufactured monolithic integrated circuit into individual pieces, the wafer is diced and delivered (completed) 111 to the company (or group) that ordered the diced chips.

According to the ninth embodiment, the same effect as that of the first embodiment of the present invention can be obtained. Further, it is possible to rapidly and mass-produce monolithic integrated circuits used for various wireless communication services and the like. In addition, since a company (or group) that integrates wireless communication systems or devices assembles and implements functional circuits and tests and evaluates the systems or devices, the manufacturing cost and period of monolithic integrated circuits and wireless communication systems or devices Can be reduced. In FIG. 16, the company (or group) that integrates the wireless communication system or device and the company (or group) that designs / develops the monolithic integrated circuit may be the same company (or group).

[0144]

As described above, according to the present invention, the development of active elements (transistors and FETs) and the development of interconnection technology for forming wiring layers are divided into different manufacturers (or enterprises). Therefore, it is possible to reduce dispersion of process development cost and investment risk in each manufacturer (or enterprise). In addition, since each manufacturer (or company) involved in the production and development of a monolithic integrated circuit (MMIC) can specialize in the development of active devices and the development of interconnection technology, strategic devices and high-density wiring can be used. It can be developed in a shorter period than before.

Further, even in a company that does not have a manufacturing process of active elements, it is necessary to develop an interconnection technology with a much smaller investment than device development and to enter a monolithic integrated circuit (MMIC) development which can be expected to have great marketability. Is possible. In addition, the circuit designer can design a high-frequency circuit by combining a device having desired characteristics with a desired wiring (interconnection) technology, which greatly improves the degree of freedom in design and also the market needs. It is possible to develop a high-performance MMIC tailored to.

As a result, the development of the monolithic integrated circuit (MMIC) led by the designer can be realized, so that the cost reduction and the shortening of the development period of the monolithic integrated circuit (MMIC) are dramatically promoted. In addition, since the photomask manufactured from circuit data is divided and used by the manufacturers (or corporations) who manufacture active devices and wiring, the information is kept secret even in strategic functional circuits compared to the past. It

[Brief description of drawings]

FIG. 1 is a manufacturing flow chart showing a first embodiment of a method for manufacturing a monolithic integrated circuit according to the present invention.

FIG. 2 is a cross-sectional view of a first monolithic integrated circuit manufactured according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a part of another manufacturing flow showing the first embodiment of the method of manufacturing a monolithic integrated circuit according to the present invention.

FIG. 4 is a cross-sectional view of a second monolithic integrated circuit manufactured according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view of a third monolithic integrated circuit manufactured according to the first embodiment of the present invention.

FIG. 6 is a manufacturing flow chart showing a second embodiment of the method for manufacturing a norric integrated circuit according to the present invention.

FIG. 7 is a cross-sectional view of a monolithic integrated circuit manufactured according to the second embodiment of the present invention.

FIG. 8 is a diagram showing a part of another manufacturing flow showing the second embodiment of the method of manufacturing a monolithic integrated circuit according to the present invention.

FIG. 9 is a manufacturing flow chart showing the third embodiment of the method for manufacturing a monolithic integrated circuit according to the present invention.

FIG. 10 is an image diagram of a method for manufacturing a monolithic integrated circuit according to a third embodiment of the present invention.

FIG. 11 is a manufacturing flowchart showing the fourth embodiment of the method for manufacturing a monolithic integrated circuit according to the present invention.

FIG. 12 is a manufacturing flow chart showing a fifth embodiment of the method for manufacturing a monolithic integrated circuit according to the present invention.

FIG. 13 is a manufacturing flow chart showing a sixth embodiment of the method for manufacturing a monolithic integrated circuit according to the present invention.

FIG. 14 is a manufacturing flow chart showing a seventh embodiment of the method for manufacturing a monolithic integrated circuit according to the present invention.

FIG. 15 is a manufacturing flow chart showing an eighth embodiment of the method for manufacturing a monolithic integrated circuit according to the present invention.

FIG. 16 is a manufacturing flow chart showing the ninth embodiment of the method for manufacturing a monolithic integrated circuit according to the present invention.

FIG. 17 is a manufacturing flow chart showing a conventional method for manufacturing a monolithic integrated circuit.

FIG. 18 is a plan view of a first conventional monolithic integrated circuit manufactured by the conventional method for manufacturing a monolithic integrated circuit.

FIG. 19 is a perspective view of a second conventional monolithic integrated circuit manufactured by the conventional method for manufacturing a monolithic integrated circuit.

[Explanation of symbols]

1 Semiconductor substrate 2 Active element (transistor or FET) 2a, 4a electrodes 3 Capacitor base electrode 4 resistance 10 First dielectric film 11, 12, 13, 50, 51, 52 Through hole 14, 15, 40, 41, 42, 43 Wiring 20 ground conductor 20a, 20b conductor 21 First passivation film 22 Dielectric film 30 Second dielectric film 40, 41, 42, 42 wiring 40p wire bonding pad 60 Third dielectric film 61 Second passivation film 70 Relocation wiring 71 post metal 72 Solder ball 100 Device Specifications / Specifications 101 Functional design 102 Selection of semiconductor process 103 circuit design 104 pattern design 105 Mask making 106 Manufacturing by semiconductor process 107 On-wafer evaluation 108 Assembly 109 test and evaluation 110 Reliability evaluation 111 Completed and delivered 120 Device process selection 121 Selection of wiring process 122 Manufacturing by device process 123 Manufacturing by wiring process 124 Bonding Process Selection 125 Manufacturing by bonding process On-wafer evaluation of 126 devices 127 Device data correction 128 Master Array Selection 129 Master array mask creation 130 software 131 circuit specifications 132 Order for monolithic integrated circuit 200 Semiconductor substrate 201 FET 202 resistance 203 Capacitor 204 inductor 205 wiring 206 Capacitor base electrode 210,230 Dielectric film 211 holes in the dielectric film 210 220 ground conductor 220b conductor 221 through hole 222 Opening of ground conductor 220 240 wiring

Continuation of front page (56) References JP-A-8-162621 (JP, A) JP-A-11-163642 (JP, A) JP-A-5-299622 (JP, A) JP-A-10-93219 (JP , A) JP-A-6-29391 (JP, A) JP-A-9-69568 (JP, A) JP-A-2000-12697 (JP, A) JP-A-9-198413 (JP, A) JP-A-7 -183473 (JP, A) JP-A-6-21222 (JP, A) JP-A-8-167703 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/822 G06F 17/50 H01L 21/82 H01L 27/04

Claims (15)

(57) [Claims] 1. A semiconductor substrate having a plurality of active elements and passive elements formed on a surface thereof, a first dielectric film formed on the active elements and the passive elements, and a first dielectric film on the first dielectric film. Formed on the active element and the passive element, the window is formed on the active element and the passive element used in the active element and the passive element, and the cover section is formed on the active element and the passive element. A selective ground conductor plate covering the active element and the passive element used, a second dielectric film formed on the selective ground conductor plate, and a wiring formed on the film of the second dielectric film. In a method of manufacturing a Morrisic integrated circuit comprising a layer and a connecting means for connecting the active element and the passive element to be used to the wiring layer, the entire apparatus is divided into functional blocks in consideration of required device characteristic specifications. Performance suitable for functional circuit specifications Each active device processes specific for fabricating the device and the wiring layer
A design step for designing a circuit by selecting a design rule and a design rule specific to the wiring process , and designing a circuit pattern for the designed circuit configuration to create the active device.
A step of forming a photomask used in the chair process and the wiring process ; and performing steps of forming the selective ground conductor plate by the active device process using the photomask of the photomask up to the selective ground conductor plate. And using a photomask after the selective grounding conductor plate
A step of performing a manufacturing process after the selective grounding conductor plate by the wiring process, the manufacturing method of a monolithic integrated circuit. 2. After the selective ground conductor plate is formed by the active device process, the entire surface of the wafer is covered with a first passivation film, and then part or all of the first passivation film is removed by the wiring process. The method for manufacturing a monolithic integrated circuit according to claim 1, wherein 3. The method of manufacturing a monolithic integrated circuit according to claim 1, wherein the wiring layer is a multilayer wiring layer, and the first bonding pad is formed by the uppermost wiring. 4. The method of manufacturing a monolithic integrated circuit according to claim 1, wherein one or more wiring layers are formed between the semiconductor substrate and the selective ground conductor plate. 5. The active device process, wherein the entire device is divided into functional blocks in consideration of the required device characteristic specifications, and active devices, wiring layers and second bonding pads suitable for each functional circuit specification are manufactured. Unique design route
Design rules and bondies specific to the wiring process
A step of designing a circuit by selecting a design rule specific to the wiring process, designing a circuit pattern of the designed circuit configuration, and designing the active device process, the wiring process and the wiring process.
A method of fabricating a photomask used for fine the bonding process, one of the photomask, the active by using a photomask to said selected ground conductor plate
Performing a step up to the formation of the selective ground conductor plate by a device process, and the wiring process and the bonding using a photomask from the selective ground conductor plate to the first bonding pad
A step of performing a manufacturing process after the selective grounding conductor plate by a process, and rearranging the first bonding pad on a second bonding pad at a different position using a photomask after the first bonding pad, Forming a third dielectric film on the entire surface, and providing a window of the third dielectric film on the second bonding pad, the solder ball formed on the third dielectric film, and the solder ball formed on the third dielectric film. 5. The method of manufacturing a monolithic integrated circuit according to claim 3, further comprising the step of connecting two bonding pads. The method according to claim 6, wherein said first bonding pads after the part or by using all of the photomask bonding <br/> process, which comprises carrying out the first bonding pads subsequent fabrication step A method of manufacturing a monolithic integrated circuit according to claim 5. 7. The first bonding pad is formed by the wiring process, the entire surface of the wafer is covered by a second passivation film, and then part or all of the second passivation film is removed by the bonding process. 7. The method for manufacturing a monolithic integrated circuit according to claim 5, wherein: 8. Information of active elements and passive elements manufactured in the active device process, information of wiring manufactured in the wiring process, and information of relocation wirings and ball bumps manufactured in the bonding process. 8. The monolithic integrated circuit according to claim 1, wherein a part or all of the monolithic integrated circuit is stored in a computer system, and circuit design and pattern design are carried out by using information received from the computer system. Manufacturing method. 9. Information on active and passive elements manufactured by a plurality of the active device processes in the computer system, information on a wiring layer manufactured by a plurality of the wiring processes, and manufacturing by a plurality of the bonding processes. 9. The method for manufacturing a monolithic integrated circuit according to claim 8, wherein a part or all of the information of the relocated wiring and the ball bump to be stored is stored and part or all of the information can be deleted or updated. 10. A manufacturing process is performed by the active device process using a part or all of the photomask up to the selective ground conductor plate of the photomask, and the manufactured active element is measured, and the measurement is performed. perform circuit design by using the obtained information, to create a photomask required for the remainder of the active device process and the circuit pattern design a circuit arrangement designed, the said active device process <br/> scan 10. The method for manufacturing a monolithic integrated circuit according to claim 1, wherein the monolithic integrated circuit is manufactured by using a wiring process or only the wiring process. 11. A master array in which master cells each including a plurality of active elements, at least one of a plurality of resistors having different resistance values and at least one of a plurality of capacitors having different resistance values are arranged in a matrix on the semiconductor substrate. The active device process for dividing the entire device into functional blocks in consideration of the required device characteristic specifications and manufacturing active devices and wiring layers suitable for each functional circuit specification
11. The method for manufacturing a monolithic integrated circuit according to claim 1, wherein the master array including the wiring process and the active device is selected for circuit design. 12. An active device process and a process for producing an active device and a wiring layer suitable for a required functional circuit specification.
A step of selecting a wiring process and designing a circuit,
The active circuit is designed by designing a circuit pattern of the designed circuit configuration.
And creating a photomask used in a chair process and the wiring process among the photomask, using said photomask to said selected ground conductor plate
A step of forming the selective grounding conductor plate by an active device process, and a manufacturing process of the selective grounding conductor plate and the subsequent steps by the wiring process using a photomask after the selective grounding conductor plate. The method for manufacturing a monolithic integrated circuit according to any one of claims 1 to 11, further comprising: 13. The active method using an existing photomask.
2. A monolithic integrated circuit is manufactured on a semiconductor substrate by performing steps up to formation of the selective grounding conductor plate by a device process and performing fabrication steps after the selective grounding conductor plate by the wiring process. 13. The method for manufacturing a monolithic integrated circuit according to any one of items 1 to 12. 14. The steps up to the selected ground conductor plate forming performed by the active device process, the distribution
A manufacturing process after the selective grounding conductor plate is performed by a line process, a monolithic integrated circuit is manufactured on a semiconductor substrate, and all the manufactured semiconductor substrates are diced to separate the functional circuits into individual pieces. A method of manufacturing a monolithic integrated circuit according to claim 1. 15. The method of manufacturing a monolithic integrated circuit according to claim 1, wherein the semiconductor substrate is a compound semiconductor substrate.