JP3558057B2 - Audio coding apparatus and method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an audio encoding device and method, and more particularly to an audio encoding method for encoding audio of a plurality of channels.
[0002]
[Prior art]
FIG. 6 is a schematic block diagram of an audio encoding device for encoding audio signals of a plurality of channels. FIG. 6 shows a system LSI 101 for encoding audio signals of two channels, and CPU cores 102 and 103 are provided for each channel. A memory 104 and a memory control circuit 105 are provided in common for these CPU cores 102 and 103, and these CPU cores and memory control circuits are connected by a bus 107. The access to the memory 104 via 105 is free.
[0003]
The CPU core 101 performs audio encoding processing of channel # 0, and the CPU core 102 performs audio encoding processing of channel # 1. Here, it is a well-known fact that speech encoding processing requires arithmetic processing such as an impulse response and a correlation function, and that such arithmetic processing requires continuous product-sum operations (for example, JP-A-2000-250895 and JP-A-11-15660). The speech encoding process including the equal product sum operation is executed in parallel using the CPU cores 102 and 103 for each channel.
[0004]
[Problems to be solved by the invention]
As shown in FIG. 6, in a conventional speech encoding apparatus, encoding processing of speech signals of a plurality of channels is executed separately and in parallel by CPU cores 102 and 103 in a system LSI 101. In this case, since the circuit size of the CPU core is extremely large, the provision of this large-scale CPU core incorporated in the system LSI 101 for each channel results in a large-scale system LSI itself. There is a problem that it is extremely disadvantageous in terms of hardware and cost.
[0005]
SUMMARY OF THE INVENTION An object of the present invention is to provide a speech coding apparatus and a method thereof which are advantageous in terms of hardware and cost by reducing the circuit scale.
[0006]
[Means to solve the problem]
According to the present invention, there is provided an audio encoding device that performs an encoding process on audio signals of a plurality of channels, and an encoding processing unit that performs an encoding process other than a product-sum operation process in the encoding process on the audio signal. And a sum-of-products processing means for performing the sum-of-products processing, wherein the coding processing means performs coding processing of another channel during execution of the sum-of-products processing of one channel. Thus, there is provided a speech coding apparatus characterized by the above.
[0007]
The product-sum operation processing means performs the product-sum operation processing of another channel while the encoding processing means is executing the encoding processing of one channel, and the encoding processing means When the product-sum operation is required during the encoding process of a certain channel, the product-sum operation means is instructed to the information necessary for the product-sum operation, and the execution instruction of the product-sum operation is instructed. And a means for shifting to encoding processing of another channel after that, wherein the product-sum operation processing means uses the information in response to the execution instruction and uses the product-sum operation processing of the certain channel. Characterized in that it has means for:
[0008]
Further, the product-sum operation means has means for outputting an interrupt signal indicating the end of the product-sum operation processing to the encoding processing means in response to the end of the product-sum operation processing, and the encoding processing means responds to the interruption signal. Means for responding and restarting the encoding process of the certain channel using the result of the product-sum operation process. Further, a memory which is accessible by the encoding processing means and the product-sum operation processing means and can store the processing results is further included. The memory is a dual-port memory that can be accessed in parallel by the encoding processing means and the product-sum operation processing means.
[0009]
According to the present invention, encoding processing means for performing an encoding process other than the product-sum operation process in the audio signal encoding process, and product-sum operation processing means for performing the product-sum operation process, the multi-channel What is claimed is: 1. An encoding method in an audio encoding device that performs an encoding process on an audio signal, wherein said encoding processing unit performs encoding of another channel while the product-sum operation unit is executing a product-sum operation process of one channel. Thus, a speech coding method characterized by performing a coding process is obtained.
[0010]
The product-sum operation processing means performs the product-sum operation processing of another channel while the encoding processing means is executing the encoding processing of one channel, and the encoding processing means In the above, when the product-sum operation is required during the encoding process of a certain channel, information necessary for the product-sum operation is instructed to the product-sum operation means and execution instruction of the product-sum operation is given. And, after that, shifting to the encoding process of another channel. In the product-sum operation processing means, the product-sum operation of the certain channel is performed using the information in response to the execution instruction. It is characterized by having a step of performing processing.
[0011]
Further, the product-sum operation processing means includes a step of outputting an interrupt signal indicating the end of the product-sum operation processing to the encoding processing means in response to the end of the product-sum operation processing. A step of restarting encoding processing of the certain channel using a result of the product-sum operation processing in response to a signal.
[0012]
The operation of the present invention will be described. An encoding processing unit (CPU) that divides a product-sum operation process and another encoding process in the audio encoding process and performs an encoding process other than the product-sum operation, and a product-sum operation process dedicated to the product-sum operation Parts are provided. Then, when the CPU is executing the encoding processing of a certain channel, the operation control is performed so that the product-sum operation processing unit executes the product-sum operation processing of another channel. By doing so, it is not necessary to provide a large-scale CPU core for each channel, and the overall circuit scale can be reduced.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of an embodiment of the present invention. A system LSI 1 includes a CPU core 2, a product-sum operation circuit 3, a memory 4, and a memory control circuit 5. . The CPU core 2 accesses the product-sum operation circuit 3 and the memory control circuit 5 via the bus 7, and the product-sum operation circuit 3 accesses the memory control circuit 5 via the bus 7. Therefore, the memory 4 is freely accessible by the CPU core 2 and the product-sum operation circuit 3. Further, the product-sum operation circuit 3 notifies the CPU 2 of the end of the predetermined processing using the interrupt 6, and the CPU core 2 receives the operation result via the bus 7.
[0014]
In the configuration of FIG. 1, it is assumed that the CPU core 2 performs an encoding process other than the product-sum operation in the audio signal encoding process, and the product-sum operation circuit 3 has a function of performing the product-sum operation.
[0015]
Therefore, when the CPU core 2 starts speech coding of a certain channel and needs a product-sum operation, the CPU core 2 sends the product-sum operation circuit 3 the start address of the two variables to be subjected to the product-sum operation and the operation. A total of three variables of the number of times are notified via the bus 7. The product-sum operation circuit 3 reads variable values from the memory 4 via the bus 7 and executes the product-sum operation. As a result, the CPU core 2 can perform the speech encoding process of another channel while the product-sum operation circuit 3 is executing the continuous product-sum operation process. When the predetermined processing is completed, the product-sum operation circuit 3 notifies the CPU core 2 to that effect using the interrupt 6. The CPU core 2 receives the calculation result from the sum-of-products calculation circuit 3 and restarts the encoding process of the certain channel.
[0016]
FIG. 2 is a block diagram showing a specific configuration example of the product-sum operation circuit 3 in the embodiment of FIG. 1, and FIG. 3 is a flowchart showing the operation of the state machine 24 in FIG. In FIG. 2, the product-sum operation circuit 3 includes a state machine 24, a register 20, a bus control unit 21, a FIFO 22, a FIFO 23, and a product-sum operation unit 25. The register 20 stores the head address of the memory storing the two variables to be subjected to the product-sum operation notified from the CPU core 2 and the number of operations. The register 20 also stores an execution instruction notified from the CPU core 2, and the execution instruction is notified to the state machine 24 via the processing start signal 30 (step S1 in FIG. 3).
[0017]
The state machine 24 notifies the bus control unit of the memory read instruction using the memory read instruction signal 31 (step S2 in FIG. 3). The bus control unit 21 reads the start addresses of the two variables and the number of operations from the register 20 using the register data signal 32. The bus control unit 21 stores the data of the two variables in the FIFO 22 and the FIFO 23 using the data signal 33 and the data signal 34, respectively, and notifies the state machine 24 that the memory read is completed using the memory read completion signal 35. Notify (step S3 in FIG. 3).
[0018]
The state machine 24 notifies the product-sum calculator 25 of the calculation execution instruction using the calculation execution instruction signal 36 (step S4 in FIG. 3). The product-sum calculator 25 notifies the register 20 of the calculation result using the calculation result data signal 37, and notifies the state machine 24 of the completion of the calculation using the calculation completion signal 38 (step S5 in FIG. 3). ). The state machine 24 notifies the register 20 of the interrupt output instruction using the interrupt output instruction signal 39 (step S6 in FIG. 3).
[0019]
Next, the operation of the circuit shown in FIG. 1 will be described with reference to the sequence diagram of FIG. In the CPU core 2, the audio encoding process of channel 0 (shown as CH0 in FIG. 4) is started. When continuous product-sum operation processing becomes necessary, the CPU core 2 sets the address of the two variables and the number of operations to the product-sum operation circuit 3 in the register of the product-sum operation circuit 3 and issues an execution instruction.
[0020]
The CPU core 2 allocates the processing time to the channel 1 (shown as CH1 in FIG. 4) when the processing result of the product-sum operation circuit 3 is awaited in the channel encoding process. The product-sum operation circuit 3 receives the execution instruction, accesses the memory control unit 5, reads the data of the variable, and executes the product-sum operation. The product-sum operation circuit 3 notifies the CPU core 2 of the completion of the product-sum operation using the interrupt 6.
[0021]
On the other hand, in the CPU core 2, where continuous product-sum operation is required in the encoding process of channel 1, the product-sum operation circuit 3 similarly calculates the address of two variables and the number of operations by the product-sum operation. It is set in the register of the circuit 3 and an execution instruction is issued. The CPU core 2 allocates a processing time to the channel 0 when the processing result of the product-sum operation circuit 3 is awaited in the audio coding processing of the channel 1. Since the interrupt 6 is active, the CPU core 2 accesses the product-sum operation circuit 3, receives the processing result of the channel 0, and restarts the encoding processing of the channel 0.
[0022]
FIG. 5 is a block diagram showing the configuration of another embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. In this example, a dual-port memory is used as the memory 4, a memory control circuit 8 is added in addition to the memory control circuit 5, and a memory bus 9 connects between the memory control circuit 8 and the product-sum operation circuit 3. It is configured to connect.
[0023]
When the CPU core 2 and the product-sum operation circuit 3 frequently access the memory, a problem arises in that the processing time of the CPU core 2 is taken as the memory access waiting time due to access competition. Therefore, in the present embodiment, as shown in FIG. 5, the product-sum operation circuit 3 is made accessible through the memory bus 9 and the memory control circuit 8 using the dual-port memory 4, and the product-sum operation is performed with the CPU core 2. The memory access conflict with the circuit 3 is prevented.
[0024]
Since the CPU core 2 and the product-sum operation circuit 3 perform audio coding processing of different channels, the number of simultaneous accesses to the same memory address is extremely small. By doing so, it is possible to prevent a decrease in processing performance due to a memory access conflict between the CPU core 2 and the product-sum operation circuit 3.
[0025]
【The invention's effect】
As described above, according to the present invention, the speech encoding process is divided into a product-sum operation process and other encoding processes, and the CPU core performs the other encoding process, and the product-sum operation process is performed. Since the dedicated sum-of-products calculation circuit is used, when the sum-of-products calculation circuit is performing the sum-of-products calculation for a certain channel, the CPU core may perform the encoding processing for the other channels in parallel. Therefore, there is an effect that the voice coding processing of a plurality of channels can be efficiently executed.
[0026]
In particular, as compared with the conventional method in which a CPU core is provided for each channel for audio coding processing of a plurality of channels, the product-sum operation circuit is separated and a dedicated circuit is provided to reduce the load on the CPU core. This eliminates an increase in the circuit scale of the CPU core, which is advantageous in terms of hardware and cost. Since the product-sum operation circuit may have a relatively small circuit configuration, the advantage of separating the product-sum operation circuit is greater.
[Brief description of the drawings]
FIG. 1 is a block diagram of one embodiment of the present invention.
FIG. 2 is a block diagram showing a specific example of a product-sum operation circuit in the block of FIG. 1;
FIG. 3 is a flowchart illustrating an operation of the state machine of FIG. 2;
FIG. 4 is a sequence diagram showing an operation of one embodiment of the present invention.
FIG. 5 is a block diagram of another embodiment of the present invention.
FIG. 6 is a block diagram illustrating an example of a conventional technique.
[Explanation of symbols]
1 System LSI
2 CPU core 3 Product-sum operation circuit 4 Memory 5, 8 Memory control circuit 6 Interrupt 7 Bus 9 Memory bus

Claims (10)

What is claimed is: 1. An audio encoding device that performs an encoding process on audio signals of a plurality of channels, comprising: an encoding processing unit that performs an encoding process excluding a product-sum operation process in the audio signal encoding process; Wherein the encoding processing means performs encoding processing of another channel during execution of the product-sum operation processing of one channel. Characteristic speech encoding device. 2. A speech coding apparatus according to claim 1, wherein said product-sum operation processing means performs the product-sum operation processing of another channel while said coding processing means is executing the coding processing of one channel. apparatus. The encoding processing means, when the sum-of-products processing becomes necessary during the encoding processing of a certain channel, instructs the sum-of-products processing means with information necessary for the sum-of-products processing, and Means for instructing the execution of the sum operation, and means for shifting to encoding processing of another channel after that,
3. The speech coding apparatus according to claim 1, wherein said product-sum operation processing means includes means for performing a product-sum operation for the certain channel using the information in response to the execution instruction. The product-sum operation processing means has means for outputting an interrupt signal to that effect to the encoding processing means in response to the end of the product-sum operation processing,
4. The speech coding apparatus according to claim 3, wherein said coding processing means has means for restarting coding processing of the certain channel using a result of the product-sum calculation processing in response to the interrupt signal. . 5. The speech encoding apparatus according to claim 1, further comprising a memory accessible by said encoding processing means and said product-sum operation processing means and capable of storing the processing results. 6. The speech encoding apparatus according to claim 5, wherein said memory is a dual-port memory that can be accessed in parallel by said encoding processing means and said product-sum operation processing means. Encoding processing means for performing an encoding process other than the product-sum operation process in the audio signal encoding process; and product-sum operation processing means for performing the product-sum operation process; An encoding method in a speech encoding device that performs processing,
A speech encoding method, wherein the encoding processing means performs the encoding processing of another channel while the product-sum operation processing means is performing the product-sum operation processing of one channel. 8. A speech encoding apparatus according to claim 7, wherein said product-sum operation processing means performs product-sum operation processing of another channel while said encoding processing means is executing encoding processing of one channel. Method. In the encoding processing means, when the product-sum operation processing becomes necessary during the encoding processing of a certain channel, information necessary for the product-sum operation processing is instructed to the product-sum operation processing means, and the product A step of instructing the execution of a sum operation, and a step of shifting to an encoding process of another channel after that,
9. The speech encoding method according to claim 7, wherein said product-sum operation processing means includes a step of performing a product-sum operation for the certain channel using the information in response to the execution instruction. The product-sum operation processing means includes a step of, in response to the end of the product-sum operation processing, outputting an interrupt signal indicating the end to the encoding processing means,
10. The speech encoding apparatus according to claim 9, wherein said encoding processing means has a step of restarting the encoding processing of the certain channel using a result of the product-sum operation processing in response to the interrupt signal. Method.

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