JP3560166B2 - Semiconductor storage device - Google Patents

Description

[0001]
[Industrial applications]
It is an object of the present invention to detect whether or not discharge by a matching circuit provided for each memory cell constituting a memory matrix for storing data having a bit length N and the number of words M is performed on a precharged match line. The present invention relates to a semiconductor memory device which obtains a collation result between search word data of a bit pattern input to a bit line and storage word data of a bit pattern stored in a word row of a memory matrix. Semiconductor memory device that can reduce the load on the power supply line due to the large current and reduce the power supply noise intensity by reducing power consumption at the time of operation and reducing the peak maximum current flowing through the power supply line. About.
[0002]
[Prior art]
2. Description of the Related Art In recent years, digital circuit technology has been used in various fields due to advances in various design techniques such as improvement in the degree of integration and design of a logic circuit to be incorporated. In such digital circuit technology, not only those that perform calculations and data processing of a CPU (central processing unit) and the like, but also semiconductor storage devices such as a RAM (random access memory) and external storage devices such as a hard disk device, For example, dramatic progress has been made in terms of the degree of integration and the like, and it has come to be used in various fields.
[0003]
For example, in data processing in a database, various signal processing and image processing, a large amount of data is often handled during the processing, and the number of accesses to the data being processed tends to increase. For example, in data processing in a database, data search is frequently performed on data stored in a semiconductor storage device. Therefore, in a digital processing device that performs such processing, the configuration and performance of the storage device used and the method of using the storage device greatly affect the performance of the entire digital processing device.
[0004]
For this reason, a semiconductor memory device itself provided with a data search function, which is frequently performed in data processing in a database, has been widely used in recent years. This semiconductor memory device detects whether or not discharge by a matching circuit provided for each memory cell constituting a memory matrix for storing data of a bit length N and the number of words M is performed on a precharged match line. Thus, a collation result between the search word data of the bit pattern input to the bit line and the storage word data of the bit pattern stored in the word row of the memory matrix is obtained. Hereinafter, such a semiconductor memory device is referred to as a semiconductor memory device with a search function.
[0005]
FIG. 12 is a circuit diagram of a memory matrix of the conventional semiconductor memory device with a search function.
[0006]
The memory matrix of the semiconductor memory device with a search function shown in FIG. 12 stores data of bit length N and word number M. Therefore, a total of (M × N) memory cells M11 to MMN that store 1-bit bit data are used. Each of the memory cells M11 to MMN inputs or outputs a bit line pair Bn and (Bn bar), a word line Wm, a search enable line ENm, and a match line MCHm.
[0007]
As shown, the memory cells M11 to MMN are arranged in a matrix as shown in the figure, and a total of N identical word rows have the word line Wm, the search enable line ENm, and the match line MCHm. It is common. The bit line pairs Bn and (Bn bar) are common to those having a total of M identical bit strings.
[0008]
FIG. 13 is a circuit diagram of a memory cell used in the conventional semiconductor memory device having a search function.
[0009]
The memory cell shown in FIG. 13 is one of the memory cells M11 to MMN used in the semiconductor memory device with a search function shown in FIG. 12 (hereinafter, referred to as memory cell M). The memory cell M includes a total of two inverter gates I1 and I2 and a total of six N-channel MOS transistors T1 to T6.
[0010]
First, one output of the inverter gates I1 and I2 is connected to the other output, and bit data is held. The gates of the N-channel MOS transistors T1 and T2 are connected to the word line Wm. Each gate of the N-channel MOS transistors T4 and T6 is connected to the search enable line ENm. The gate of the N-channel MOS transistor T3 is connected to the input side of the inverter gate I1. The gate of the N-channel MOS transistor T5 is connected to the output of the inverter gate I1.
[0011]
In such a memory cell M, first, when writing bit data, the word line Wm is set to the H state. Thus, the N-channel MOS transistors T1 and T2 are both turned on. At the same time, by inputting bit data to be written from the bit line pair Bn and (Bn bar), the bit data can be held by the inverter gates I1 and I2.
[0012]
In reading out the bit data held in the memory cell M, the word line Wm is set to the H state. As a result, the N-channel MOS transistors T1 and T2 are both turned on, and the retained bit data can be read from the bit line pair Bn and (Bn bar).
[0013]
Note that, with respect to the inverter gates I1 and I2 of the memory cell as shown in FIG. 13, the bit line Bn side, that is, the input of the inverter gate I1 is held in the H state, and the bit line (Bn bar) Side, that is, when the output of the inverter gate I1 is held in the L state, such a state is hereinafter referred to as "Memory cell MHold the H state ("1"). "on the other handFor these inverter gates I1 and I2, when the bit line Bn side is held in the L state and the bit line (Bn bar) side is held in the H state, such a state is referred to as "Memory cell ML state (“0”) is held ”.
[0014]
Regarding the bit line pair Bn and (Bn bar), the state in which the bit line Bn is in the H state and the bit line (Bn bar) is in the L state is hereinafter referred to as “the bit line pair Bn and (Bn bar)”. (Bn bar) is in the H state. "on the other handWhen the bit line Bn is in the L state and the bit line (Bn bar) is in the H state with respect to the bit line pair Bn and (Bn bar), such a state is hereinafter referred to as “the bit line pair Bn and (Bn bar)”. (Bn bar) is in the L state ”.
[0015]
In FIG. 13, search of bit data in such a memory cell M, that is,Memory cell MThe bit data held by the bit line pair Bn and the bit data input from the bit line pair (Bn bar) are collated as follows.
[0016]
That is, in the collation, first, the word line Wm and the search enable line ENm are kept in the L state, and the match line MCHm is precharged to the H state. In this precharge, after the match line MCHm is connected to a power supply line, the match line MCHm is brought into a floating state. By such precharge, the logic state of the match line MCHm is maintained at the H state by the electric charge accumulated in the match line MCHm.
[0017]
In contrast to the precharge, bit data to be collated is input to the bit line pair Bn and (Bn bar). When such bit data is input, the word line Wm remains in the L state and the search enable line ENm also remains in the L state.Memory cell M, Or the precharged match line MCHm.
[0018]
After completing the precharge and inputting bit data to the bit line pair Bn and (Bn bar), the search enable line ENm is set to the H state. By setting the search enable line ENm to the H state, both the N-channel MOS transistors T4 and T6 are turned on. One of the N-channel MOS transistors T3 and T5 isMemory cell MIs turned on in accordance with the bit data held in. That is,In memory cell MWhen the bit data in the H state (“1”) is held, the N-channel MOS transistor T3 is turned on. on the other hand,In memory cell MWhen the bit data in the L state (“0”) is held, the N-channel MOS transistor T5 is turned on.
[0019]
Therefore, when the search enable line ENm is brought to the H state in this manner,In memory cell MWhen the held bit data matches the bit data input at the bit line pair Bn and (Bn bar), the match line MCHmIsIt remains in the H state.
[0020]
For example,Memory cell MAnd the H state (“1”) is held in the bit line pair Bn and (Bn bar), when the H state is input, the N-channel MOS transistors T3 and T4 are both turned on, and the match line Since MCHm is connected to the bit line Bn in the H state, the match line MCHm remains in the H state. on the other hand,Memory cell M, The L-state ("0") is held in the bit line pair, and when the L-state is input from the bit line pair Bn and (Bn bar), both the N-channel MOS transistors T5 and T6 are turned on. And the match line MCHm is connected to the bit line (Bn bar) in the H state, and the match line MCHm remains in the H state.
[0021]
on the other hand,In memory cell MWhen the held bit data and the bit data input from the bit line pair Bn and (Bn bar) do not match, the match line MCHm is discharged to be in the L state.
[0022]
For example,Memory cell MWhen the H state is input from the bit line pair Bn and (Bn bar), the N-channel MOS transistors T5 and T6 are both turned on, and the match line MCHm is Connected to the bit line (Bn bar) in the L state, the match line MCHm is discharged to the L state. or,Memory cell MWhen the L state is input to the bit line pair Bn and (Bn bar), both the N-channel MOS transistors T3 and T4 are turned on, and the match line MCHm is Connected to the bit line Bn in the L state, the match line MCHm is discharged to the L state.
[0023]
According to the semiconductor memory device with a search function as described above, a large number of checks between the search word data of the bit pattern input to the bit line and the storage word data of the bit pattern stored in the word row of the memory matrix are performed. Can be matched in parallel.
[0024]
For example, in the semiconductor memory device with a search function shown in FIG. 12, search word data is input to bit line pairs (B1- (B1 bar)) to (Bn- (Bn bar)).AndBy setting all the search enable lines EN1 to ENM to the H state at the same time, the word data stored in all of the M total words can be collated simultaneously with the input search word data. . The result of this comparison can be obtained from the match lines MCH1 to MCHm.
[0025]
[Problems to be solved by the invention]
However, in the above-described conventional semiconductor memory device with a search function, since the match lines of the word rows whose matching with the input search word data do not match are discharged at the same time, such a discharge is required. The current was concentrated on the power line at one time. For this reason, a large current flows almost instantaneously through the power supply line.
[0026]
If the current flowing through the power supply line is concentrated at one time in this way, a large current will burden the power supply line. For example, the power supply line may generate heat due to Joule heat due to the large current and may be damaged such as disconnection. Further, in order to prevent such damage, conventionally, the cross-sectional area of the power supply line has been increased. However, if the power supply line is made thicker, the integration degree of the semiconductor memory device is reduced. There is a problem. Further, when the current is concentrated on the power supply line at one time as described above, there is a problem that the intensity of power supply noise increases.
[0027]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and it is intended to reduce power consumption during a search operation in a semiconductor memory device having a search function and to further reduce a peak maximum current flowing through a power supply line. It is another object of the present invention to provide a semiconductor memory device capable of reducing a load on a power supply line due to a large current and reducing the intensity of power supply noise.
[0028]
[Means for achieving the object]
It is an object of the present invention to detect whether or not discharge by a matching circuit provided for each memory cell constituting a memory matrix for storing data having a bit length N and the number of words M is performed on a precharged match line. In a semiconductor memory device configured to obtain a comparison result between search word data of a bit pattern input to a bit line and storage word data of a bit pattern stored in a word row of a memory matrix, a bit is set for each bit string. A memory in which a plurality of divided memory matrix blocks each of which is provided with a line and includes a total of P memory cells each having a matching circuit are arranged in the bit string direction so that data having a bit length N and the number of words M is stored. A divided memory matrix block for inputting a matrix and a search enable signal; At least a total of (M × (P−1) +1) search enable lines independent of each memory block and independent of each word row of the memory matrix; Words for which the matching result during the search does not match are independent for each of the divided memory matrix blocks and are independent for each of the word rows of the memory matrix, which are discharged by the matching circuit of the mismatching memory cells. And at least a total of (M × P) match lines transmitting a matching match auxiliary signal corresponding to a precharge state, and a p-th divided memory matrix block to which the search enable signal is input. the search enable signal transmitted on the search enable line corresponding to the m-th word; A matching match signal obtained by delaying a signal obtained by ANDing the two signals with the matching matching auxiliary signal output from the match line is referred to as a (p + 1) th search enable signal. This object has been achieved by providing a search enable timing circuit for inputting the search enable signal to the m-th word of the divided memory matrix block input by the detection enable line.
[0029]
Further, in the semiconductor memory device, the search enable timing circuit is cascaded, and the second to Pth search enable signals are sequentially generated from the connection point and the final stage output. (P-1) total block-by-block delay circuits from which the second enable timing signal to the P-th enable timing signal used for the timing control are derived, and the p-th divided memory to which the search enable signal is input The search enable signal transmitted on the search enable line corresponding to the m-th word of the matrix block, the collation match auxiliary signal output from the match line corresponding to the word, and a cascade connection The p-th connection point of the block-by-block delay circuit or the p-th connection point derived from the output of the last stage+1From the logical product of these three signals with the enable timing signal, the (p + 1) th search enable signal is searched for to the mth word of the divided memory matrix block to which the search enable line is input. The above object is achieved by providing a search enable signal generation circuit that generates a collation match signal that is input as an enable signal.
[0030]
Further, in the semiconductor memory device, for the m-th word of the divided memory matrix block to which the search enable signal is input first, the search enable signal generation circuit generates the match corresponding to the word. The matching match auxiliary signal output from the line and a first connection point of the cascaded block-by-block delay circuits.SecondBy generating the collation coincidence signal from the logical product of these two signals with an enable timing signal, the above-described object is achieved and the number of elements used is reduced.
[0031]
Further, in the semiconductor memory device, the search enable timing circuit is transmitted by the search enable line corresponding to the m-th word of the divided memory matrix block to which the p-th search enable signal is input. The word-by-word delay circuit inputs the search enable signal, and outputs an enable delay signal obtained by delaying the search enable signal, the enable delay signal output by the word-by-word delay circuit, and the enable delay signal. From the logical product of these two signals with the matching match auxiliary signal corresponding to the word, the (p + 1) th search enable signal is sent to the m-th word to which the search enable line is input. And a search enable signal generator for inputting the search enable signal and generating a collation match signal. By providing a circuit, in which to achieve the above objects.
[0032]
[Action]
The memory matrix used in the semiconductor memory device with a search function according to the present invention includes a plurality of divided memory matrix blocks each having a bit line provided for each bit string and a total of P blocks each including a memory cell having a matching circuit. By arranging in the bit string direction, data having a bit length N and the number of words M is stored. Therefore, it can be said that the memory matrix of the present invention is divided into P blocks in the bit string direction, for example.
[0033]
For example, in the case of a memory matrix having a bit length of 64 bits and a word number of 128 words, for example, as in the embodiment described later,4The divided memory matrix blocks having a block length of 16 bits and a word count of 128 words may be arranged in the bit string direction and used. Alternatively, further subdivide and add8The divided memory matrix blocks each having a block length of 8 bits and a word count of 128 words may be arranged in the bit string direction and used for the memory matrix.
[0034]
In the present invention, the memory matrix is divided into a total of P blocks as described above, and the comparison between the search word data and the storage word data performed in each of the divided memory matrix blocks is performed between the divided memory matrix blocks. I'm staggering.
[0035]
This is performed by inputting search enable signals whose timings are shifted from each other to independent search enable lines provided for each of the divided memory matrix blocks. The search enable signals whose timings are mutually shifted in this way can be generated by a search enable timing circuit, for example, using a delay circuit or the like as in an embodiment described later.
[0036]
As described above, in the present invention, the memory matrix to be used is divided into the plurality of divided memory matrix blocks, and the divided memory matrix blocks are sequentially searched, so that the current due to the discharge due to the mismatch of the collation during the search is dispersed, The peak maximum current flowing through the power supply line during the search operation is reduced. For example, when the memory matrix is divided into a total of two divided memory matrix blocks, the peak maximum current can be almost halved. By reducing the peak maximum current in this way, for example, power supply noise radiated from the power supply line is also reduced. Further, for example, when the peak maximum current is halved, the thickness of the power supply line to be used can be halved, for example, and the degree of integration of the semiconductor memory device can be improved.
[0037]
Furthermore, in the present invention, when sequentially searching for each of the divided memory matrix blocks into which the memory matrix is divided as described above, for a word row that does not match in the collation in the preceding divided memory matrix block, The matching is not performed on the corresponding word row of the divided memory matrix block searched thereafter.
[0038]
This is because, for a word row that has already failed to match in the preceding divided memory matrix block, even if the collation matches in the divided memory matrix block that is subsequently collated, the word row does not match. This is because it is determined that there is no match.
[0039]
In addition, for the word row that does not match in the matching in the divided memory matrix block searched in the preceding stage, the matching in the subsequent divided memory matrix blocks is not performed, so that unnecessary matching is performed. It is possible to prevent the power supply current from flowing due to the discharge due to mismatch. Accordingly, in the present invention, not only the peak current flowing in the power supply current at the time of the search operation can be dispersed by sequentially searching for each of the divided memory matrix blocks, but also at the time of matching in the subsequent divided memory matrix block, Since the collation is not performed on the word line that has become, it is possible to further reduce the current consumption.
[0040]
As described above, based on the comparison result in the divided memory matrix block in the preceding stage, whether or not to perform the comparison in each word row in the divided memory matrix block in the next stage is determined for each word row in the preceding stage. The collation result, that is, the collation matching auxiliary signal for each word row of the preceding stage is input to the search enable timing circuit, and the search enable signal of the next stage is generated in accordance with the input collation matching auxiliary signal of the preceding stage. By doing so.
[0041]
Note that the search enable timing circuit includes some signal delay circuit because it is necessary to sequentially search each divided memory matrix block. However, the present invention does not specifically limit the search enable timing circuit such as the signal delay circuit.
[0042]
For example, the delay circuit used in the enable timing circuit may be a block-by-block delay circuit provided for each of the divided memory matrix blocks as in a first embodiment described later. Alternatively, as in a second embodiment described later, a word-by-word delay circuit may be provided for each divided memory matrix block or for each word of each divided memory matrix block.
[0043]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0044]
FIG. 1 is a circuit diagram of a main part of an embodiment of a semiconductor memory device with a search function to which the present invention is applied.
[0045]
The semiconductor memory device shown in FIG. 1 has a bit length of 64 bits, a word number of 128 words, and a memory matrix including a total of (64 × 128 = 8192) memory cells corresponding to the word length. Is provided. The memory matrix is composed of a total of four blocks of the divided memory matrix block. That is, it is composed of the first to fourth divided memory matrix blocks.
[0046]
Each of the four divided memory matrix blocks has a bit length of 16 bits and a word count of 128 words. The memory matrix is composed of a total of 512 word memories MW1a to MW128a, MW1b to MW128b, MW1c to MW128c, and MW1d to MW128d. That is, the first divided memory matrix block includes the word memories MW1a to MW128a. The second divided memory multi-tox block includes the word memories MW1b to MW128b. The third divided memory matrix block includes the word memories MW1c to MW128c. The fourth divided memory multi-tox block includes the word memories MW1d to MW128d.
[0047]
Each of the word memories MW1a to MW128a, MW1b to MW128b, MW1c to MW128c, and MW1d to MW128d is configured by using a total of 16 memory cells M each having the above-described matching circuit shown in FIG. Have been. Therefore, each of the first to fourth divided memory matrix blocks has a configuration like the memory matrix shown in FIG. 12, and the bit length N in FIG. Is 128 words.
[0048]
In the first to fourth divided memory matrix blocks, the word lines W1 to W128 are connected to each other and are common. All of the search enable lines EN1 to EN128 of the first divided memory matrix block are connected to each other, and receive a search enable signal ENa. The search enable signal ENa is the same as the enable timing signal SEa.
[0049]
The matching match auxiliary signals MCH1a to MCH128a output from the match lines MCH1 to MCH128 of each of the word memories MW1a to MW128a of the first divided memory matrix block are supplied to one input of each of AND logic gates G1a to G128a. Is entered. An enable timing signal SEb is input to the other input of each of the AND logic gates.
[0050]
The outputs of these AND logic gates G1a to G128a are, ThatThe search enable signals EN1b to EN128b are input to the search enable lines EN1 to EN128 of the word memories MW1b to MW128b of the second divided memory matrix block, respectively. Each of the search enable signals EN1b to EN128b is also input to one input of each of the AND logic gates G1b to G128b.
[0051]
In the second divided memory matrix block, the matching match auxiliary signals MCH1b to MCH128b output from the respective match lines MCH1 to MCH128 of the respective word memories MW1b to MW128b respectively correspond to the AND logic gates G1b to G128b, respectively. To one input. An enable timing signal SEc is input to one input of each of the AND logic gates G1b to G128b.
[0052]
The search enable signals EN1c to EN128c output from the AND logic gates G1b to G128b are input to the search enable lines EN1 to EN128 of the word memories MW1c to MW128c of the third divided memory matrix block. These search enable signals EN1c to EN128c are also input to one input of AND logic gates G1c to G128c, respectively.
[0053]
In the third divided memory matrix block, the matching match auxiliary signals MCH1c to MCH128c output from the match lines MCH1 to MCH128 of the respective word memories MW1c to MW128c are connected to one of the AND logic gates G1c to G128c. Input has been entered. One input of these AND logic gates G1c to G128c also receives the enable timing signal SEd.
[0054]
The search enable signals EN1d to EN128d output from the AND logic gates G1c to G128c are respectively sent to the search enable lines EN1 to EN128 of the word memories MW1d to MW128d of the fourth divided memory matrix block., EnterIt is empowered. Also, these search enable signals EN1 dTo EN128d are also input to respective one inputs of the AND logic gates G1d to G128d.
[0055]
In the fourth divided memory matrix block, the matching match auxiliary signals MCH1d to MCH128d output from the respective match lines MCH1 to MCH128 of the respective word memories MW1d to MW128d are each one of the AND logic gates G1d to G128d. Input has been entered.
[0056]
Each of these AND logic gates G1d to G128d is a final collation result of the semiconductor memory device with a search function of the first embodiment, that is, a collation match signal.No. MC1 to MC128 are output.
[0057]
In this embodiment, the search is started in accordance with the input enable timing signal SEa. The enable timing signal SEa is supplied to a delay circuit for each block.DEntered in a.
[0058]
The block-by-block delay circuitDa delays the enable timing signal SEa by a predetermined time and outputs it as an enable timing signal SEb. The enable timing signal SEb is input to one input of each of the AND logic gates G1a to G128a, and is also input to the block-by-block delay circuit Db.
[0059]
The block-by-block delay circuit Db delays the input enable timing signal SEb by a predetermined time and outputs the result as the enable timing signal SEc. The enable timing signal SEc is input to one input of each of the AND logic gates G1b to G128b, and is also input to the block-by-block delay circuit Dc.
[0060]
The block-by-block delay circuit Dc delays the input enable timing signal SEc by a predetermined time and outputs it as the enable timing signal SEd.
[0061]
In addition, the block-by-block delay circuitDa ~Dc (Hereafter, block-by-block delay circuitDx), as shown in FIG.bufferIt is constituted by a gate B. That is, the block-by-block delay circuitDx obtains a predetermined delay time by a signal delay when a signal is transmitted through these cascade-connected buffer gates B. The block-by-block delay circuitDThe enable timing signal SE (x + 1) output by x is obtained by delaying the input enable timing signal SEx by such a predetermined delay time.
[0062]
In the first embodiment, the search enable timing circuit of the present invention mainly includes the block-by-block delay circuits Da to Dc and the AND logic gates G1a to G128a, G1b to G128b, and G1c to G128c.,G1d to G128d,as well as,theseConnectIt is composed of wiring.
[0063]
FIG. 3 is a time chart showing the operation of the first embodiment.
[0064]
The time chart of FIG. 3 shows the enable timing signals SEa to SEb, the search enable signals ENma to ENmd, the collation match auxiliary signals MCHma to MCHmd, and the collation match signal MCm. Note that, in the code names of these signals, "m" indicates that the signal is of the m-th word row.
[0065]
In this time chart, the m-th word row shows a case where the storage word data of the bit pattern stored in the word row matches the search word data of the bit pattern input to the bit line. ing. Hereinafter, the operation of the present embodiment will be described based on this time chart and according to the elapsed time.
[0066]
First, when the enable timing signal SEa rises, all the word memories MW1a to MW128a of the first divided memory matrix block are searched. That is, a search is also performed in the word memory MWma to which the search enable signal ENma shown in this time chart, which is the same as the enable timing signal SEa, is input.
[0067]
On the other hand, the rise of the enable timing signal SEa is delayed by the block-by-block delay circuit Da, and the enable timing signal SEb rises after a predetermined time. When the enable timing signal SEb rises, the collation in the word memory MWma is completed, and the collation matching auxiliary signal MCHma according to the collation is determined.
[0068]
The AND logic gate Gma receives the collation matching auxiliary signal MCHma and the enable timing signal SEb, and outputs a logical product of these signals as the search enable signal ENmb. If the collation matching auxiliary signal MCHma is in the H state, that is, if the collation result in the word memory MWma is a collation match, the search enable signal output by the AND logic gate Gma when the enable timing signal SEb rises. Signal ENmb rises.
[0069]
When the search enable signal ENmb rises, a search in the word memory MWmb of the second divided memory matrix block is performed. The search in each of the word memories MW1b to MW128b of the second divided memory matrix block is performed only for the word whose collation result in the word memories MW1a to MW128a of the first divided memory matrix block matches. .
[0070]
In the word memory MWmb of the second divided memory matrix block, when the search enable signal ENmb rises and the search is performed, after a predetermined time,AndBefore the rise of the enable timing signal SEc, the matching match auxiliary signal MCHmbIs determined. When the matching timing signal SEc rises while the matching match auxiliary signal MCHmb is in the H state in the case of the matching match, the search enable signal ENmc output by the AND logic gate Gmb also rises.
[0071]
When the search enable signal ENmc rises, a search in the word memory MWmc of the third divided memory matrix block is also performed. If the search result is a collation match, the search is performed according to the rise of the enable timing signal ENmd. The search of the fourth divided memory matrix block in the word memory MWmd is also performed. The final search result of the word row m 1 is output from the AND logic gate Gmd as a collation match signal MCm.
[0072]
FIG. 4 is a time chart showing the operation at the time of non-matching in this embodiment.
[0073]
In FIG. 4, in a certain word row m 2 of a certain divided memory matrix block x (x is any of a to d), the matching result in the word memory MWmx (m is the word row of the word) is compared. A time chart at the time of a mismatch is shown.
[0074]
In this time chart, when the search enable signal ENmx input to the word memory MWmx rises, the word memoryMW mxIs searched for. If the search result is a mismatch, the matching match auxiliary signal MCHmx output from the word memory MWmx after a predetermined time is discharged and goes to the L state.
[0075]
When the matching match auxiliary signal MCHmx goes to the L state, the search output from the AND logic gate Gmx which receives the matching match auxiliary signal MCHmx, the search enable signal EMmx, and the enable timing signal SE (x + 1) is output. The enable signal ENm (x + 1) also remains in the L state. Therefore, the collation matching auxiliary signal MCHm (x + 1) output from the word memory MWm (x + 1) at the next stage of the word memory MWmx is not discharged.
[0076]
FIG. 5 is a time chart when a collation mismatch occurs in a certain word row of the fourth divided memory matrix block in the last block of the first embodiment.
[0077]
In the time chart of FIG. 5, a search is performed in the word memory MWmd of the m-th word row of the fourth divided memory matrix block, and the search result indicates that the collation does not match. is there.
[0078]
In the word memory MWmd, the input search enable signal ENmd becomes the H state and the search is started. If the search does not match, the matching match auxiliary signal MCHmd output from the word memory MWmd is discharged after a predetermined time. To be in the L state. When the matching match auxiliary signal MCHmd goes to the L state, the matching match signal MCm output from the AND logic gate Gmd also goes to the L state. Therefore, by determining the logic state of the collation match signal MCm at a timing after a predetermined time from the rise of the search enable signal ENmd, such collation mismatch can be confirmed.
[0079]
In this embodiment, the AND logic gates G1b to G128b and G1c to G128c are three-input AND logic gates because the search operation is performed in the corresponding word memory (that is, the preceding stage in the word memory). This is to detect that the search result of the word memory is a match and that the corresponding enable timing signal SEx rises.
[0080]
In comparison, the AND logic gates G1a to G128a are two-input AND logic gates. This is because the search operation is always performed for all the word memories MW1a to MW128a of the first divided memory matrix block because the first divided memory matrix block is the first stage.That is, MW1a to MW128a are searched by the AND logic gates G1a to G128a, for example, by the logical product with the enable timing signal used as a search enable signal in the first memory matrix block. This is because it is not necessary to determine whether As described above, in the present embodiment, the number of required elements can be reduced by using the AND logic gates G1a to G128a, which may be three-input AND logic gates, as two-input AND logic gates.
[0081]
On the other hand, the AND logic gates G1d to G128d are also two-input AND logic gates. this is,The search enable signal EN1 c ~ EN128 c And the collation matching auxiliary signal MCH1 d ~ MCH128 d And only the logical AND operation ofFor good.
[0082]
As described above, according to the first embodiment, the peak current flowing through the power supply line during the search operation can be reduced by shifting the timing of the search operation in the first to fourth divided memory matrix blocks. Can be dispersed. In particular, in the present embodiment, in the word memory in which the collation does not match, the collation in the subsequent word memory is not performed. As a result, it is possible to reduce the flow of the power supply current due to the discharge of the match line performed when the matching is not performed during the search in the word memory, and the power consumption is reduced.
[0083]
FIG. 6 is a circuit diagram of a main part of a second embodiment of the semiconductor memory device with a search function to which the present invention is applied.
[0084]
In FIG. 6, the semiconductor memory device has a bit length of 64 bits and a word number of 128 words, as in the first embodiment, and a total (64 × 128 = 8192) corresponding to this. Of memory cells. The memory matrix is composed of a first divided memory matrix block to a fourth divided memory matrix block of a total of four blocks.
[0085]
BookAlso in the second embodiment, each of the four divided memory matrix blocks has a bit length of 16 bits and a word count of 128 words. The configuration of the first divided memory matrix block to the fourth divided memory matrix block of the second embodiment is the same as that of the first embodiment. Also, these divided memory matrix blocksIs,RespectivelyFIG.It is a configuration like a memory matrix shown inFIG.Is configured using a memory cell M shown in FIG. The word lines W1 to W128 of the first to fourth divided memory matrix blocks are connected to each other and are common.
[0086]
In the second embodiment, the search enable lines EN1 to EN128 of the first divided memory matrix block are connected to each other, and a search enable signal EN is input. The search enable signal EN is input to one input of each of the AND logic gates H1a to H128a via the word-by-word delay circuits D1a to D128a, respectively.
[0087]
The matching match auxiliary signals MCH1a to MCH128a output from the match lines MCH1 to MCH128 of the word memories MW1a to MW128a are input to one input of the AND logic gates H1a to H128a, respectively. The AND logic gates H1a to H128a calculate the logical product of the enable delay signals END1a to END128a output from the word-by-word delay circuits D1a to D128a and the collation matching auxiliary signals MCH1a to MCH128a, respectively. EN1b to EN128b are output to the word memories MW1b to MW128b, respectively.
[0088]
The following second divided memory matrix block to fourth divided memory matrix block also use the respective word-by-word delay circuits D1b to D128b and D1c to D128c, and AND logic gates H1b to H128b and H1c to H128c. An operation similar to that of the one-divided memory matrix block is performed. On the output side of the fourth divided memory matrix block, the word-by-word delay circuit as described above is not particularly provided, and the search enable signals EN1d to EN128d input to the word memories MW1d to MW128d, respectively, The logical product of each of the collation matching auxiliary signals MCH1d to MCH128d output from each of the word memories MW1d is obtained by the AND logic gates H1d to H128d, and the collation matching signals MC1 to MC128 are output as the overall search result Have been.
[0089]
FIG. 7 is a circuit diagram focusing on one of the word memories used in the second embodiment.
[0090]
As shown in FIG. 7, the search enable line ENm of any one of the word memories MWmx (x is any of a to c) of the second embodiment.ToIs input with the search enable signal ENmx. Further, one delay circuit Dmx for each word is provided for one word memory MWmx, and the search enable signal ENmx is inputted. The word-by-word delay circuit Dmx receives the search enable signal EN.mxAs a signal delayed by a predetermined time, the enable delay signal ENDmxIs output.
[0091]
On the other hand, the word memory MWmx outputs the collation matching auxiliary signal MCHmx from the match line MCHm.
[0092]
Also, one AND logic gate H is provided for one word memory MWmx.mxIs provided. The AND logic gate Hmx finds the logical product of the enable delay signal ENDmx and the matching match auxiliary signal MCHmx, and outputs the result as a search enable signal ENm (x + 1). The search enable signal ENm (x + 1) is input to the search enable line ENm of the next-stage word memory MWm (x + 1) of the same word row.
[0093]
FIG. 8 is a circuit diagram of the word-by-word delay circuit of the second embodiment.
[0094]
As shown in FIG. 8, the word-by-word delay circuits D1a to D128a, D1b to D128b and D1c to D128c (hereinafter collectively referred to as Dmx) are composed of a total of six buffer gates B. That is, the word-by-word delay circuit Dmx is connected to these cascade-connected buffer gates B.By, And generates and outputs the enable delay signal ENDmx obtained by delaying the search enable signal ENmx by a predetermined time.
[0095]
In the second embodiment, the search enable timing circuit of the present invention mainly includes the word-by-word delay circuits D1a to D128a, D1b to D128b and D1c to D128c, and the AND logic gates H1a to H128a, H1b to D1c. H128b, H1c to H128c,H1d to H128d,as well as,theseConnectIt is composed of wiring.
[0096]
FIG. 9 is a time chart showing the operation of the second embodiment.
[0097]
In the time chart of FIG. 9, the word memory MWmx of the second embodiment and the word memory MWm (x + 1) at the next stage of the word memory are shown. In this time chart, regarding the word memories MWmx and MWm (x + 1), the enable signal ENmx, the collation matching auxiliary signal MCHmx, the enable delay signal ENDmx, and the enable signal ENm (x + 1) It is shown.
[0098]
In the time chart of FIG. 9, when the enable signal ENmx rises first, a collation circuit or the like included in each of the 16 memory cells Mm1 to Mm in the word memory MWmx operates, and the word memory MWmx Such a search operation is performed. The search result is output as the collation match auxiliary signal MCHmx indicating collation match or collation mismatch. In this time chart, the matching match is indicated by a one-dot chain line, and the mismatching is indicated by a broken line.
[0099]
On the other hand, the enable signal ENmx is delayed by a predetermined time in the word-by-word delay circuit Dmx, and is output as an enable delay signal ENDmx. The delay time corresponds to the time until the search operation performed in the word memory MWmx is completed, and is slightly longer than the time required for the search operation. Therefore, at the rise of the enable delay signal ENDmx, it is determined whether the collation matching auxiliary signal MCHmx is collation coincidence or collation non-coincidence. Based on this, the enable signal ENm (x + 1) is determined. It is generated by an AND logic gate Hmx.
[0100]
As described above, in the second embodiment, similarly to the first embodiment, the search is performed by shifting the timing of the search operation performed in each of the first to fourth memory matrix blocks. The peak current flowing through the power supply line during operation can be dispersed. Also in the second embodiment, whether or not a search is performed in each word row after the second divided memory matrix block is performed based on the search result at the preceding stage. Therefore, if the collation does not match in the preceding word memory, the search for the corresponding word row in the next stage is not performed in the word memory, so that the overall power consumption can be reduced.
[0101]
When the first embodiment is compared with the second embodiment, a portion of the delay circuit, that is, a portion of the block-by-block delay circuit Dx in the first embodiment, and a portion of the delay circuit Dx in the second embodiment. The part of the delay circuit Dmx and the part of the logic gate Gmx of the first embodiment and the second embodiment and the circuits in the vicinity thereof are partially different. For example, in the first embodiment, delay circuits for a small number of blocks are concentratedly provided as the block-by-block delay circuits Dx, which is excellent in this point. On the other hand, in the second embodiment, since the word-by-word delay circuit Dmx is arranged near each word memory MWmx, the wiring related to the word-by-word delay circuit Dmx is shortened, which is excellent in this point. These first and second embodiments may be selectively determined according to the state of the circuit to be provided.
[0102]
FIG. 10 is a graph of a power supply current at the time of a search operation in a conventional semiconductor memory device with a search function. On the other hand, FIG. 11 is a graph showing the power supply current at the time of the search operation in the first embodiment and the second embodiment.
[0103]
First, conventionally, as shown in FIG. 10, the power supply current at the time of the search operation is time t.₁Is focused on On the other hand, in the first embodiment and the second embodiment, as shown in FIG. 11, the peak current at the time of the search operation is dispersed. That is, the time t in FIG.₂~ T₅And the peak maximum current is made smaller than before.
[0104]
In particular, the time t₂Corresponds to a search operation in the first divided memory matrix block, and the time t₃Corresponds to the search operation in the second divided memory matrix block, and the time t₄Corresponds to the search operation in the third divided memory matrix block, and the time t₅Corresponds to the search operation in the fourth divided memory matrix block.
[0105]
As described above, when the search operation at the corresponding front stage of each word memory does not match, the search at the subsequent stage of the word memory is not performed, and the power consumption is reduced. . This point is different from the time t in FIG.₂~ T₅And the peak current is shown to be gradually decreasing with respect to the broken line according to the elapsed time.
[0106]
Thus, as apparent from the comparison between FIGS. 10 and 11, according to the first embodiment or the second embodiment, the peak maximum current flowing through the power supply line at the time of the search operation is smaller than that of the related art. It can be reduced to almost 1/4. Furthermore, in the first and second embodiments, the overall power consumption during the search operation can be reduced to 1/4 or less as compared with the related art.
[0107]
【The invention's effect】
As described above, according to the present invention, the power consumption at the time of the search operation in the semiconductor memory device with the search function is reduced, and the peak maximum current flowing through the power supply line is further reduced, so that the power supply line due to the large current can be supplied. , And the strength of power supply noise can be reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a main part of a first embodiment of a semiconductor memory device with a search function to which the present invention is applied;
FIG. 2 is a circuit diagram of a block-by-block delay circuit used in the first embodiment.
FIG. 3 is a time chart showing the operation of the first embodiment at the time of matching.
FIG. 4 is a time chart showing the operation of the first embodiment at the time of non-matching;
FIG. 5 is a time chart showing the operation of the fourth stage divided memory matrix block at the last stage when there is no match in the first embodiment;
FIG. 6 is a circuit diagram of a main part of a second embodiment of the semiconductor memory device with a search function to which the present invention is applied;
FIG. 7 is a circuit diagram focusing on one word memory of the second embodiment.
FIG. 8 is a circuit diagram of a word-by-word delay circuit used in the second embodiment.
FIG. 9 is a time chart showing the operation of the second embodiment.
FIG. 10 is a graph of a power supply current during a search operation in a conventional semiconductor memory device with a search function.
FIG. 11 is a graph showing a power supply current at the time of a search operation in the first embodiment or the second embodiment.
FIG. 12 is a circuit diagram of a memory matrix of a conventional semiconductor memory device having a search function.
FIG. 13 is a circuit diagram of a memory cell used in the memory matrix of the conventional semiconductor memory device with a search function.
[Explanation of symbols]
MWmx, MW1a to MW128a, MW1b to MW128b, MW1c to MW128c, MW1d to MW128d ... word memory
G1a to G128a, G1b to G128b, G1c to G128c, G1d to G128d, H1a to H128a, H1b to H128b, H1c to H128c, H1d to H128d ... AND logic gate
Da to Dc: delay circuit for each block
D1a to D128a, D1b to D128b, D1c to D128c ... delay circuit for each word
M11 to MMN: Memory cell
T1 to T6: N-channel MOS transistors
I1, I2 ... Inverter gate
B: Buffer gate
Bn (Bn bar), B1 to Bn, (B1 bar) to (Bn bar) ... bit line
Wm, W1 to W128 to Wm (or W1 to WN to W128) ... word line
ENn, EN1 to ENN ... search enable line (or search enable signal)
ENmx: Search enable signal
ENDmx, END1a to END128a, END1b to END128b, END1c to END128c, END1d to END128d ... enable delay signal
SEa to SEd: enable timing signal
MCHm, MCH1 to MCHM ... match line (or collation match holding signal)
MCHma: Matching matching auxiliary signal
MC1 to MC128 ... collation match output (or collation match signal)
t₁~ T₅…Times of Day

Claims (4)

By detecting whether or not the discharge by the matching circuit provided for each memory cell constituting the memory matrix for storing the data of the number of words M with the bit length N is performed on the precharged match line, In a semiconductor memory device that obtains a comparison result between search word data of a bit pattern input to a memory cell and word data of a bit pattern stored in a word row of a memory matrix,
By arranging a plurality of divided memory matrix blocks of a total of P blocks each having a matching circuit provided with a bit line for each bit string and having a matching circuit in the bit string direction, data having a bit length N and the number of words M is stored. And a memory matrix
At least a total of (M × (P−1) +1) search enable lines, each of which is independent of the divided memory matrix block and independent of each word row of the memory matrix, for inputting a search enable signal;
It is precharged before executing the search, and for the word in which the matching result during the search does not match, the word is discharged by the matching circuit of the memory cell that does not match, independently for each of the divided memory matrix blocks, At least a total of (M × P) match lines for transmitting a matching match auxiliary signal corresponding to a precharge state, which is independent for each word row of the memory matrix;
The search enable signal transmitted on the search enable line corresponding to the m-th word of the divided memory matrix block to which the search enable signal is input p-th, and the match line corresponding to the word A matching match signal obtained by delaying a signal obtained by ANDing the two signals with the matching matching auxiliary signal output from the comparator, and (p + 1) th search enable signal having the detection enable line A search enable timing circuit for inputting the search enable signal to the m-th word of the divided memory matrix block input at step (i). 2. The search enable timing circuit according to claim 1, wherein
A second enable timing signal to a P-th enable which are used for timing control at the time of generating the second to P-th search enable signals sequentially from the connection point and the output of the last stage in a cascade connection. A total of (P-1) delay circuits for each block from which a timing signal is derived;
The search enable signal transmitted on the search enable line corresponding to the m-th word of the divided memory matrix block to which the search enable signal is input p-th, and the match line corresponding to the word And the p + 1 enable timing signal derived from the p-th connection point or the output of the last stage of the cascade-connected block-by-block delay circuit. From the product, a (p + 1) th search match signal is generated, which is input as the search enable signal to the m-th word of the divided memory matrix block input through the search enable line, and a matching match signal is generated. And a search enable signal generation circuit. In claim 2,
For the first word of the m-th word of the divided memory matrix block to which the search enable signal is input, the search enable signal generation circuit outputs the matching match output from the match line corresponding to the word. The collation matching signal is generated from a logical product of an auxiliary signal and a second enable timing signal extracted from a first connection point of the cascade-connected block-by-block delay circuit. A semiconductor memory device characterized by the above-mentioned. 2. The search enable timing circuit according to claim 1, wherein
Inputting the search enable signal transmitted on the search enable line corresponding to the m-th word of the divided memory matrix block to which the p-th search enable signal is input, and delaying the search enable signal A word-by-word delay circuit that outputs the enabled enable delay signal;
From the logical product of these two signals of the enable delay signal output by the word-by-word delay circuit and the collation matching auxiliary signal corresponding to the word corresponding to the enable delay signal, the (p + 1) th is A search enable signal generation circuit for generating a match signal, the search enable signal being input as the search enable signal to the m-th word whose search enable signal is input through the search enable line; Storage device.

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