JP3564166B2 - Disk unit - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a disk device for detecting the position of a head by judging the phase of servo information recorded on a disk surface, and more particularly to a disk device for detecting a head position by detecting a zero cross of a servo information reading waveform.
2. Description of the Related Art A magnetic disk device is a storage device that moves a head in a radial direction of a rotating magnetic disk to position it on a target track, reads data on a track of the magnetic disk by a magnetic head, and writes data on the track. In this magnetic disk drive, in order to increase the storage capacity and reduce the size, it is essential to improve the recording density, especially the track density.
[0002]
In addition, a head seek time of about 10 mm is required for higher speed. For this reason, a digital circuit using a high-speed processor is adopted as the head positioning circuit. If this digital servo circuit is used, the position needs to be detected only at the sampling timing, and a position detection circuit for the servo head that is different from the analog servo position detection circuit is required.
[0003]
[Prior art]
In general, the two-phase servo pattern, which has been widely used, has a problem that the frequency band of a position signal demodulation circuit increases as the track density of the magnetic disk increases, and the pattern becomes weak to noise. In the two-phase servo pattern, a peak of a waveform obtained by reading servo information recorded on a servo surface of a magnetic disk is detected, and a position is detected based on a height of the detected peak. However, although the peak height is obtained continuously, there is a problem that the influence of noise and the level fluctuation of the magnetic disk medium surface directly affect the position detection amount.
[0004]
For this reason, a servo pattern is recorded as phase information, and the position is detected based on the phase difference of the servo information. US Pat. No. 4,549,232 and US Pat. No. 4,642,562 (corresponding to Japan) Published patent application No. 10472/1985).
FIG. 89 shows a conventional phase servo pattern. The phase servo pattern divides the servo surface of the magnetic disk into four cylinders of No. 1, No. 1, No. 2, and No. 3, and records servo information having different phases in the circumferential direction of each cylinder. That is, one phase servo pattern is divided into a first field EVEN1, a second field ODD, and a third field EVEN2. Servo patterns of the same phase are recorded in the first and third fields EVEN1 and EVEN2, and patterns of the opposite phase are recorded in the second field ODD so that the position of the moving head can be read at the center position of the second field ODD. ing.
[0005]
FIG. 90 shows the detection of the phase difference in the first and third fields EVEN1 and EVEN2 of FIG. Here, the servo pattern is recorded with four clocks of the reference clock as one cycle, and the position of cylinders 0 to 3 in the four cylinders can be detected as an example.
Assuming that the reference phase of the reference clock is a phase indicated by a thick line in the figure, when the head is at the position 600 which is the center of the second cylinder, the phase difference between the clock reference phase and the read pulse of the phase servo pattern is a phase difference signal. As shown by reference numeral 610, the period becomes 1/2 of the servo pattern period. When the head is at the position 620 which is the center of the first cylinder, the phase difference between the clock reference phase and the read pulse of the servo pattern has a 1/4 cycle like the phase difference signal 630.
[0006]
When the head is at the position 640 which is the center of the third cylinder, the phase difference between the reference phase and the read pulse of the servo pattern has a period of 3/4 like the phase difference signal 650. Further, when the head is at the center of cylinder 0, the phase difference between the clock reference phase and the read pulse of the servo pattern is zero or one cycle.
FIG. 91 shows detection of a phase difference in the second field ODD. For example, when the head is located at the position 660 which is the center of the second cylinder, the phase difference between the clock reference phase and the read pulse of the servo pattern has a half cycle like the phase difference detection signal 670. When the head is located at the position 680 which is the center of the third cylinder, the phase difference between the clock reference phase and the read pulse of the servo pattern is １ ／ period like the phase difference detection signal 690. Therefore, by detecting this phase difference, it is possible to detect which position of the 0th to 3rd cylinders the magnetic head is located.
[0007]
According to the head position detection using this phase servo pattern, the peak of the waveform read from the servo surface is detected, the phase difference from the clock reference phase is detected a plurality of times, and the average phase difference is used as the position signal. Since the phase difference detection is performed a plurality of times, the position signal cannot be obtained continuously, but is not easily affected by noise due to the averaging.
Also, if the level fluctuation of the disk medium surface does not cause fluctuation of peak detection, accurate position detection can be performed. Further, in the digital positioning control of the head, since it is only necessary to obtain position information for each sampling period, continuous information is not required, and position detection using a phase servo pattern is suitable.
[0008]
In the conventional apparatus, a clock source having a fixed phase such as a crystal oscillator is used. Therefore, if there is a rotation fluctuation in the disk, the phase difference from the servo pattern cannot be accurately detected, and the position detection accuracy is reduced. In the crystal oscillator, the oscillation frequency fluctuates depending on the temperature, and therefore, the phase of the clock reference fluctuates, and the phase difference from the servo pattern cannot be accurately detected.
[0009]
Further, in the conventional apparatus, since the position detection processing by calculating the average value after detecting the phase difference is performed by the dedicated processor, if the seek speed is increased, the processing of the processor cannot be performed in time, and it is difficult to perform high-speed seek. Further, in the conventional apparatus, when the head moves in the range of four cylinders from No. 0 to No. 3, the phase difference changes in the range of 0 to 1 cycle (4 clocks). For this reason, the phase difference of the second cylinder at the center has a continuous variation width of four clocks, but the other cylinders 0, 1, and 3 have a small variation width of the phase difference. For this reason, head position detection in corus controlrangeAnd seek control is difficult.
[0010]
In order to solve such a problem, the inventor of the present application has proposed a "servo position detecting device for a disk device" in Japanese Patent Application No. 5-54977 (corresponding to U.S. Patent Application No. 08 / 194,666). In this disk device, a training area in which timing information is recorded is provided before the servo area of the disk, and a PLL circuit which is a clock generation source is phase-synchronized to generate a reference clock synchronized with the disk servo pattern. ing. For this reason, a reference clock having a prescribed phase can be generated irrespective of disk rotation fluctuations and environmental temperature fluctuations, and the phase difference from the servo pattern is accurately detected to improve the head position detection accuracy.
[0011]
The position signal detection processing is converted into a duty pulse whose duty ratio changes in a range of 0 to 100% according to the head position in the first to third fields, and the first to third fields are used by using this duty pulse. In this order, the capacitor is switched to charge, discharge, and charge for integration, and a head position signal is detected as an integrated voltage of the capacitor.
[0012]
Here, the phase servo information is such that the sum of the first and third fields is substantially the same as that of the second field. Therefore, in the on-track state to the target cylinder, the duty ratio of the first to third fields becomes 50%, 50%, 50%, and the integrated voltage becomes zero. By detecting the analog position signal by the integration circuit, the processor only needs to AD-convert and read the integration signal, and the position detection corresponding to the high-speed seek can be performed.
[0013]
Further, by automatically performing so-called cylinder switching for selecting a reference clock corresponding to a target cylinder from a plurality of reference clocks having different phases, even if any of the 0th to 3rd cylinders becomes the target cylinder, the target cylinder is always output. As a center cylinder, a position signal that changes within a range of ± 2 cylinders is obtained, and the coace control and the on-track control are ensured.
[0014]
[Problems to be solved by the invention]
However, in the disk device already proposed, the position signal of the head is created by detecting the peak of the read signal of the phase servo information obtained from the servo head. There is a problem that is easily generated. That is, the peak detection is made by differentiating the read signal obtained from the servo head after level slicing. For this reason, peak detection is performed at an erroneous timing due to noise mixed in the read waveform, and jitter that causes phase fluctuation is likely to occur, resulting in a problem that the positioning accuracy of the head is reduced.
[0015]
In the disk device already proposed, the duty signal obtained from the servo information during the on-track ideally has a duty ratio of 50%, 50%, and 50% in the first to third fields. It does not become 50% due to circuit delay.
For this reason, in the on-track state, the duty ratio becomes, for example, 40%, 40%, 40%, and the duty pulse becomes thin, and the duty ratio becomes 60%, 60%, 60%, and the duty pulse becomes thick.
[0016]
In on-track control, the head is
(Even field)-(odd field) = 0
Therefore, there is no problem in the accuracy of the on-tok even if the duty ratio is always 60% or 40%. However, when the seek operation is performed, the seek can be performed in the range of −50% to + 50% if the on-tok is 50%, whereas the seek can be performed only in the range of −40% to + 60% if the on-track is 40%. There is a problem that the margin for the high-speed seek is reduced.
[0017]
Further, since the analog integration circuit is used, an error occurs between the charge current and the discharge current of the capacitor, and even when the duty ratio is 50%, the integrated voltage does not become zero, which is a factor of deteriorating the position detection accuracy. .
On the other hand, in the phase servo pattern, only the position detection can be performed within a range of four cylinders, for example, two cylinders before and after the target cylinder, so that the head movement defined by the number of moving cylinders per sampling cycle of position detection is performed. The speed must be kept within 4 cylinders, and the seek speed is limited, and there is a problem that high-speed seek cannot be performed.
[0018]
In the case of cores control for detecting a head position for each sampling period, the target speed is set by predicting the next head position from the previous and current head positions. However, since the Koas control is performed in accordance with the target speed pattern of acceleration, constant speed, and deceleration, a simple prediction based on the speed alone results in a large deviation between the predicted position and the actual position, and the position prediction fails. Highly likely to cause seek error.
[0019]
Further, in a disk device using a conventional two-phase servo pattern, servo information is recorded in a specific cylinder on a data surface in order to realize a thermal offset measurement and a yaw angle offset measurement, but a phase servo pattern is used. In this case as well, it is necessary to record a phase servo pattern in a specific cylinder on the data surface.
In this case, in contrast to a servo head that reads servo information on a servo surface, a data head that reads and writes data on a data surface is provided with two types, a write head and a read head. An MR head is used. Therefore, even if the same phase servo pattern as that on the servo surface is recorded on the data surface, there is a problem that a continuous head position signal cannot be obtained from a signal read by a small MR head.
[0020]
In addition, the measurement and correction of the yaw angle offset, the adjustment of the center value for the DA converter provided in the drive system of the voice coil motor (VCM), the rezero operation as the initialization processing accompanying the power-on start, the optimization of the servo system Various problems for ensuring the performance of the disk device, such as automatic adjustment to the state and optimization of the on-track slice value at the time of erasing, must be solved.
[0021]
An object of the present invention is to provide a disk device that can perform position detection using phase servo information that is resistant to noise and jitter.
Another object of the present invention is to provide a disk drive capable of obtaining a duty pulse having a duty ratio of 50% in an on-track state even if there is a circuit delay.
An object of the present invention is to provide a disk device that removes various errors relating to an integration operation and maintains an integration circuit in an optimum state.
[0022]
Another object of the present invention is to provide a disk apparatus capable of performing high-speed seek at a head moving speed exceeding 4 cylinders per sample period.
Another object of the present invention is to provide a disk drive capable of accurately predicting a position accompanying movement of a head.
Another object of the present invention is to provide a disk device for recording a phase servo pattern suitable for a small MR head (read head) provided on a data head on a data surface.
[0023]
Another object of the present invention is to provide a disk device in which data bits 0 and 1 can be read from and written to a specific cylinder in a user area of a data surface by using phase servo information by using a head position detection circuit.
Another object of the present invention is to provide a disk drive capable of measuring and correcting a yaw angle offset of a read head when a data head is positioned by rotating a head arm between an innermost part and an outermost part with a head arm.
[0024]
[Means for Solving the Problems]
FIG. 1A is a diagram illustrating the principle of the present invention.
First, the disk device of the present invention records phase servo information on a servo surface of a disk medium. That is, a plurality of servo frames arranged in the circumferential direction of each cylinder are arranged with four cylinders on the servo surface as one unit. Each servo frame is provided with a training area, a marker area, an index guard band area, and a servo area.
[0025]
As shown in FIG. 1B, the servo area is divided into a first field (EVEN1), a second field (ODD1), a third field (ODD2), and a fourth field (EVEN2).. No.In the first and fourth fields (EVEN1, 2), servo information having a phase change in position is recorded. Servo information having an opposite phase change is recorded in the second and third fields (ODD1,2).
[0026]
Timing information is recorded in a training area ahead of the servo area in the rotation direction, and marker information for determining the servo area is recorded in the marker area. Further, a plurality of sets of index information and card band information are simultaneously recorded in the card band index area. For the index / guard band area, each information is detected by majority decision of the read result of a plurality of sets of index information and card band information.
[0027]
A read pulse is detected by the read pulse detecting means 3 from the read signal of the servo frame read by the servo head means 18. The read pulse detecting means 3 includes, for example, a peak detecting means 100 and a zero-cross detecting means 112. The peak detecting means 100 detects a timing signal in the training area, a marker signal in the marker area, and a peak timing of a read waveform of the index signal and the guard band signal in the index / card band area to generate a read pulse (peak detection pulse). I do.
[0028]
Here, the read pulse detecting means 3 may perform zero-cross detection for all read signals in the training area, marker area, index / card band area, and servo area, or may perform peak detection for all read signals.
The clock generation means 102 generates a reference clock having a reference phase synchronized with the timing signal of the training area.
The master clock creating means 110 creates a plurality of master clocks having a floor phase using the reference clock from the clock generating means 102 as a reference phase, and calculates a master clock corresponding to the target cylinder on which the servo head means 18 tracks on. And outputs the selected master clock (cylinder switching function).
[0029]
To detect the head position signal, the duty pulse generator 120 generates a duty pulse having a duty ratio corresponding to the phase difference from the master clock reference phase to the zero-cross detection pulse. The integrating means 124 integrates the duty pulse to generate a position signal indicating the position of the servo head means 18.
Further, a duty measuring means 1 for measuring a duty ratio of a duty pulse in an on-track state of the servo head means 18 with respect to a specific target cylinder in an initialization process immediately after power-on is provided. The duty measuring means 1 can obtain an integrated signal indicating the duty ratio by inverting the duty pulses corresponding to the second and third fields of the servo information and outputting the inverted pulses to the integrating means 124.
[0030]
The measurement result of the duty measuring means 1 is given to the duty adjusting means 2 to adjust the duty ratio of the duty pulse to 50% in the on-track state of the target cylinder. The duty adjustment unit 2 includes a first delay unit 108 for delaying the reference timing of the master clock to reduce the duty ratio, and a second delay unit 114 for delaying the timing of the zero-cross detection pulse to increase the duty ratio. You.
[0031]
The first delay means 108 includes a shift circuit that delays the master clock stepwise by a predetermined time within one cycle of the reference clock, selects one of the shift stage outputs of the shift circuit, and sets a desired delay to the master clock. Give the amount.
The second delay unit 114 includes a plurality of delay elements (delay lines) having a determined delay amount, and selectively connects the plurality of delay elements in series to provide a desired delay amount to the zero-cross detection pulse clock.
[0032]
The adjustment of setting the duty ratio of the duty pulse to 50% is also applied to the detection of the head position based on the servo information recorded on the data surface. That is, the duty ratio is similarly measured in a state where the servo head means 20 is switched to the data head means 18 by the selection means 116, and the duty ratio is adjusted to 50% with a delay.
[0033]
An integrating error measuring means for measuring an integrating error and a correcting means therefor are provided for circuit adjustment of the integrating means. The integration error measuring means simulates supplying the servo head means 18 with a duty pulse corresponding to an on-track state to an arbitrary target cylinder position on the servo surface to the integrating means 124 during the power-on start initialization processing. To measure the integration error. Specifically, a duty pulse in which the first to fourth fields of the servo information all have a duty ratio of 50% is pseudo-generated and supplied to the duty pulse creating means 120 as a zero-cross detection pulse (read pulse). After the initialization process is completed, the integration error correction means corrects the position signal obtained from the integration means 124 with the measured integration error to obtain a correct position signal.
[0034]
Further, in order to measure the cylinder gain indicating the head movement amount per cylinder, at the time of the initialization processing of the power-on start, a duty pulse equivalent to on-tracking the servo head means 18 to an arbitrary target cylinder is generated. Switching to generation of a duty pulse equivalent to moving one cylinder in one direction or generation of a duty pulse equivalent to moving one cylinder in the opposite direction is performed, and the change in position is measured by the integration means 124, respectively. Then, the amount of position change per cylinder is obtained based on these measurement results, and is set as a cylinder gain used for head positioning control after the initialization processing.
[0035]
Specifically, the duty pulse generating means 120 generates a duty pulse in which the duty ratio of all the first to fourth fields of the servo information is 50% at the target cylinder position, and the duty ratio 25 at the position shifted by -1 cylinder. A duty pulse that changes as%, 75%, 75%, and 25% is generated, and a duty pulse that changes as duty ratio 75%, 25%, 25%, and 75% is generated at a position moved by +1 cylinder.
[0036]
On the other hand, in order to realize seek control using a head position detection signal obtained discretely, a speed detecting means for detecting a head moving speed at each sampling cycle at which a position signal is generated at the time of seeking, and the following at each sampling cycle: There is provided a position estimating means for estimating the head position at the time of sampling and causing the clock selecting means 110 to select a reference clock having a phase corresponding to the target cylinder obtained by the position estimation.
[0037]
At the time of seek control, the position predicting means switches the target cylinder in each of the first to fourth fields of the servo area according to the head moving speed, and causes the master clock of the corresponding phase to be selected. In the switching of the target cylinder, as the head moving speed increases, the number of switching stages in the first to fourth fields and the number of changes of the target cylinder for each switching increase.
[0038]
When the head moving speed defined by the number of moving cylinders in the sampling cycle is within the number of repeating cylinders of the servo information, the position predicting means selects the corresponding master clock without switching the target cylinder in the first to fourth fields. Let it. That is, when the number of cylinders for repeating servo information is four, and when the head moving speed is -4 cylinders to +4 cylinders, the target cylinder is not switched in the first to fourth fields and the phase corresponding to the center target cylinder is not changed. Select the master clock.
[0039]
When the head moving speed defined by the number of moving cylinders in the sampling period exceeds the number of repeating cylinders of the servo information, the target cylinder is switched into two stages by dividing the first and second fields and the third and fourth fields. A master clock having a corresponding phase is selected. For example, when the number of repeating cylinders of the servo information is four, if the head moving speed is −2 to +6 cylinders, the target cylinder is switched to the target cylinder one cylinder less than the center cylinder in the first and second fields, and In the fourth field, the target cylinder is switched to a target cylinder one cylinder more than the center cylinder, and a master clock having a corresponding phase is selected.
[0040]
When the head moving speed is further increased, the target cylinder is switched in four stages for each of the first to fourth fields to select a master clock having a corresponding phase. In this case, the number of switching cylinders in the head moving direction may be increased to 1, 2, 3.
In order to improve the accuracy of the position prediction in the seek control, the position prediction means detects the acceleration of the head movement and predicts the head position at the next sampling time. For the prediction including the acceleration, for example, the predicted position is calculated by adding the number of moving cylinders depending on the head acceleration to the current position based on the head drive current.
[0041]
According to the present invention, data surface servo information writing means is provided for writing servo information to the data surface. The data surface servo information writing means is provided in each of the plurality of servo frames arranged in the circumferential direction of the specific cylinder on the data surface in the first and fourth fields (EVEN1, 2) among the four fields. And the servo information having the opposite phase change is recorded in the second and third fields (ODD1, 2) to form a servo area.
[0042]
Here, since a small MR head is used for the read head of the data head with respect to the servo head, a position signal that changes linearly with the movement of the head cannot be obtained even if the same servo information is recorded on the servo surface. .
Therefore, for example, when servo information is recorded on the servo surface at a 0.5 cylinder pitch, the data surface servo information writing means writes the servo information on the data surface at the same 0.5 cylinder pitch as the servo surface, and The servo information of the first field (EVEN1) and the fourth field (EVEN2) and the phase information of the second field (ODD1) and the third field (ODD2) are written with a shift of 0.25 cylinder pitch.
[0043]
In order to enable writing of servo information to such a servo surface, write pulses for 16 phases synchronized with the rise and fall of the reference clock are generated, and seek is performed in 0.25 cylinders at each cylinder position. The write pulse of the corresponding phase number of the first to fourth fields is selected to write the servo pattern.
In general, when the number of cylinder repetitions of servo information recorded on a servo surface is N, the data surface servo information writing means applies a write pulse obtained by dividing the reference clock by 1 / N to 1 for the reference clock. / 4N types of write pulses having phases different from each other by a period of / 4N are generated, and a write pulse having a predetermined phase specified by a write cylinder is selected from the write pulses, and is written to the servo area on the data surface. Write the servo information corresponding to the servo information on the servo surface.
[0044]
Servo information for the data surface is written to the outer cylinder outside the user area of the data surface for use in off-track measurement of the data surface. Also, servo information is written to the last inner cylinder in order to measure the yaw angle offset of the head drive mechanism.
In the yaw angle offset measurement, at the time of the initialization process of the power-on start, the data head means integrally provided with the write head and the read head is moved to the outer cylinder and the inner cylinder of the data surface based on the servo information of the servo surface. The data head means is positioned at each position, and the yaw angle offset of the read head accompanying the rotation of the head arm is measured based on the servo information of each cylinder.
[0045]
The measured inner and outer yaw angle offsets are used in the interpolation calculation for obtaining the yaw angle offset at each cylinder position by the interpolation calculation, and a correction table is created using the Linder address as an index. The correction table may store the yaw angle offset in units of a predetermined number of cylinders.
In the yaw angle offset correction, for example, when a data surface read error occurs, the yaw angle offset is corrected and a retry operation is performed.
[0046]
According to the present invention, the data bits 0 and 1 are converted into two types of servo patterns for reading and writing by using a writing / reading function of a phase servo pattern located on the data surface. In order to realize this function, data writing means for writing data using servo information to a specific cylinder outside the user area on the data surface, and data writing by reading the servo information written by the data writing means. Is provided.
[0047]
The data writing means writes servo information using duty pulses having different duty ratios in the first and fourth fields and duty ratios in the second and third fields corresponding to the write data bits 0 and 1.
For example, corresponding to the write data bit 0, the duty pulses of the first to fourth fields with the duty ratios of 25%, 75%, 75%, and 25% are written. Also, the servo information is written using a duty pulse having a duty ratio of 75%, 25%, 25%, 75% for the first to fourth fields as data bit 1.
[0048]
The data reading means supplies a read signal of the servo information on the data surface to the duty pulse creation means 120 to generate a duty pulse, and further integrates the data bit 0 or 1 from the signal obtained by integrating the duty pulse by the integration means 120. Restore.
Further, in the disk drive of the present invention, the drive signal is supplied to the VCM according to the polarity and magnitude of the converted signal of the VCM D / A converter with respect to the reference voltage giving the midpoint, and the D / A conversion is performed. There is an error between the center value and the reference voltage. Therefore, in the initialization process of the power-on start, the head drive data for the DA converter is changed from the center value, an error until the AD conversion signal matches the reference voltage is obtained, and after the initialization process, the error is output to the DA converter. Correction is made so that the measurement center error is removed from the output head drive data.
[0049]
In addition, for automatic adjustment of the servo system, the coarse time until switching from the coarse control to the fine control by the seek operation is measured while varying the gain for determining the acceleration / deceleration of the target speed pattern used for the speed control as an adjustment value. Further, the absolute integral value of the position error from the time when the control is switched to the fine control in the seek operation to the time when the track is turned on is measured while varying the gain for determining the acceleration / deceleration of the target speed pattern used for the speed control as an adjustment value.
[0050]
Then, the servo system is automatically adjusted by detecting the sum of the absolute integral value of the position error and the core time obtained by the measurement as the evaluation function, and detecting the minimum adjustment value as the optimum value.
Further, the on-track slice value for judging the on-track state at the time of erasing is changed to a value enlarged from the on-track slice value at the time of reading and writing.
[0051]
[Action]
According to such a disk device of the present invention, the following effects can be obtained.
Since the servo read pulse is detected by the zero-cross detection with respect to the read signal of the servo information, the head position can be accurately detected without causing jitter due to noise such as peak detection.
[0052]
Further, when the reference clock is synchronously controlled by peak detection and the servo information is detected at zero cross, the duty pulse based on the phase difference detection at the time of on-track inevitably deviates from 50%. %, The offset of the position signal obtained by the integration circuit during on-track can be removed. This delay adjustment simultaneously corrects the deviation of the duty ratio due to the circuit delay.
[0053]
Further, by performing the correction for measuring the integration error signal due to the variation of the integration circuit and removing the integration error signal from the position data obtained by the A / D conversion, the position can be detected with higher accuracy.
Further, by switching the cylinders in the first to fourth fields according to the head speed at the time of seeking, even if the head speed exceeds the range of ± 4 cylinders, which is the detection limit of the position signal, the head position is accurately detected and the speed is increased. Seek can be realized.
[0054]
Further, by including a change in the head position due to acceleration, more accurate position prediction can be performed, and a seek error due to a large deviation in position prediction can be prevented.
In addition, by writing a unique phase servo pattern suitable for the readhead core width on the data surface that uses a small readhead for the servo head, off-track measurement and yaw angle offset measurement on the data surface are possible. Then, a correction process based on each measurement result can be performed.
[0055]
Further, by using two types of servo information corresponding to data bits 0 and 1 to read and write data in a free area other than the user area on the data surface independently of access from a higher-level device, the disk device can be used alone. It is possible to read and write the minimum information required for the configuration and adjustment.
Further, by adjusting the center value for VCM, optimizing the adjustment value of the servo system, expanding the on-track slice value at the time of erasing, etc., the performance of the disk device can be further improved.
[0056]
【Example】
<Table of Contents>
1. Hardware configuration
2. Functional configuration of disk unit
3. Phase servo pattern on servo surface
(1) Position signal creation circuit
(2) Servo frame
(3) Phase servo pattern
(4) Writing the phase servo pattern
(5) Position detection by reading the phase servo pattern
4. Duty ratio measurement and delay adjustment
(1) Integration circuit
(2) Duty ratio deviation during on-track
(3) Duty ratio measurement
(4) Delay adjustment of duty ratio
5. Adjusting the integration circuit
6. Position prediction including acceleration component
7. Cylinder switching by seek speed
8. Phase servo pattern on data surface
9. Read / write with phase servo pattern on data surface
10. Measuring and correcting yaw offset
11. Center value adjustment of VCM DA converter
12. Rezero operation
13. Automatic adjustment of servo system
14． Increase of on-track slice value during erase
15. Other
1. Hardware configuration
FIG. 2 shows the overall configuration of the disk drive of the present invention. The disk device of the present invention includes a disk enclosure 10 and a drive controller 12. The disk enclosure 10 is provided with a spindle motor 14 for rotating the disk and a voice coil motor (hereinafter, referred to as “VCM”) 16 for moving the head. Further, a servo head 18 and a servo head IC 22 are provided to read information on the servo surface of the magnetic disk.
[0057]
Further, data heads 20-1 to 20-n and a data head IC 24 are provided for reading and writing information on a plurality of data surfaces. Each of the data heads 20-1 to 20-n has a write head and a read head integrally in a head portion. A magnetic head is used as a write head, and an MR head using a magnetoresistive element is used as a read head.
[0058]
Here, the servo head 18 and the write head and the read head provided in the data heads 20-1 to 20-n have the largest core width of the servo head 18 and the next largest write head core width. The head (MR head) has the smallest core width. For example, if the track pitch of the data surface is 7 μm, the core width of the servo head 18 is 7 μm which is almost equal to the track pitch. On the other hand, the write head provided in the data head has a core width of 6 μm, and the core width of the MR head as a read head is about half, that is, about 3 μm.
[0059]
The drive controller 12 is provided with a control processor 26 as an overall control unit. The control processor 26 is coupled to an upper disk control unit via an interface circuit 28, receives various commands such as a seek command, a read command, and a write command, and executes a corresponding process.
A drive processor 30 for executing head positioning control is provided under the control processor 26. As the drive processor 30, a digital signal processor is used. For detecting the head position with respect to the drive processor 30, a position signal generating circuit 36 is provided.
[0060]
A read signal of the servo head 18 is input to the position signal generating circuit 36. In the present invention, the phase servo information is recorded on the data surface of the disk medium, and the position signal generating circuit 36 generates a position detection signal indicating the head position based on the read signal of the phase servo information. The position signal from the position signal creation circuit 36 is converted into digital data by the AD converter 38 and is taken into the drive processor 30.
[0061]
The drive processor 30 controls the spindle motor 14 via a DA converter 32 and a driver 34. In addition, the VCM 16 is driven via the DA converter 40 and the driver 42 to control the position of the head. The head positioning control by the drive processor 30 performs seek control for moving the head to the target cylinder based on a seek command and on-track control for maintaining the on-track state when the head reaches the target cylinder.
[0062]
Here, the seek control is composed of a coarse control and a fine control. The coace control is control for moving the head immediately before the target cylinder in accordance with the target speed pattern. The fine control is a control in which the head is drawn into the target cylinder by switching from the speed control to the position servo control when reaching the position immediately before the target cylinder, for example, 0.5 cylinder before by the coarse control.
[0063]
On the other hand, an encoding / decoding circuit 44, a demodulation circuit 48, and a bias current control circuit 46 are provided to read / write data from / to the data surface of the disk medium. Known circuits can be used for these read / write circuits as they are.
Furthermore, in the present invention, the phase of the servo surface is added to an inner guard band region located at the inner end and an outer guard band region located at the outer side with respect to a specific cylinder or user region on the data surface of the disk medium. The equivalent phase servo pattern corresponding to the servo pattern is recorded. In order to detect the head position by reading the phase servo pattern on the data surface with a read head provided on the data head, the read signal of the read head from the data head 24 is passed through a demodulation circuit 48 to a position signal generation circuit 36. To supply.
[0064]
FIG. 3 shows a partially cut-away device structure of the disk enclosure 10 in the disk device of the present invention shown in FIG. 3, eleven magnetic disks 50-1 to 50-11 are rotatably incorporated in a case 52 of the disk enclosure 10 by supporting a rotating shaft 54, and a spindle motor (not shown) provided at a lower portion is provided. ).
[0065]
A head actuator 58 is provided on the right side of the magnetic disks 50-1 to 50-11, and the head provided at the tip can be moved integrally in the radial direction of each medium surface of the magnetic disks 50-1 to 50-11. . In this embodiment, the magnetic disks 50-1 to 50-11 have a diameter of 5.25 inches.
FIG. 4 shows a longitudinal section of the head actuator 58 of FIG. 3 together with a magnetic disk. The head actuator 58 has a block 62 rotatably mounted on a fixed shaft 60 via upper and lower bearings 56-1 and 56-2. The coil 64 of the VCM 16 is mounted on the right side of the block 62. On the left side of the block 62, eleven arms 66-1 to 66-11 are integrally extended. Two heads are supported at the tips of the arms 66-1 to 66-11 via a pair of spring arms.
[0066]
In this embodiment, 20 heads are provided for 11 magnetic disks 50-1 to 50-11. Of the heads, the upper nine heads are data heads 20-1 to 20-9, and the servo head 18 is provided subsequently. The remaining ten heads following the servo head 18 are data heads 20-10 to 20-19.
[0067]
The disk surfaces of the magnetic disks 50-1 to 50-11 facing the data heads 20-1 to 20-19 are data surfaces used for reading and writing data. On the other hand, the medium surface above the magnetic disk 50-6 where the servo head 18 is located is a servo surface on which servo information is recorded on all tracks. According to the present invention, a phase servo pattern is recorded on the servo surface.
[0068]
The reason that the medium surface of the magnetic disk 50-6 at the center of the magnetic disks 50-1 to 50-11 facing the servo head 18 is set as the servo surface is that the servo surface is located at the center, so that the farthest magnetic disk is located. This is for minimizing the distances to 50-1 and 50-11, and for minimizing the offset amount as a position variation on each data surface with respect to the servo surface due to mechanical deformation due to temperature change.
2. Functional configuration of disk unit
FIG. 5 shows various control functions centered on head positioning control in the disk device of the present invention realized by processor control of the drive processor 30 provided in the drive controller 12 of FIG.
[0069]
In FIG. 5, as hardware directly related to the control function of the drive processor 30, the VCM 16, the servo head 18, the data head 20, the DA converter 32 for the VCM 16, the position signal creation circuit 36, and the AD converter 38 are included. Is shown. Of these, the data head is actually provided with a plurality of data heads, but for simplicity of description, one data head 20 is shown as a representative. Since the position signal creation circuit 36 creates a position signal from the phase servo pattern on the servo surface or the phase servo pattern on the data surface, this switching is indicated by a virtual switch 68.
[0070]
The drive processor 30 of the drive controller 12 includes a servo automatic adjustment unit 70, a data plane phase information writing unit 70, a data plane bit data writing / reading unit 74, a yaw angle Cylinder switching which is a function of the offset measurement unit 76, the yaw angle offset correction unit 78, the VCM DAC center value adjustment unit 80, the rezero processing unit 82, the duty delay adjustment processing unit 84, the integration circuit adjustment processing unit 86, and the seek control unit 88 A control unit 90, a position prediction processing unit 92, a thermal offset measurement unit 94, a thermal offset correction unit 96, and a padding processing unit 98 are provided. The details of each processing unit provided in the drive processor 30 will be clarified later, but the outline will be described as follows.
[0071]
In the final stage of the production process in which writing of the phase servo pattern is completed by a dedicated device such as a servo writer or the like on the servo surface, the servo system automatic adjustment unit 70 performs acceleration and deceleration in the target speed pattern used for the cores control. The adjustment value for determining the inclination (speed gain) is adjusted to an optimum value through simulation of seek control.
[0072]
The data surface phase information writing unit 72 as a data surface servo information writing unit uses a write head (magnetic head) provided on the data head 20 to specify a specific cylinder of an inner guard band and an outer guard band on the data surface. Then, a phase servo pattern peculiar to the data surface capable of generating a position signal by reading a read head (MR head) of the data head corresponding to the servo information on the servo surface is written. Writing of the phase servo pattern on this data surface is also performed in the final manufacturing process of the disk device.
[0073]
The data side bit data writing / reading unit as the data writing unit and the data reading unit using the phase servo information is provided in a single unit in which the drive controller 12 shown in FIG. 2 is not coupled to the upper disk control unit. The various setting data and the data such as the machine number are read and written in the free area other than the user area on the data surface by using the writing and reading functions of the phase servo information. The function of the data surface bit data writing / reading unit 74 is also used at the final stage in the disk device production process or at the time of system construction at the installation site.
[0074]
The yaw angle offset measuring unit 76 as a yaw angle offset measuring unit uses the phase servo pattern written in the inner guard band region and the outer guard band region of the data surface by the data surface phase information writing unit 74 to An offset at the innermost and outermost positions of the head due to driving, that is, a yaw angle offset is measured.
[0075]
A yaw angle offset correction unit 78 as a yaw angle offset correction unit corrects the read head offset when the data surface is read by the read head based on the measurement result of the yaw angle offset measurement unit 76. The measurement processing by the yaw angle offset measurement unit 76 is performed at the time of initialization processing by power-on start.
The VCM DAC center value adjustment unit 80 adjusts the center value of the DA converter 32 used to supply a drive current to the VCM 16 during the power-on start initialization process.
[0076]
The re-zero processing unit 82 performs, for example, a re-zero operation of the head located in the innermost contact start / stop area in the outermost re-zero operation in the initialization processing by power-on start.
The duty delay adjustment processing section 84 constituting the duty measuring means and the duty adjusting means has a duty ratio of a duty pulse generated at the time of on-tracking in the position signal generating circuit 36 due to the detection of the read signal of the phase servo information being zero cross detection. Is adjusted so that a duty pulse having a duty ratio of 50% can always be generated in an on-track state.
[0077]
The integration circuit adjustment processing unit 86 adjusts the integration error of the integration circuit that performs the integration operation based on the duty pulse provided in the position signal generation circuit 36 (integration error adjustment means), and the amount of change in the head position signal per cylinder Is measured (measurement means and cylinder gain setting means).
The cylinder switching control unit 90 provided as a function of the seek control unit 88 switches the target cylinder that determines the pseudo clock used to generate the position signal in the position signal generation circuit 36 based on the seek speed. The position prediction processing unit 92 as the position prediction means needs to know the target cylinder where the head is located at the next sampling by the position signal creation circuit 36 and switch to the corresponding master clock. For position prediction, accurate position prediction is performed including acceleration in addition to speed.
[0078]
Here, the seek control unit 88 of the present invention does not use a track crossing pulse as in the conventional head position control by two-phase phase servo, but uses a predetermined period determined by a position signal generation cycle of the position signal generation circuit 36. Coass control (speed control) is performed using a head position signal discretely obtained for each sampling period.
Regarding such Coass control not using a track crossing pulse, the “Applicant's International Patent Application No. WO09 / 11636, filed on June 27, 1991, describes a“ disk drive head positioning control device and control method thereof ”. It is described in the specification.
[0079]
In brief, the drive processor 30 calculates the head moving speed from the current head position and the previous head position, predicts the head position at the next sampling, and calculates the number of remaining cylinders for the target cylinder. Then, a target speed is obtained from a target speed pattern set in advance based on the number of remaining cylinders, a current value of the VCM 16 corresponding to a difference between the actual speed and the target speed at that time is calculated, and the VCM 16 is driven via the DA converter 32. I do.
[0080]
The thermal offset measuring section 94 seeks the data head to the phase servo pattern written in the outer guard band area of the data surface, detects, for example, 16 offsets for one round of the cylinder due to the temperature fluctuation of the device, and detects each offset. Create a thermal offset correction table using the rotation position as an address.
The thermal offset correction unit 96 uses the correction table created by the thermal offset measurement unit 94 to correct a position control signal output to the DA converter 32 during on-track control. The measurement process by the thermal offset measuring unit 94 may be performed according to a predetermined time schedule at the time of power-on start and thereafter, but according to the present invention, the disk device monitors an idle state in which no command is received. Then, when it is determined that no command has been received, the thermal offset process is executed.
[0081]
When the padding processing unit 98 receives an erase command for a specific cylinder from the upper disk control unit, the padding processing unit 98 expands the on-track slice value indicating the allowable range of the head positioning signal in the erase operation as compared with a normal read operation or write operation. The on-track slice value is changed, and even if the off-track is large, the erasing operation is continued as far as possible without erasing the adjacent track.
[0082]
FIG. 6 shows a series of processes performed in the final stage of the assembling process before product shipment among the processing units shown in the drive processor 30 of FIG. That is, in the final stage of the production process before product shipment, first, in step S100, a process of writing a phase servo pattern on the servo surface is performed. This writing process of the phase servo pattern is usually performed using a dedicated servo writer. After the writing of the phase servo pattern on the servo surface is completed, in step S200, the servo system automatic adjustment unit 70 is used to perform automatic adjustment processing of the servo system, that is, adjustment for determining the inclination of acceleration / deceleration of the target speed pattern in the coace control. Perform value optimization adjustment processing.
[0083]
After the servo system automatic adjustment process is completed, in step S300, the data surface phase information writing unit 72 is used to write a phase servo pattern on the data surface. Subsequently, in step S400, various data necessary for the disk device alone are used for the empty cylinders in the outer guard band area (OGB1 and inner guard band area (IGB1)) on the data surface using the data surface bit data write / read unit 74. Is written using the phase servo pattern.
[0084]
Subsequently, in step S500, the data head is sequentially sought in the inner guard band area (IGB1) and the outer guard band area (OGB1) of the data surface on which the phase servo pattern is written, and the data heads are provided on the innermost and outermost data heads. The yaw angle offset of the read head (MR head) is measured, and the yaw angle offset at each user cylinder position is obtained by linear interpolation to perform a yaw angle offset process for creating a correction table.
[0085]
The above is the processing at the final stage of the assembling process before the product is shipped. The other processing is initialization processing accompanying power-on start after installation of the disk device, seek control based on a higher-order command after completion of the initialization processing, read / write. Done through.
FIG. 7 shows the overall processing operation in the operation state of the disk device of the present invention. In FIG. 7, when power-on start is performed by turning on the power of the disk device, first, in step S1, a basic initialization process including a program load initialization diagnosis is performed. Subsequently, in step S2, the VCM DAC center adjustment unit 80 performs center adjustment processing of the VCM DA converter 32.
[0086]
Next, in step S3, the rezero processing section 82 is activated to seek the head to the outer guard band area (OGB1) and perform a rezero operation for obtaining the absolute value of the cylinder address. Next, the process proceeds to step S4, where a delay adjustment process for adjusting the duty ratio of the on-track duty pulse to 50% in the position signal generation circuit 36 using the duty delay adjustment processing unit 84 is performed. Subsequently, in step S5, the integration circuit adjustment processing unit 86 is activated to create an error correction value by detecting an integration error at the time of on-track when the position signal of the integration circuit provided in the position signal creation circuit 36 becomes zero. Adjustment processing of the integration circuit including measurement of a cylinder gain indicating a change amount of the position signal when the head is moved by one cylinder is performed. As described above, after the series of processes associated with the power-on start in steps S1 to S5, the disk device is in a ready state, and in step S6, a command is awaited from a higher-level disk control unit.
[0087]
In step S6, when a command accompanying the execution of the input / output command in the upper disk control unit is received, the command is decoded in step S7. In the case of a normal input / output request, the seek command is received first. In S8, a seek operation is performed to perform seek control of the head to the target cylinder to bring it into an on-track state.
[0088]
When the seek operation is completed, in step S9, a read operation or a write operation accompanying the obtained read command or write command is performed. At the end of the read operation or the write operation, if it is determined in step S10 that there is an error, the process returns to step S9 to retry the read operation or the write operation. If there is no error, in step S11, a normal completion status response is returned to the upper disk control unit, and the process is terminated. Then, the process returns to step S6.
[0089]
On the other hand, when waiting for a command to be received in step S6, the disk device is in an idle state, and in this idle state, the process proceeds to step S12 to check whether a predetermined measurement process is possible. If it is determined that the state in which the command is not received is continuously measurable, the process proceeds to step S13, and in the present invention, the thermal offset measuring unit 94 executes the thermal offset measuring process.
3. Phase servo pattern on servo surface
(1) Position signal creation circuit
FIG. 8 shows an embodiment of the position signal generating circuit 30 provided in the drive controller 12 of FIG. Note that the servo head 18, the data head 20, the drive processor 30, and the DA converter 38 related to the position signal generation circuit are also shown.
[0090]
In FIG. 8, a read signal of the servo surface read by the servo head 18 is input to a peak detection circuit 100, and a peak detection pulse (read pulse) that detects a peak timing of a read waveform is output. Here, the magnetic recording and reading on the servo surface and the data surface of the disk are as shown in FIG.
FIG. 9A shows a write signal. As shown in FIG. 9B, the polarity of the medium is magnetized to the N pole at the rise of the write signal, and the S polarity is magnetized at the fall of the write signal. As shown in FIG. 9C, a read signal obtained by reading the magnetization state of the medium has a positive read waveform at the N-pole magnetized portion and a negative read waveform at the S-pole magnetized portion. Can be In an actual servo pattern, since the interval between the N pole and the S pole is very short, the read waveform in FIG. 9C is a continuous sine waveform.
[0091]
FIG. 9 (D) is a simplified representation of the magnetization state of the medium of FIG. 9 (B), where the magnetized portion of the N pole is indicated by a solid line 212 and the magnetized portion of the S pole is indicated by a dotted line 214. The track recording state of the following phase servo pattern is represented by a solid line 212 indicating the N-pole magnetization state and a dotted line 214 indicating the S-pole magnetization state.
The peak detection circuit 100 of FIG. 8 that functions as a part of the read pulse detection means detects the peak timing of the read waveform of the read signal of FIG. 9C and outputs a peak detection pulse rising at the peak timing. . Specifically, a differentiated pulse is generated after slicing the read waveform at a certain level.
[0092]
The output of the peak detection circuit 100 is given to a PLL circuit 102 and a marker detection circuit 104. The PLL circuit 102 oscillates a reference clock in synchronization with a peak detection pulse based on reading of a timing signal recorded in a training area at the head of a servo frame, which will be described later. The oscillation frequency of the PLL circuit 102 is 20 MHz in this embodiment, so that one clock cycle τ is 50 nsec. The marker detection circuit 104 detects a marker signal in a marker area following the training area of the servo frame.
[0093]
The guard band index detection circuit 105 detects a guard band signal and an index signal in a guard band index area following the marker area. The marker detection circuit 104 becomes operable upon receiving the marker search signal E1. The guard band index detection circuit 105 also receives the guard band search signal E3 to enter the guard band detection state, and receives the index search signal E4 to enter the index detection state.
[0094]
The marker detection circuit 104 outputs a marker detection signal E2. The guard band / index detection circuit 105 outputs a first outer guard band detection signal OGB1, a second outer guard band OGB2, and an index signal INDEX.
The PLL counter 106 counts the clock of the PLL circuit 102 from the time when the marker detection signal E2 from the marker detection circuit 104 is obtained. Therefore, the value of the PLL counter 106 provides a count value indicating the information recording position in the guard band index portion and the servo pattern portion, starting from the marker detection time.
[0095]
On the other hand, the output of the servo head 18 is supplied to a zero cross detection circuit 112 functioning as a part of the read pulse detection means via a selection circuit 116. According to the present invention, the phase servo read signal of the servo pattern portion provided at the end of the servo frame is subjected to zero cross detection instead of peak detection. By this zero-cross detection, a read signal of the phase servo can be reliably obtained even if noise is mixed.
As for the zero-cross detection, the zero-cross timing between the N-pole positive read waveform and the S-pole negative read waveform in the read signal of FIG. 9C is detected. Therefore, the zero-cross detection inevitably has a phase delay in the detection timing with respect to the peak detection of the read waveform. That is, for the reference clock by the PLL circuit 102, synchronization control by peak detection is performed. Originally, the read pulse by reading the phase servo must also be synchronized with the clock of the PLL circuit 102. Inevitably, a phase delay occurs with respect to the reference clock.
[0096]
The phase delay due to the zero-cross detection is adjusted by the variable delay circuit 114 and the shifter 108, and a duty pulse having a duty ratio of 50% at which the integrated voltage becomes zero in the on-track state can be created. Here, the shifter 108 digitally outputs the rising edge of a pulse signal obtained by dividing the reference clock of the PLL circuit 102, which is obtained as the second bit output of the PLL counter 106, to one-fourth in a range of 0 to 3τ. Adjust delay. On the other hand, the variable delay circuit 114 analogously delays the rising timing of the zero-cross detection circuit 112 by selectively connecting a plurality of analog delay elements. The delay adjustment by the shifter 108 and the variable delay circuit 114 will be described later in detail.
[0097]
The master clock creation circuit 110 creates a master clock having a period 4τ obtained by dividing the reference clock having a phase determined corresponding to the target cylinder by four, and outputs it as a master clock signal E10. Switching of the master clock having a phase corresponding to the target cylinder is performed by a cylinder switching signal E30 from the drive processor 36.
[0098]
The so-called cylinder switching by the cylinder switching signal E30 is a master clock having a phase corresponding to the target cylinder in which the head is currently located in the on-track control. On the other hand, at the time of seek control, a master clock having a phase corresponding to the target cylinder at the predicted next predicted position is created by adding the actual speed obtained at the previous head position and the current head position and further the acceleration. Switch to
[0099]
The duty pulse generation circuit 120 is a set / reset circuit, and is set at the rising edge (reference phase) of the master clock signal E10 corresponding to the target cylinder from the master clock generation circuit 110, and is a zero-cross detection pulse obtained through the selection circuit 118. Is reset at the falling edge (detection phase). When the servo head 18 is in the on-track state, the duty ratio is generated in the first field (EVEN1), the second field (ODD1), the third field (ODD2), and the fourth field (EVEN2) of the phase servo pattern from the duty pulse generation circuit 120. Duty pulses E19 of 50%, 50%, 50%, and 50% are output.
[0100]
The duty pulse E19 from the duty pulse creation circuit 120 is given to the integration circuit 124. The integration circuit 124 basically includes a capacitor 126 and four switch elements 128, 130, 132, and 134 that are bridge-coupled to the capacitor 126. The lower switch elements 132 and 134 for the capacitor 126 are on / off controlled by the duty pulse E19. On the other hand, the switching elements 128 and 130 on the upper side of the capacitor 126 are controlled to be switched according to the first to fourth fields of the phase servo pattern.
[0101]
Here, assuming that the polarity of the position signal taken out from both ends of the capacitor 126 is brass on the right side and minus on the left side as shown in the figure, the integration operation by switching of the switch elements 128, 130, 132, 134 in the first to fourth fields. Is as follows.
First, in the first field and the fourth field (EVEN1, 2), the switching element 128 above the capacitor 126 is turned on and 130 is turned off. In this state, the switching element 130 is turned on and off by the duty pulse E19. For this reason, the capacitor 126 is charged along the path indicated by the solid line, and the position signal viewed from the voltage across the capacitor 126 increases to the negative side.
[0102]
On the other hand, in the second and third fields (ODD1, 2), the switch element 130 above the capacitor 126 is turned on and 128 is turned off. In this state, the switch element 132 is turned on and off by the duty pulse E19. Accordingly, the capacitor 126 is charged along the path shown by the broken line, and the position signal viewed in the illustrated polarity increases to the positive side.
[0103]
In the on-track state with respect to the target cylinder, the duty pulse E19 has a duty ratio of 50% for all fields, and the number of pulses in each field is the same. The integration voltage becomes zero. When the servo head deviates from the state where the target cylinder is on-track, the duty ratio deviates from 50%, and a voltage corresponding to the change in the duty ratio is obtained in the capacitor 126.
[0104]
Specifically, when the servo head 18 moves in the minus direction, that is, toward the outer side with respect to the target cylinder, the duty ratio of the first and fourth fields (EVEN1, 2) decreases, and conversely, the second and third fields (EVEN1, 2). The duty ratio of ODD1,2 increases. On the other hand, when the servo head 18 moves in the plus direction, that is, toward the inner side with respect to the target cylinder, the duty ratios of the first and fourth fields (EVEN1, 2) increase, and the second and third fields (ODD1). , 2) is reduced.
[0105]
The switching control for each field of the switch elements 128 and 130 above the capacitor 126 in the integration circuit 124 is performed by output signals E5, E6, E7 and E8 from the coincidence detection circuit 122. The coincidence detection circuit 122 determines coincidence between the count value of the PLL counter 106 and a predetermined value, and outputs a signal corresponding to each coincidence position.
[0106]
That is, in addition to the search signals E1, E3, and E4 for the marker detection circuit 104 and the guard band / index detection circuit 105, the demodulation mode generator 122-1 outputs a demodulation mode signal E5 indicating the first to fourth fields. In addition, the half mode generation unit 122-2 outputs a half mode signal E6 indicating the position signal detection time point at the boundary between the second field and the third field. The data window generating unit 122-3 outputs a data window signal E7 for making the duty pulse for the integration circuit 124 valid in the first to fourth field periods.
[0107]
Further, the discharge control unit 122-4 outputs a discharge control signal E8 for resetting the discharge of the capacitor 126 at a timing other than the duty pulse generation period covering the first to fourth fields. The discharge reset by the discharge control signal E8 turns off the switch elements 128 and 130 provided in the integration circuit 124 and turns on the switch elements 132 and 134.
[0108]
The position signal E40 obtained as a voltage between both ends of the capacitor 126 of the integrating circuit 124 is taken into the drive processor 30 by the interrupt signal E9 obtained at the end timing of the servo frame by the AD converter 38.
On the other hand, in the present invention, a phase servo pattern is also written in the inner guard band area (IGB1) and the outer guard band area (OGB1) on the data surface, and the head position based on the phase servo pattern on the data surface is written. To enable detection, a read signal of a read head 410 provided in the data head 20 is input to a zero-cross detection circuit 112 via a selection circuit 116. The selection circuit 116 is switched by a control signal E31 from the drive processor 30. That is, in normal servo control, the selection circuit 116 is switched to the servo head 18 side. On the other hand, when reading the phase servo pattern on the data surface, the data head 20 is switched to the data head 20 in units of a predetermined number of servo frames in one rotation of the cylinder.
[0109]
That is, the phase servo information on the data surface is read while switching to the data head 20 discretely for the on-track control based on the phase servo information on the servo surface, and for example, thermal offset measurement and yaw angle offset measurement are performed.
Further, in the present invention, after the phase writer information is written on the servo surface by the servo writer, the disk device itself has a function of writing the phase servo pattern on the data surface. The data is generated by the clock generation circuit 110 and supplied to the write head 400 of the data head 20 to write the servo information on the data surface.
[0110]
Further, a selection circuit 118 is provided in order to create a duty pulse having an arbitrary duty ratio in a pseudo manner by the duty pulse creation circuit 120 and create a position signal by the integration circuit 124. The selection circuit 118 switches between a pseudo read pulse from the drive processor 30 and a zero-cross detection pulse obtained from the zero-cross detection circuit 112 according to the control signal E32.
[0111]
The generation of the duty pulse by the generation of the pseudo read pulse by the drive processor 30 is used for measuring the duty ratio of the actual duty pulse used for the adjustment of the duty 50% performed by the shifter 108 and the variable delay circuit 114.
(2) Servo frame
FIG. 10 shows servo information for one cylinder recorded on the servo surface of the disk drive of the present invention, developed on a straight line. In FIG. 10, the servo area 154 for one rotation of the disk is divided into 216 sections to form 216 servo frames 156. In the present invention, the number of clocks in the servo area 154 for one rotation of the disk is fixedly determined.
[0112]
One servo frame 156 includes a training section 158, a marker section 160, a guard band index section 162, and a servo pattern section 164 as shown in an enlarged manner. Assuming that the start position of the servo frame 156 is zero in each area, the training section 158 has a count value of 0 to 1128, the marker section 160 has 1128 to 1160, the guard band index section 162 has 1160 to 1268, and The servo pattern section 164 has a count value of 1268 to 1512.
[0113]
FIGS. 11, 12, 13 and 14 show the magnetic recording state of the training section 158, marker section 160, guard band index section 162 and servo pattern section 164 provided in the servo frame 156. Here, with respect to the training unit 158 of FIG. 11A, the marker unit 160 of FIG. 11B, and the guard band index unit 162 of FIG. 12, the reference clock 166 is shown on a scale of 4τ, which is 4 clock cycles. I have. On the other hand, in the servo pattern section 164 of FIGS. 13 and 14, the reference clock 166 is shown on a scale of 1τ, which is one clock cycle.
[0114]
The training area 158 shown in FIG. 11A records a timing signal for synchronizing the phase of the PLL circuit 102 shown in FIG. By reading the timing signal of the training unit 158 and obtaining the peak detection pulse at 4τ, the PLL circuit 102 can perform synchronous oscillation of 1τ = 50 ns, that is, 20 MHz synchronized with the actual disk rotation.
[0115]
FIG. 11B shows the marker unit 160 following the training unit 158. The marker section 160 plays a role of determining the position in the servo frame, starts the counting operation of the PLL counter 106 provided in FIG. 8 by marker detection, and causes the match detection circuit 122 to perform various types of match determination. A read signal of “LHHHHLHLHLH” is obtained from the marker section 160, and the marker is detected by detecting the coincidence of the illustrated 6-bit pattern of “L □ HH □ L □ L □ L □”.
[0116]
FIG. 12 shows the guard band index section 162. According to the present invention, the guard band index section 162 is divided into three areas of a first majority section 174, a second majority section 176, and a third majority section 178, and the same signal is repeatedly recorded in each area.
The guard band index detection circuit 105 shown in FIG. 8 obtains two or more pieces of coincidence information among the three first to third majority decision sections 174, 176, and 178 obtained from the read signal of the guard band index section 162. If it is determined that the guard band and the index are detected, the detection performance of the guard band and the index is improved.
[0117]
The servo surface is radially divided into an inner guard band region (IGB1) 180, a user region 182, a first outer guard band region (OGB1) 184, and a second outer guard band region (OGB2) 186 from the inner side. I have. The index information 188, 190, 192 is recorded in the inner guard band area 180 and the user area 182. Index information is not provided for the first and second outer guard band areas 184 and 186, and information indicating a unique area is recorded.
[0118]
FIGS. 13 and 14 show details of the servo pattern section 164 in which the phase servo pattern is recorded. The servo pattern section 164 includes a first field 200, a second field 202 shown in FIG. 13, and a third field 204 and a fourth field 206 shown in FIG. In the following drawings, the first field 200 is “EVEN1”, the second field 202 is “ODD1”, the third field 204 is “ODD2”, and the fourth field 206 is “ EVEN2. "
[0119]
The length of each of the first to fourth fields has the same length except for the unused portions 194, 196, 208 and 201. Specifically, assuming that 4τ for four periods of the reference clock is a reference length, each field has a length of 4τ × 10. In the first and fourth fields 200 and 206 to be EVEN1 and EVEN2, a pattern in which the phase is shifted by 1τ for every 0.5 cylinder movement in the increasing direction (inner direction) on the positive side of the cylinder number is written in a period of 8τ. In.
[0120]
On the other hand, the second and third fields 202 and 204 serving as ODDs 1 and 2 are written so as to have opposite phase shifts. Each phase servo pattern is repeated every four cylinders.
(3) Writing the phase servo pattern
The writing of the phase servo patterns shown in FIGS. 13 and 14 is performed using a dedicated servo writer. In the disk device of the present invention, after writing the phase servo pattern on the servo surface, the disk device itself has a function of writing the phase servo pattern on the data surface. The principle of writing a phase servo pattern on a surface will be described.
[0121]
FIG. 15 shows a write signal used for writing a phase servo pattern on a servo surface. FIG. 15A shows a reference clock, which is the same as the clock by the PLL circuit 102 shown in FIG. FIG. 15B shows a bit 2 output when the clock from the PLL circuit 102 is counted by the PLL counter 106, which is a pulse signal obtained by dividing the frequency of the PLL clock by １. This pulse signal becomes the write signal of phase number 0.
[0122]
FIGS. 15C to 15I show signals obtained by sequentially shifting the phase of the write signal having the phase number 0 by the clock period 1τ, and the signals of the phase numbers 2, 4, 6, 8, 10, 12, and 14 are shown. It becomes a write signal. For writing the servo pattern on the servo surface, a combination of eight write signals having even phase numbers shown in FIGS. 15B to 15I is used.
[0123]
FIG. 16 shows write signals having odd-numbered phase numbers 1, 3, 5, 7, 9, 11, 13, and 15, which are further required when the disk device of the present invention writes a phase servo pattern on a data surface. That is, the clock shown in FIG. 16A is a clock obtained by inverting the PLL clock of FIG. 6A, and the falling timing of the clock before the inversion is set as the rising timing.
[0124]
By using the inverted PLL clock of FIG. 16A to shift the phase of the bit 2 output of the PLL counter 106 shown in FIG. 16B by 1τ at a time, the odd numbers shown in FIGS. Can be obtained. In the following description, the phase numbers 10, 11, 12, 13, 14, and 15 are represented in hexadecimal notation A, B, C, D, E, and F.
[0125]
FIG. 17 shows a circuit for creating the write signals of the phase numbers 0 to 16 shown in FIGS. This circuit is realized as the master clock generation circuit 110 in FIG.
In FIG. 17, a PLL clock is supplied to a shift circuit 500 as a shift pulse. On the other hand, the inverted PLL clock inverted by the inverting circuit 520 is input to the shift circuit 510 as a shift clock. Further, the bit 2 output of the PLL counter 106 is input to each of the shift circuits 500 and 510. The shift circuit 500 sequentially outputs eight types of write signals having phase numbers 0, 2, 4, 6, 8, A, C, and E every 1τ in synchronization with the PLL clock.
[0126]
On the other hand, the shift circuit 510 sequentially outputs write signals of odd-numbered phase numbers having phase numbers of 1, 13, 5, 7, 9, B, D, and F with a delay of 0.5τ from the shift circuit 500. . A multiplexer (selection circuit) 530 selects one of the 16 types of write signals output from the shift circuits 500 and 510 with a phase shift of 0.5τ.
[0127]
FIG. 18 shows write signal phase numbers when writing the phase servo patterns shown in FIGS. 13 and 14 while seeking the servo head by 0.5 cylinders. In the present invention, a combination of write signals having the same phase number is repeatedly used in units of four cylinders.
The writing of the phase servo pattern to such a servo surface is not performed by the disk device itself, but since the writing of the phase servo pattern to the data surface is enabled, the position of the servo head can be externally positioned as a function. It is possible to write the phase servo pattern also on the data surface.
[0128]
FIG. 19 shows the phase numbers for selecting the master clock used for switching the master clock corresponding to the target cylinder when reading the phase servo pattern written on the servo surface according to FIG. The writing of the phase servo pattern is performed in 0.5 cylinder units, but the master clock corresponding to the target cylinder is performed in 1 cylinder units and is repeated every 4 cylinders.
[0129]
Therefore, assuming that the cylinder numbers from the outer side to the inner side are 0 to 3, the master clock according to the pattern of the corresponding phase number corresponding to each target cylinder number 0 to 3 is generated by the master clock generation circuit 110. Created with Specifically, the circuit shown in FIG. 17 is provided in the master clock generation circuit 110, and the drive processor 30 sends a selection signal of a phase number corresponding to the cylinder number of the target cylinder at that time to the drive signal shown in FIG. Switching may be selected by the multiplexer 530 for each of the first and fourth fields according to the pattern.
[0130]
As described above, when detecting the position by reading the servo information on the data servo surface, of the 16 types of master clock signals shown in FIGS. 15 and 16, four types of combinations of phase numbers 0.4, 8, and 12 are used. Is used.
(4) Position detection by reading the phase servo pattern
FIG. 20 shows a timing chart of each signal output from the coincidence detection circuit 122 in FIG. 8 when one reads the phase servo pattern on the servo surface by the disk device of the present invention for one servo frame. In FIG. 20, when the synchronization of the PLL circuit 102 by the timing signal read from the leading training area in the reading of the servo frame is completed, the marker detection signal E2 shown in FIG. Is output. In response to the marker detection signal E2, the PLL counter 106 is activated as shown in FIG. 20C, and starts counting the clock signal E0 from the PLL circuit 102.
[0131]
Here, the period from the detection of the marker to the reading of the position signal at the end of the frame is determined to be 180H as the hexadecimal count value of the PLL counter 106. Therefore, the counter operation is performed until the hexadecimal count value 180H is obtained. Further, as shown in FIG. 20A, a marker search signal E1 for enabling the detection operation of the marker detection circuit 104 is also output over the same period.
[0132]
Subsequently, a guard band index detection signal E3 shown in FIG. 20 (D) is obtained over a period of 0 to B0H as a hexadecimal count value. At this time, the valid guard band index search signal E4 of FIG. 20E rises, and the detection operation of the guard band index detection circuit 105 is prohibited. The period from B0H to 148H in the hexadecimal count value in which the guard band index search signal E4 rises to the H level is the reading period of the servo pattern section 164.
[0133]
During the reading period of the servo pattern section 164, the coincidence detection circuit 122 outputs the demodulation mode signal E5 of FIG. 20 (F) which changes in the first field EVEN1, the second and third fields ODD1, 2 and the fourth field EVEN2. Then, the switch elements 128 and 130 above the capacitor 126 provided in the integration circuit 124 are selectively turned on / off in each field period. Also, it outputs a half mode signal E6 that gives a position detection point that is the middle point of the servo pattern section 164 shown in FIG.
[0134]
An interrupt signal E9 shown in FIG. 20H is generated until the next training unit 158 after the servo pattern unit 164 is completed. At this timing, the drive processor 30 performs the integration converted by the AD converter 38. A position signal determined by the voltage across the capacitor 126 of the circuit 124 is captured. Further, as shown in FIG. 20 (I), a discharge control signal E8 that is valid during a period other than the period in which the servo pattern portion 164 and the interrupt signal E9 are generated is output, and the capacitor 126 of the integration circuit 124 is reset to a discharge reset state. That is, it is in a zero voltage state.
[0135]
FIG. 21 shows a phase servo pattern on a servo surface, a master clock, a read pulse based on zero-cross detection, a duty pulse, and a change in the terminal voltage of the capacitor 126 based on the duty pulse based on the duty pulse.
In FIG. 21, the servo pattern on the servo surface is repeated with four cylinders of cylinder numbers 0 to 3. Suppose now that the servo head 18 is on-track on the second cylinder at the center. In this state, the master clock having the reference phase advanced by 4τ with respect to the phase servo pattern recorded in the cylinder number 2 is selected.
[0136]
Therefore, FIG.DThe duty pulse E19 shown in () is set at the rise of the reference clock every 4τ, and is reset when the phase servo pattern is read by the servo head 18. Since the track is in the on-track state, the duty ratio is 50% for all of the first to fourth fields EVEN1, ODD1, ODD2, and EVEN2.
[0137]
In the state where the duty ratio is 50%, the capacitor 126 of the integrating circuit 124 is charged in the minus direction in the first field EVEN1. Subsequently, the battery is charged in the plus direction in the second field ODD2, and is further charged in the plus field in the third field ODD2 after passing 0V. Finally, in the fourth field EVEN2, similarly to the first field EVEN1, the capacitor is charged in the negative direction, and when the reading of the phase servo pattern is completed, the capacitor voltage becomes zero voltage indicating on-track.
[0138]
When the servo head 18 seeks in the minus direction and on-tracks to the cylinder number 1 or 0, the duty ratio of 50% is selected by selecting the master clock of the reference phase advanced by 4τ phase with respect to the phase servo pattern of each track. % Duty pulse E19 is similarly obtained. This applies to the case where the servo head 18 is sought to the cylinder number 3 in the plus direction. Then, a head position signal that changes linearly according to the head position at a position of ± 2 cylinders with respect to the on-track cylinder position can be generated.
4. Duty ratio measurement and delay adjustment
(1) Integration circuit
FIG. 22 shows an embodiment of the integrating circuit 124 shown in FIG. In FIG. 22, the integration circuit 124 operates with a first power supply + Vdd1 and a second power supply + Vdd2. In this embodiment, the first power supply + Vdd1 to the second power supply + Vdd2 are generated by a circuit including the resistor R20, the transistor Q1, the constant current source 138, and the transistor Q2.
[0139]
Here, the transistors Q1 and Q2 operate as diodes for ensuring the voltage between the base and the emitter. The second power supply voltage Vdd2 represents the constant current of the constant current source 138 as i, the base-emitter voltage V of the transistors Q1 and Q2, and the base-emitter voltage of the transistors Q1 and Q2 as V._BEThen, it is given by the following equation.
Vdd2 = Vdd1-｛(R20 × i) + V_BE｝
That is, the voltage drop of the resistor R20 due to the constant current i from the first power supply voltage Vdd1 and the base-emitter voltage V_BEIs subtracted.
[0140]
Eight transistors Q3, Q4, Q5, Q6, Q7, Q8 which operate as current switches via resistors R1, R2, R4, R5, R6, R7, R9, R10 in parallel to such a power supply voltage. , Q9, Q10 are connected. The transistors Q3 to Q10 form a differential circuit with the transistors Q3 and Q4, Q5 and Q6, Q7 and Q8, Q9 and Q10, and the constant current sources 140, 142, 144 and 146 are connected to the common emitter side. ing.
[0141]
Control signals E20, E21, E22 and E23 are supplied to the transistors Q3, Q6, Q7 and Q10 of each differential circuit from the integration control circuit shown in FIG. That is, the control signal E20 controls the transistor Q3, the control signal E21 controls the transistor Q7, the control signal E22 controls the transistor Q6, and the control signal E23 controls the transistor Q10.
[0142]
The transistors Q3, Q7, Q6, and Q10 controlled by the control signals E20, E21, E22, and E23 respectively perform the differential on / off operations of the transistors Q4, Q8, Q5, and Q10 that are differentially connected. Transistors Q11 and Q12 are connected in series to transistors Q6 and Q7, respectively, and a capacitor 126 is connected therebetween.
[0143]
Therefore, the transistors Q11, Q12, Q6, and Q7 form a bridge-type switching circuit shown in the integrating circuit 124 of FIG. Servo transistors Q3, Q4 and Q9, Q10 for controlling transistors Q1, Q2 located above capacitor 126 are provided with demodulation mode signal E5 from demodulation mode generating section 122-1 provided in coincidence detection circuit 122 shown in FIG. Thus, switching control is performed according to the first to fourth field periods.
[0144]
Therefore, the control signal E20 for the transistor Q3 and the control signal E23 for the transistor Q10 are generated from the demodulation mode signal. On the other hand, the two transistors Q6 and Q7 located below the capacitor 126 are on / off controlled by control signals E21 and E23 based on the duty pulse E19 from the duty pulse generation circuit 120 shown in FIG.
[0145]
That is, the control signal E21 changes according to the duty pulse in the first and fourth fields, and the transistor Q11, the capacitor 126 and the transistor Q7 when the transistor Q7 is turned on and off, and the capacitor 126 by the constant current through the path determined by the constant current source 144. Charge.
On the other hand, in the second and third fields, the control signal E22 changes according to the duty pulse to turn on / off the transistor Q6, and a constant current flows through a path serving as the transistor Q12, the capacitor 126, the transistor Q6, and the constant current source 142. Then, the capacitor 126 is charged.
[0146]
The terminal voltage of the capacitor 126 is input to the operational amplifiers 148 and 150 operating as voltage followers and further to the differential amplifier 152 via the resistors R1 and R2. The gain of the differential amplifier 152 is determined by the center voltage Vc supplied from the drive processor 36 via the period resistors R33 and R34. Further, a reference voltage Vref is applied to the bases of the transistors Q4, Q5 and Q8, Q9, and sets a reference voltage as a midpoint for giving a relative charging voltage as viewed from the power supply voltage. Therefore, the terminal voltage of the capacitor 126 is charged or discharged to the plus side or the minus side around the reference voltage Vref.
[0147]
FIG. 23 shows an integration operation based on the control signals E20, E21, E22 and E23 supplied in the on-track state of the servo head in the integration circuit 124 shown in FIG.
FIG. 23A shows a simplified 4-phase phase servo pattern. In response to such reading of the phase servo pattern, the control signal E20 in FIG. 23B goes high in each of the first and fourth fields EVEN1 and EVEN2, turning on the transistor Q3 and turning off the transistor Q4. This turns on the transistor Q11. The control signal E23 shown in FIG. 23C is at the H level during the second and third fields ODD1 and ODD2, turning on the transistor Q10 and turning off the transistor Q9, thereby turning on the transistor Q12.
[0148]
FIG. 23A shows a state in which the servo head 18 is on-track at cylinder number 2, the clock pulse shown in FIG. 23D is selected as the master clock, and the read pulse shown in FIG. 23E is obtained. . Therefore, the duty pulse E19 shown in FIG. 23 (F) has a duty ratio of 50% in any of the first to fourth fields.
[0149]
In response to such a duty pulse E19, the control signal E21 of FIG. 23 (G) changes according to the duty pulse E19 in the first and fourth fields EVEN1 and EVEN2, and turns on and off the transistor Q7. Of the capacitor 126 via the transistor Q11 in the step (1).
[0150]
On the other hand, the control signal E22 shown in FIG. 23H changes according to the duty pulse E19 in the second and third fields ODD1 and ODD2, and is turned on and off by the transistor Q6 via the transistor Q12 which is on at this time. The constant current determined by the constant current source 142 flows through the capacitor 126 in the reverse direction to perform the integration operation.
Further, the data window signal E7 shown in FIG. 23 (I) is used for the actual integration operation, and the control signals E21 and E22 for the period when the data window signal E7 is at the H level cause the one-way movement of the capacitor 126. And a charging operation in the reverse direction is performed. At this time, since the servo head 18 is on-track to the cylinder number 2, the voltage across the capacitor when the integration operation of the first to fourth fields is completed is 0V.
(2) Duty ratio deviation during on-track
The duty ratio of the duty pulse generated based on reading the phase servo pattern that operates the integration circuit 124 shown in FIG. 22 is ideally 50% in the on-track state. However, as shown in the embodiment of FIG. 8, the synchronization of the PLL circuit 102 is performed by detecting the peak of the read signal, while the read signal of the phase servo pattern is performed by detecting the zero-crossing. However, the timing of the zero-cross detection is shifted, and a duty pulse having a duty ratio of 50% cannot be obtained in the on-track state.
[0151]
FIG. 24 shows the difference between the duty ratio when the peak of the reading of the phase servo pattern is detected and the duty ratio when the zero cross is detected as in the present invention.
As shown in FIG. 24A, when the servo head 18 is on-track in the cylinder of cylinder number 2 out of the four cylinders, the duty pulse is selected by selecting the master clock having the reference phase shown in FIG. The set timing in the creation circuit 120 is obtained, and in the case of conventional peak detection, a peak detection timing that matches the magnetic recording of the servo pattern is obtained as shown in FIG. In this case, the duty pulse has a duty ratio of 50% in the first to fourth fields as shown in FIG.
[0152]
However, in the zero cross detection of the present invention, the zero cross detection timing has a delay from the peak detection timing as shown in FIG. As a result, in the on-track state, the duty ratio of the duty pulse becomes 75% as shown in FIG. As described above, the reason why the duty ratio does not become 50% in the on-track state is arbitrarily caused by circuit delay in the analog circuit system in addition to the zero-cross detection. turn into.
[0153]
Therefore, in the disk device of the present invention, first, the duty ratio of the duty pulse obtained in the on-track state is measured, and the shifter 108 and the variable delay circuit shown in FIG. By setting the amount of delay for 114, an adjustment state with a duty ratio of 50% is automatically created during the power-on start initialization process.
(3) Measurement of duty ratio
FIG. 25 shows an embodiment of an integration control unit constituting a part of the integration circuit 124 shown in FIG. 8 which incorporates a function for measuring the actual duty ratio of the duty pulse E19 obtained in the on-track state.
[0154]
In FIG. 25, the integration control unit includes an inverting circuit 312, AND circuits 314, 322, 324, OR circuits 318, 320, 326, 328 and an exclusive OR circuit (EOR) 316. Among them, an AND circuit 314 and an exclusive OR circuit 316 are provided for measuring the duty ratio.
In this circuit, based on the ODD area inversion signal E20 from the drive processor 36, a duty signal is generated by inverting the pulses of the second and third fields ODD1 and ODD2 of the duty pulse E19 output from the duty pulse generation circuit 120.
[0155]
The circuit units other than the inversion circuit unit in the ODD area use the demodulation mode signal E5, the data window signal E7, and the discharge control signal E8 from the match detection circuit 122 located at the preceding stage, and (G) Generate the control signals E20, E23, E21 and E22 shown in (H).
FIG. 26 shows the integration operation of the duty pulse and the capacitor when the ODD area inversion signal E20 from the drive processor 36 is disabled and enabled.
[0156]
FIG. 26A shows a duty pulse E19 obtained in a non-measurement state of the duty ratio, which is a pulse train exceeding, for example, a duty ratio of 50% in all the periods of the first to fourth fields. FIG. 26B shows a change in the integrated voltage due to the duty pulse E19 when the duty ratio is not measured, that is, a change in the voltage across the capacitor 126. Even if the duty ratio deviates from 50%, the final integrated voltage becomes zero voltage. Therefore, there is basically no problem with position control during on-track.
[0157]
However, the position must be detected when the position signal changes in a range of ± 2 cylinders in the on-track state. Therefore, if the on-track duty ratio is 75%, the duty ratio changes from -50% to + 50% within a range of two cylinders. Therefore, the duty pulse changes from + 25% to + 125%, and if it exceeds + 125% and 100%, the position cannot be detected.
[0158]
Conversely, if the duty ratio is lower than 50%, for example, 25%, the duty ratio similarly changes in the range of -50% to + 50% in the range of four cylinders, and The duty ratio becomes -25% to + 75%, and if the duty becomes negative, position detection becomes impossible. For this reason, it is necessary to maintain the duty ratio of the duty pulse during on-track to 50%.
[0159]
FIG. 26C shows an output signal E24 output from the exclusive OR circuit 316 when the ODD area inversion signal E20 from the drive processor 36 is enabled for the discharge control unit of FIG. 3 shows an integrated voltage of the capacitor 126.
In this case, the duty pulse E19 shown in FIG. 26A is inverted for the periods of the second and third fields ODD1 and ODD2, and the finally obtained integrated voltage has a duty ratio of 0% with a duty ratio of 50%. It is possible to obtain a duty ratio measurement voltage that has changed to the minus side by an amount increased by 50%.
[0160]
In FIGS. 26C and 26D, the case where the duty ratio is increased is taken as an example. However, when the duty ratio is smaller than 50%, the finally obtained measured voltage is on the plus side. It becomes the measured voltage. With such a measurement function, the drive processor 30 can actually measure the percentage of the duty ratio of the duty pulse E19 output from the duty pulse generation circuit 120.
(4) Duty ratio delay adjustment
FIG. 27 shows an embodiment of the shifter 108 shown in FIG. The shifter 108 includes D-FFs 300, 302, 304 and a selection circuit 306. The three D-FFs 300, 302, 304 form a shift register by direct connection. The first stage D-FF receives a bit 1 output from the PLL counter 106 provided in the preceding stage, that is, a frequency-divided pulse obtained by dividing the frequency of the PLL clock E0 of 20 MHz by half.
[0161]
To the D-FFs 300, 302, 304, a PLL clock E0 is supplied as a shift clock. When the oscillation frequency of the PLL clock E0 is 20 MHz, the clock cycle 1τ is 50 nsec. The selection circuit 306 receives the bit 1 output of the PLL counter and the output signals E12, E13, E15 of the D-FFs 300, 302, 304 constituting the shift register. The output of bit 1 of the PLL counter is shown as signal E15.
[0162]
The selection circuit 306 receives the selection signal E11 for delay control determined based on the measurement result of the duty ratio in the drive processor 30, selects one of the inputs, and sets a reference to the master clock generation circuit 110. Output as clock.
FIG. 28 shows the delay adjustment by the shifter 108 of FIG. FIG. 28A shows the PLL clock E0. In the case of 20 MHz, 1τ is 50 nsec. The output of the PLL counter bit 1 in FIG. 28B is a pulse obtained by dividing the PLL clock E0 by half. This bit 1 output is directly supplied to the selection circuit 306 as shown by a signal E15 in FIG. 28 (F), and in this case, the delay amount is 0 ns.
[0163]
FIG. 28C shows the output signal E12 of the D-FF 300, which is a signal delayed by the period 1τ of the PLL clock E0, that is, by 50 nsec. FIG. 28D shows the output signal E13 of the second stage D-FF 302, which is a signal delayed by 100 nsec. Further, FIG. 28E shows an output signal E14 of the third stage D-FF 304, which is a signal delayed by 150 nsec.
[0164]
As described above, in the shifter 108 of FIG. 27, a digital delay amount having a delay time of 0, 50, 100, or 150 nsec is given to the PLL clock E0. Here, the delay amount digitally set by the shifter 108 is τd1.
FIG. 29 shows an embodiment of the variable delay circuit 114 of FIG. 29, the variable delay circuit 114 includes eight delay elements 308-1 to 308-8 and eight selection circuits 310-1 to 310-8. Each of the delay elements 309-1 to 308-8 has two inputs to the input stages of the selection circuits 310-1 to 310-8: a direct connection from the preceding stage and a path via the delay elements 308-1 to 308-8. Connect.
[0165]
Therefore, by selecting any one of the inputs by the selection circuits 310-1 to 310-8, a necessary number of delay elements can be connected in series from the input stage to the output stage. Each of the selection circuits 310-1 to 310-8 is controlled by a selection signal E17 from the drive processor 30. As the delay elements 308-1 to 308-8, for example, six delay elements 308-1 to 308-6 having a delay time of 12 nsec are used, and two delay elements 308-7 and 308-8 having a delay time of 5 nsec. Use things.
[0166]
The selection signal E17 from the drive processor 30 is an 8-bit signal b7 to b0 corresponding to the delay elements 308-1 to 308-8, and the bit signals b0 to b7 in the order of the selection circuits 310-1 to 310-8. You are typing. When each bit of the bit signals b0 to b7 is at the H level (bit 1), the selection circuits 310-1 to 310-8 select the lines from the delay elements 308-1 to 308-8. Conversely, when the bit signals b0 to b7 are at L level (bit 0), a line that bypasses the delay elements 308-1 to 308-8 is selected.
[0167]
The relation of the selection delay time to the bits b0 to b7 of the selection signal E17 from the drive processor 30 is as shown in the table of FIG. In response to such an 8-bit selection signal E17, the drive processor 30 generates 256 types of delay times τ0 to τ255 from table numbers I = 0 to 255 shown in FIG. Can be set.
[0168]
Here, the table number I = 0 is a case where the delay time τ0 = 0 nsec and there is no delay amount, and the delay time τ255 of I = 255 is 82 nsec which gives the maximum delay amount. Note that the delay times τ0 to τ255 are not arranged according to the magnitude relation of the delay times, and the selection of the optimum delay time is determined by repeating the setting of the delay time and the measurement of the duty ratio. In addition, the respective delay times shown in FIGS. 31 and 32 actually have a certain degree of variation, and these show only ideal design values.
[0169]
FIG. 30 shows a delay operation by the variable delay circuit 114 shown in FIG. The variable delay circuit 114 delays the zero cross detection signal E16 obtained from the zero cross detection circuit 112. The zero-crossing detection signal E16 gives a duty pulse reset timing in the duty pulse generation circuit 120, and thus delays the reset timing.
[0170]
30A shows the zero-crossing detection signal E16 input from the zero-crossing detection circuit 112. An arbitrary delay time τb2 is set by the selection signal E17 from the drive processor 30, and the final stage selection circuit 310-8 The delay output signal E18 is obtained.
FIG. 33 shows a duty pulse delay adjusting operation by the shifter 108 of FIG. 27 and the variable delay circuit 114 of FIG. FIG. 33A shows the rising timing of the PLL clock E10. On the other hand, it is assumed that the duty pulse before correction in FIG. 33B exceeds the duty ratio of 50% at 4τ. The duty ratio of this duty pulse is obtained as an integrated voltage of the capacitor 126 by the integration circuit 124 by inverting the second and third fields ODD1 and ODD2 of the duty pulse as shown in FIG. The delay amount that is taken into the processor 30 and needs to be adjusted is determined. For example, in the case of FIG. 33B, it is necessary to reduce the duty of Δτd exceeding 4τ in order to make the duty 50%.
[0171]
In this case, the drive processor 30 determines the delay amount of the PLL clock E10 in units of 50 nsec with respect to the shifter 108 and the delay amount τd2 of the zero-cross detection timing by the variable delay circuit 114 in order to realize the delay amount Δτd that requires adjustment. That is,
Δτd−τd1 + τd2 = 100nsec
The values of the set delay amounts τd1 and τd2 are determined so that
[0172]
FIG. 33C shows the setting of τd1 = 100 nsec for the shifter 108 and the delay setting of τd2 of the zero-cross detection timing for the variable delay circuit 114 shown in FIG. 38D. As a result, a corrected duty pulse corrected to a duty ratio of 50% shown in FIG. 38E can be obtained from the duty pulse generation circuit 120.
[0173]
The flowchart of FIG. 34 shows the duty adjustment processing by the drive processor 30. In FIG. 34, first, in step S1, the duty ratio is measured by inverting the second and third fields ODD1 and ODD2 while the servo head 18 is on-track on an appropriate target cylinder. If the measured duty ratio is 50% in step S2, the process ends without performing the adjustment process.
[0174]
If the duty ratio does not coincide with 50%, based on the measured duty ratio, a delay time τd1 for decreasing the duty ratio and a delay time τd2 for increasing the duty ratio are calculated in step S3, and the shifter 108 and the variable delay circuit 114 are set in steps S4 and S5, and the process returns to step S1 to measure the duty.
[0175]
The above processing of steps S1 to S5 is repeated until a duty ratio of 50% is obtained in step S2. This duty ratio adjustment processing is performed at the time of initialization processing after power-on start, as shown in step S4 of the flowchart of FIG.
FIG. 35 shows, as a subroutine, a process of setting the delay time τd2 for the variable delay circuit 114 performed in step S4 of FIG. In this subroutine, the table information shown in FIG. 32 is used.
[0176]
35, first, in step S1, the table selection number I of the table shown in FIG. 32, the table number Ds of the finally determined delay time, and the delay time Dm obtained in the previous calculation are initialized to 0. I do. Next, in step S2, the determined delay time τd2 for the variable delay circuit 114 determined by the duty measurement is calculated by D₀Read as
[0177]
Subsequently, in step S3, the delay time Di is calculated from the combination of the delay elements specified by the initialized table selection number I = 0. In this embodiment, since the delay time is previously stored as table information as shown in FIG. 32, only a table search is required. When the table is not used, the delay time DI is calculated from the combination of the delay elements specified by the table selection number I.
[0178]
Next, in step S4, the calculated delay time DI is greater than the previously calculated calculation delay time Dm, and the determined delay time D read in step S2.₀Check if it is less than. If this condition is satisfied, the calculation delay time Dm determined by the currently selected table selection number I is valid, so the process proceeds to step S5, where the currently obtained delay time DI is set as the calculation delay time Dm. , And the table number I is set to the determined delay time table number Ds. If the condition of step S4 is not satisfied, the process of step S5 is not performed, and the delay time of this table selection number is ignored. Subsequently, in step S6, the table selection number I is incremented by one, and the processing in steps S3 to S7 is repeated until the final table number I = 255 in step S7.
[0179]
By repeating such processing, the determined delay time D read in step S2 is obtained.₀= Τd2, the table number I having the delay time closest to τd2 can be determined. Finally, in step S8, the selection signal E17 based on the determined table number I is output to the variable delay circuit 114, and the delay time closest to the delay time τd2 is set. The selection signal E17 at this time is data expressing the decimal value of the table number I shown in FIG. 32 by 8 bits, and the selection of the delay element is uniquely determined by the bit correspondence.
5. Adjusting the integration circuit
In the integrating circuit 124 shown in FIG. 22, the amount of current flowing through the capacitor 126 is determined by the constant current sources 142 and 144, but is used for a constant current circuit that realizes the constant current sources 142 and 144. Variations occur in the resistance and the capacitance of the capacitor 126 during the manufacturing process.
[0180]
For this reason, a current must flow from both directions to the capacitor 126 based on a duty pulse with a duty ratio of 50% in the on-track state, and ideally the terminal voltage must be 0 V. Voltage is generated. The error voltage at the time of on-track of the capacitor 126 is taken into the drive processor 30 as a deviation amount from the cylinder center in the position detection signal, and the position detection accuracy is reduced.
[0181]
Therefore, in the disk device of the present invention, the error voltage of the capacitor 126 when the duty ratio is 50% is measured by the function of the integration circuit adjustment processing unit 86 provided in the drive processor 30 to control the head position. Is corrected by using the correct position data by subtracting the error from the position signal fetched from the AD converter 38.
[0182]
In measuring such an error voltage of the capacitor 126 during the on-track, the control signal E32 is output from the drive processor 30 to the selection circuit 118 shown in FIG. A read pulse corresponding to the zero-cross detection pulse is supplied to the duty pulse generation circuit 120, and the duty ratio of the duty pulse E19 is controlled by the drive processor 30, so that the error voltage in the integration circuit 124 when the duty ratio is 50% is measured. I do.
[0183]
Further, a duty pulse equivalent to the seek of ± 1 cylinder with respect to the target cylinder is generated in a pseudo manner via the selection circuit 118, and the position signal is measured by the integration circuit 124. The cylinder indicating the position detection data per cylinder Measure the gain. Therefore, without actually moving the servo head 18, the capacitor error voltage of the integration circuit 124 and the cylinder gain as position detection data indicating the head movement amount of one cylinder can be measured only by creating a pseudo duty pulse.
[0184]
FIG. 36 shows three types of read pulses output together with the phase servo pattern in the drive processor 30 via the selection circuit 118 to the duty pulse generation circuit 120 for measuring the integrated error voltage and the cylinder gain.
FIG. 36A shows a phase servo pattern on the servo surface, and the servo head 18 is on-track to the cylinder number 2. In such an on-track state, the master clock shown in FIG. The master clock sets a duty pulse at its rise. The duty pulse is reset by an on-track read pulse from the drive processor 30 via the selection circuit 118.
[0185]
This on-track read pulse is generated with a phase difference of 4τ with respect to the rise of the master clock, as shown in FIG. Thus, a duty pulse having a duty ratio of 50% shown in FIG. 35D can be artificially generated to operate the integration circuit 124.
FIG. 36F shows a +1 seek read pulse output from the drive processor 30 corresponding to when the servo head 18 on-tracking to the cylinder number shown in FIG. 36A seeks one cylinder in the plus direction. Is shown. This +1 seek read pulse corresponds to a read pulse when the servo head 18 moves to the cylinder number 3 in FIG. 35A, and is generated with a phase delay of 6τ with respect to the rising edge of the master clock.
[0186]
By this +1 seek read pulse, a duty pulse having a duty ratio of 75% in the first and fourth fields EVEN1 and EVEN2 and a duty ratio of 25% in the second and third fields ODD1 and ODD2 shown in FIG. Can occur.
Further, FIG. 36 (H) shows that a pulse corresponding to a read pulse obtained when the servo head 18 seeks one cylinder in the minus direction and moves to the cylinder number 1 from the on-track state is decelerated by the drive processor 30 by -1. Generated as a seek read pulse. This -1 seek read pulse is a pulse shifted by 2τ phase with respect to the rising edge of the master clock in the first and fourth fields EVEN1 and EVEN2, and shifted by 6τ phase with respect to the reference clock in the second and third fields ODD1 and ODD2. It is.
[0187]
As a result, a duty pulse having a duty ratio of 25% in the first and fourth fields EVEN1 and EVEN2 and a duty ratio of 75% in the second and third fields ODD1 and ODD2 shown in FIG. It can occur in a pseudo manner.
FIG. 37A shows an ideal case in which the on-track read pulse shown in FIG. 36C is generated by the drive processor 30 and the integration circuit 124 is operated with a pseudo duty ratio of 50%. The change 330 of the potential difference eventually becomes zero. However, in practice, when the integration circuit 124 is operated with a duty pulse having a duty ratio of 50% based on the on-track read pulse due to variations in resistance and capacitance, the characteristics indicated by the solid line and the characteristics indicated by the solid line in FIG. As indicated by 332, the potential difference of the capacitor 126 changes, and finally the offset voltage ΔV remains as an error voltage.
[0188]
Therefore, the drive processor 30 captures and holds the offset voltage ΔV by the AD converter 38, and removes the offset voltage ΔV from one data captured from the AD converter 38 in the subsequent head position control, and corrects the offset voltage ΔV. Produce data.
FIG. 38 shows a change in the potential difference of the capacitor 126 due to the generation of the +1 cylinder read pulse and the -1 cylinder read pulse for obtaining the cylinder gain. The characteristic 334 indicated by the solid line is a change when a pseudo +1 cylinder seek is performed. In this case, a potential difference of + V1 is obtained. A characteristic 336 indicated by a dotted line is a change in the potential difference when the cylinder cylinder seeks by -1 cylinder. In this case, a potential difference of -V2 is obtained.
[0189]
Then, the drive processor 30 obtains the change power of the potential difference + V1 during the +1 cylinder seek and the potential difference -V2 during the -1 cylinder seek as (V1 + V2), and divides this by two cylinders to obtain the potential difference per cylinder, that is, the position difference. The change in the signal is obtained as a cylinder gain.
The flowchart of FIG. 39 shows the integration circuit adjustment processing by the drive processor 30. First, in step S1, the selection circuit 118 is switched to disconnect the servo head 18, and a pseudo read pulse can be supplied from the drive processor 30 to the duty pulse generation circuit 120.
[0190]
Subsequently, in step S2, the master clock with the phase number 0 is selected by the cylinder switching signal E30, and the master clock generation circuit 110 outputs the master clock as the master clock E10. Subsequently, in step S3, an on-track read pulse for generating a duty pulse of 50% in all fields is generated to create a pseudo on-track control state. Subsequently, in step S4, the integrated voltage obtained by the generation of the on-track read pulse is taken in, and the offset voltage ΔV is detected.
[0191]
After the detection, the integrated voltage correction data is created in step S5, and can be used for the subsequent correction processing. Next, the cylinder gain is measured by the processing of steps S6 to S11. First, in step S6, a read pulse for generating a duty pulse of +1 cylinder seek in which the duty ratio changes to 75%, 25%, 25%, and 75% is generated to create a pseudo +1 cylinder seek state, and in step S7, The integrated voltage V1 at that time is taken.
[0192]
Subsequently, in step S8, a read pulse for generating duty pulses of 25%, 75%, 75%, and 25% is generated to create a pseudo--1 cylinder seek state, and in step S9, the integration at that time is performed. The voltage V2 is taken. Subsequently, in step S10, the change voltage per cylinder is calculated as (V1 + V2) / 2 from the voltage change during the seek for two cylinders, that is, (V1 + V2). Finally, in step S11, the calculated voltage is stored as a cylinder gain, and the disconnection of the servo head is released.
[0193]
The adjustment processing of the integration circuit is also executed at the time of the initialization processing accompanying the power-on start of the disk device as shown in step S5 of FIG.
6. Position prediction including acceleration component
In the seek control in the disk device of the present invention using the phase servo information, since a track crossing pulse is not used unlike a conventional disk device using a two-phase servo pattern, a target speed is obtained in the speed control. For calculating the number of remaining cylinders up to the target cylinder, the next head movement position is predicted for each sampling cycle of position detection.
[0194]
Then, the remaining number of cylinders from the predicted head movement position to the target cylinder is obtained, and the target speed is obtained from the target speed pattern corresponding to the remaining cylinder number to perform speed control. With respect to the prediction of the head position in the speed control during the seek, only the speed prediction is performed in the conventional disk device.
FIG. 40 shows a conventional prediction of the head movement position using only the velocity component. Now sampling timing t_nSuppose that the head was at position 284. Also, the previous sampling time t_n-1It is assumed that the head is at the position 282. In this case, the moving speed of the head is obtained from the current head position 284 and the previous head position 282, and the next sampling time t_{n + 1}Is predicted.
[0195]
When the predicted position 286 is determined, the number of remaining cylinders up to the target cylinder is obtained. Therefore, a target speed corresponding to the target cylinder is determined by referring to the target speed pattern based on the remaining cylinder number, and the speed is controlled by setting the speed in the speed control unit. At the same time, since the phase servo information is repeated every four cylinders of cylinder numbers 0 to 3, the cylinder number 2 corresponding to the predicted position 286 is obtained, and the next sampling time t_{n + 1}Cylinder switching for selecting a master clock to be used for position detection based on the phase servo pattern in.
[0196]
However, in head speed control during seek, the target speed pattern is acceleration, constant speed, and deceleration. During acceleration and deceleration, the acceleration component at which the detected speed changes at each sampling time is calculated. Will have. For example, if FIG. 40 is accelerating, the sampling time t_{n + 1}It is assumed that the actual head position is at the position 288 with respect to the predicted position 286 at. This actual movement position 288 is a position exceeding four cylinders from the current position 284.
[0197]
Therefore, the sampling time t_{n + 1}Since the head position can be recognized only within a range of ± 2 cylinders around the predicted position 288 even in the actual head position 288, the same cylinder number as the actual position 288 one cylinder before the predicted position 286 is used. It is determined that the head has moved to the position 290 of No. 3.
Therefore, the sampling time t_{n + 1}At the next sampling time t at_{n + 2}Is significantly different from the position 294 from the actual head movement position 292, and at this point, the head position cannot be determined and a seek error occurs. Therefore, the present invention is characterized in that an acceleration component in addition to the velocity component is taken into the prediction of the next head position at each sampling time.
[0198]
FIG. 41 shows prediction of the head position in the disk device of the present invention in which the acceleration component added to the speed component is added. The sampling time t_n-1, T_nIs the same position as in FIG.
In FIG. 41, the sampling time t_nAssuming that the head is at the position 284, the number of cylinders indicating the head speed in the sampling cycle is obtained by subtracting the previous head position 282 from the current head position 284. That is, the head moving speed is defined as the number of moving cylinders per sampling cycle in position detection.
[0199]
Next sampling time t in this case_{n + 1}The predicted position based on only the velocity component at is a position 286, as in the case of FIG. That is, the next sampling time t depends on the velocity component._{n + 1}Is obtained, the number CLv of cylinders indicating the amount of head movement at. Further, in the present invention, the current sampling time t_nFrom the acceleration component at the next sampling time t_{n + 1}Calculate the number of cylinders CLa that is the amount of head movement due to acceleration at The number of cylinders CLa indicating the head movement amount due to the acceleration component is calculated based on, for example, a drive current supplied to the VCM 16 that drives the head.
[0200]
Specifically, the number of cylinders CLa indicating the head movement amount due to the acceleration component is
CLa = VCM command current value × acceleration correction coefficient
Asking. Here, the acceleration correction coefficient gives the number of moving cylinders in the sampling cycle per unit instruction current, and can be experimentally determined.
FIG. 42 shows a change during the speed control of the position correction amount CLa due to the acceleration component obtained by multiplying the VCM instruction current value by the acceleration correction coefficient. That is, the time period from t1 to t2 is an acceleration period, and the position correction amount CLa due to the acceleration is a positive change as shown in the characteristic 298-1. The section indicated by the characteristic 298-2 from the next time t2 to t3 is a constant speed section, and the position correction amount CLa based on the acceleration component is substantially zero. Further, the section indicated by the characteristic 298-3 from time t3 to t4 is a deceleration section, and the position correction amount CLa based on the deceleration acceleration component has a negative value.
[0201]
As a result, the sampling time t in FIG._{n + 1}As shown in (2), the head position 296 can be predicted, and the cylinder range in which the position can be detected with respect to the actual head position 288 can be correctly predicted. Of course, the next sampling time t_{n + 1}Since the actual position 288 is displaced from the predicted position 296, the predicted position 296 is changed to the actual position 288 and the next sampling time t_{n + 1}Is predicted.
[0202]
The flowchart of FIG. 43 shows seek control in the disk device of the present invention that performs position prediction including acceleration.
In FIG. 43, first, in step S1, a target cylinder address is set, and in step S2, speed control (coarse control) based on the target speed pattern is started. In step S3, the presence or absence of position detection based on the phase servo pattern is monitored, and position detection is performed at each sampling cycle. If the position can be detected, in step S4, the head moving speed is obtained by subtracting the previous position from the current position.
[0203]
Subsequently, in step S5, the detection position of the next head movement position is predicted. This prediction processing is performed including the velocity component and the acceleration component. Next, in step S6, the cylinder number of the target cylinder is recognized based on the predicted position, and the condition for switching the master clock is set. Subsequently, in step S7, it is checked whether the number of remaining cylinders is 0.5 cylinders before the target cylinder, and the processes in steps S2 to S7 are repeated until the number reaches 0.5 cylinders before the target cylinder.
[0204]
If it is determined that the head has moved 0.5 cylinders before the target cylinder, the process proceeds to step S8, where the speed control up to that point is switched to the fine control for pulling the head to the head position indicating the target cylinder. When the control is switched to the fine control, in step S9, it is monitored whether or not the target cylinder falls within a predetermined range of the on-track slice value. If the target cylinder falls within the range of the on-track slice value, the on-track signal is increased. The target cylinder position is recognized, and a series of seek processing ends.
[0205]
FIG. 44 shows details of the position prediction shown in step S5 of FIG. 43 as a subroutine. In the position prediction in FIG. 44, an example is taken in which the maximum head moving speed is within ± 2 cylinders for each sampling cycle. In FIG. 44, first, in step S1, the current position P_nIs the previous position P_n-1Check whether it is within ± 2 cylinders centered on. If it exceeds ± 2 cylinders, it is a runaway of the head, so the process proceeds to step S5 to perform an error detection process. If it is within ± 2 cylinders, the process proceeds to step S2, and the cylinder change number CLv from the head moving speed V already obtained to the next detection position is calculated.
[0206]
Subsequently, in step S3, the cylinder change number CLa up to the next detection position due to the acceleration is calculated. Finally, in step S4, the cylinder change number CLv based on the speed and the cylinder change number CLa based on the acceleration are calculated based on the current position P._nTo the next position P_{n + 1}Ask for.
7. Cylinder switching by seek speed
In the disk drive of the present invention in which the head position is detected using the phase servo pattern, since the phase servo pattern is repeatedly recorded every four cylinders, the first to fourth fields EVEN1, ODD1, ODD2, and EVEN2 are used. Position detection in the configured phase servo area can be performed only when the head movement speed does not exceed ± 2 cylinders around the target cylinder where the position detection is performed. Therefore, the head cannot be moved at such a speed that the passage speed of the phase servo area exceeds 4 cylinders, and high-speed seek cannot be performed.
[0207]
FIG. 45 shows how the head moves when the passing speed in the phase servo area is limited to ± 4 cylinders. Note that the head moving speed in this case is a value obtained by dividing the number of passing cylinders of the head viewed in the radial direction by the passing time width st of the servo area viewed in the circumferential direction, for example, +4 [CL / st]. Can be expressed in units. In the following description, the head passing speed is simply expressed by the number of cylinders.
[0208]
In FIG. 45, the cylinder position 215 where the head passes through the boundary point between the second and third fields ODD1 and ODD2 is detected from the phase servo pattern. Therefore, assuming that the detection position 215 is located at the cylinder number 0, the head position can be accurately detected if the passage speed is within the phase servo area which does not exceed the hatched area 214 of ± 2 cylinders around the cylinder position. Here, the cylinder in which the detection point 215 at which the head position is detected is defined as a center cylinder.
[0209]
In the case of FIG. 45, in the forward seek to the inner side where the cylinder address increases in the plus direction, as shown by the head movement locus 218, the phase servo area 214 for four cylinders is moved from the upper left corner to the lower right corner. Is the highest speed +4 cylinders. Conversely, for the reverse seek in the minus direction in which the cylinder address decreases, that is, in the outer direction, as shown in the velocity trajectory 220, the maximum seek speed -4 cylinders which passes from the upper right corner to the lower left corner of the phase servo area 214 for four cylinders as shown in FIG. Become.
[0210]
Therefore, if the seek speed is within the range of +4 cylinders to -4 cylinders, the position detection of the position 215 can be performed during the seek as in the case of the on-track to the center cylinder 216. The position of the center cylinder 216 during the seek is detected as a result of the position prediction shown in FIG. The master clock phase number corresponding to the cylinder number indicating the target cylinder in this case is as shown in the table of FIG. In other words, cylinder switching for selecting a master clock corresponding to a cylinder number is performed even during a seek, as in the case of on-track.
[0211]
FIG. 47 shows the master clock phase number in each field of the phase servo area when the head moving speed is within ± 4 cylinders as shown in FIG. 46, and is the same in all fields as in the case of on-track. Of the master clock is used naturally.
In a disk drive in which the head moving speed is limited within a range of ± 4 cylinders around the center cylinder at which the head position is detected during a seek, the present invention exceeds ± 4 cylinders. The head moving speed of the center cylinder can also be detected for the head moving speed.
[0212]
FIG. 48 shows cylinder switching when the maximum head movement speed in the forward direction is +6 cylinders. That is, in the conventional disk device, the same master clock is used for all the fields in the four fields constituting one phase servo area. However, this limits the seek speed to ± 4 cylinders. The present invention is characterized in that the cylinder switching is performed within the field of the phase servo area.
[0213]
FIG. 48 shows two-stage cylinder switching in which the master clock is switched in two stages in the phase servo area, divided into the first two fields and the second two fields. In FIG. 48, the first center cylinder 228 and the second center cylinder 230 are shifted by ± 1 cylinder with respect to the center cylinder 216 at the detection position 215 where the head position is detected, and the first field EVEN1 and the second field ODD1 are set. With regard to, cylinder switching of the master clock corresponding to the first center cylinder 228 is performed. For the third field ODD2 and the fourth field EVEN2 in the latter half, cylinder switching of the master clock corresponding to the second center cylinder 230 is performed. As a result, as for the forward seek in which the cylinder address increases, the head movement with the maximum speed of +6 cylinders can be realized as shown in the speed locus 232.
[0214]
On the other hand, as for the seek in the reverse direction in which the cylinder address decreases, the speed trajectory passing through the head detection position 215 is restricted to the range of ± 1 cylinder as shown by the speed trajectory 235, and the maximum speed is -2 cylinders. .
FIG. 49 shows the master clock phase number at the time of forward seek and the master clock phase number at the time of reverse seek for the center cylinder 216 having the head detection position 215 when the seek speed of +6 cylinders to -2 cylinders of FIG. 48 is enabled. Is shown. In the first half of the first and second fields EVEN1 and ODD1, and in the second half of the third and fourth fields ODD2 and EVEN2, cylinder switching as master clocks having different phase numbers is performed in two stages.
[0215]
FIG. 50 shows cylinder switching when the maximum speed in the forward direction is +7 cylinders. In this case, the cylinder switching is performed stepwise for each of the first to fourth fields. In other words, the first center cylinder 246, the second center cylinder 248, the third center cylinder 250, and the fourth center cylinder are shifted from the center cylinder 216 having the detection position 215 by one cylinder in the order of the first field to the fourth field. The cylinder 252 is set. The third center cylinder 250 is the same as the center cylinder 216.
As a result, regions 238, 240, 242, and 244 of ± 2 cylinders are set for the respective center cylinders 246, 248, 250, and 252. At this time, the maximum seek speed in the forward direction at which the cylinder address increases is +7 cylinders as indicated by the speed locus 254. On the other hand, the reverse seek in the minus direction in which the cylinder address decreases is restricted to -1 cylinder.
[0216]
FIG. 51 shows the master clock phase number in each field in the cylinder switching of FIG. 56 corresponding to the cylinder number of the center cylinder having the head detection position 215. In any case, cylinder switching in which phase numbers of different master clocks are selected step by step in the first to fourth fields is performed.
FIG. 52 shows cylinder switching when the maximum speed in the forward direction is +10 cylinders. The cylinder switching in FIG. 52 is performed for each field similarly to FIG. 50, and the cylinder switching for each field is performed every other cylinder in FIG. Has increased to two cylinders.
[0217]
That is, the first center cylinder 268, the second center cylinder 270, the third center cylinder 272, and the fourth center cylinder 274 are set so as to be spaced by two cylinders around the center cylinder 216 having the head detection position 215. . For each of the center cylinders 268, 270, 272 and 274, areas 260, 262, 264 and 266 within a range of ± 2 cylinders are set.
[0218]
Therefore, the maximum speed in the forward direction is +10 cylinders as shown by the speed locus 276. On the other hand, the minimum cylinder speed of the forward seek is restricted with respect to the head maximum speed, and as shown by the speed locus 278, it becomes +4 cylinders. Therefore, in the cylinder switching of FIG. 52, the head can be moved at a seek speed of +4 cylinders to 10 cylinders.
[0219]
FIG. 53 shows combinations of the phase numbers of the master clock used for the cylinder switching in FIG. 52 in correspondence with the center cylinder number of the center cylinder 216 to which the head detection position 215 belongs.
FIG. 54 shows the cylinder movement of FIG. 45 as the first speed (1ST), the cylinder switching of FIG. 48 as the second speed (2ND), the cylinder switching of FIG. 50 as the third speed (3RD), and the cylinder switching of FIG. As a fourth speed (4TH), a kind of seek speed shift pattern is shown.
[0220]
Since the shift pattern can be realized by switching the cylinders in this manner, an arbitrary seek speed can be handled by detecting the head moving speed and switching the cylinders to select a required speed range. This is a function similar to the automatic transmission used in automobiles.
The flowchart of FIG. 55 shows a cylinder switching process using two-stage speed switching of first speed (1ST) and second speed (2ND) shown in FIG.
[0221]
In FIG. 55, first, the speed V is read in step S1. This speed V is obtained from the difference between the current head position and the previous head position. Then, the process proceeds to a step S2, wherein it is checked whether or not the speed V is within a range of ± 4 cylinders. If it is within the range of ± 4 cylinders, the process proceeds to step S3, and based on the cylinder number corresponding to the predicted position of the head to be detected next, the master clock phase number is selected from the so-called first speed table shown in FIG. Decide the pattern.
[0222]
On the other hand, if the speed V exceeds ± 4 cylinders in step S2, the process proceeds to step S4, where it is checked whether or not the speed is in the range of -2 to +6 cylinders. A phase switching pattern consisting of a combination of the corresponding master clock phase numbers is selected from the so-called second speed table of FIG. 49 corresponding to the predicted cylinder numbers.
[0223]
In FIG. 52, the maximum speed is set to +10 cylinders. However, the maximum speed can be increased by further increasing the cylinder interval between the center cylinders in each field to 3 cylinders or 4 cylinders.
8. Phase servo pattern on data surface
In the disk drive of the present invention, a phase servo pattern equivalent to the phase servo pattern on the servo surface is recorded on a specific cylinder on the data surface, and the head position is read from the read head (MR head) provided on the data head. That can be detected.
[0224]
FIG. 56 shows a frame configuration of a phase servo pattern written in a specific cylinder on the data surface. In FIG. 56, a servo area 340 for one rotation of the disk, which is developed linearly, is provided in a specific cylinder in the outer guard band area OGB1 and a specific cylinder in the inner guard band area IGB1 on the data surface. .
[0225]
The servo area 340 for one rotation is divided into 216 areas to constitute 216 data plane servo frames 350, similarly to the servo plane shown in FIG. The data surface servo frame 350 includes an unused area 360 and a servo pattern section 370 as shown in an enlarged manner.
The servo pattern section 370 has the same size as the servo pattern section 164 on the data surface in FIG. 10, and when the count value of the reference clock is set to 0 at the beginning of the servo frame, the servo pattern section 370 has a count value of 1268 to 1512. It becomes. In the servo pattern section 370, phase servo patterns shown separately in FIGS. 56 and 57 are recorded.
[0226]
56 and 57, the phase servo pattern is divided into a first field 372, a second field 374, a third field 376, and a fourth field 378. In the first to fourth fields, the first field 372 is called EVEN1, the second field 374 is called ODD1, the third field 376 is called ODD2, and the fourth field 378 is called EVEN2, similarly to the servo surface phase servo area. The first to fourth fields have a length of 4τ × 10 corresponding to four periods of the reference clock except for the unused area.
[0227]
In the phase servo pattern, the first field and the fourth field have the same phase servo pattern, the second field and the third field have the same phase servo pattern, and the first, fourth and second fields have the same phase servo pattern. The pattern is opposite in phase. This point is the same as the phase servo pattern on the servo surface. The difference from the servo surface phase servo pattern is that, as shown in FIG. 59, between the phase patterns of the first field 372 (EVEN1) and the fourth field 378 (EVEN2) in the radial direction of 0.25 cylinders. The point is that the position is shifted. This point has the same relationship between the second field 374 (ODD1) and the third field 376 (ODD2) shown in FIG.
[0228]
Further, as shown in FIGS. 57 and 58, the data surface servo pattern is recorded in a range of ± 2.5 cylinders centering on the target cylinder 0 cylinder, and in a region exceeding ± 1.5 cylinders. In order to prevent the head position from being detected, a pattern having no phase shift is recorded. Therefore, the number of cylinders that can be the head position is limited to three cylinders in the data surface, whereas the four cylinders are the head position possible range in the servo surface.
[0229]
The point that the number of cylinders at which the head position can be detected is limited to three cylinders is that the servo information recorded on the data surface is intended to measure an offset while on-tracking to, for example, cylinder number 0 as a target cylinder. Therefore, it is sufficient to provide a head detection range of about ± 1.5 cylinders. The error of the head position exceeding this range is originally covered by the detection of the head position based on the phase servo information on the servo surface.
[0230]
As shown in FIGS. 59 and 60, the reason why the phase servo pattern is recorded in the first field and the fourth field and the second field and the third field shifted by 0.25 cylinder in the radial direction is that the servo head This is because the core width of the read head using the MR head provided on the data head 20 is smaller than that of the servo head 18 and the same phase servo pattern as that of the servo head 18 prevents the formation of a dead zone in position detection. This relationship is described as follows.
[0231]
FIG. 61 shows the relationship between the amount of head movement and the amount of detection when the phase servo pattern on the servo surface is read by the servo head. FIG. 61 shows a boundary portion between the second field ODD1 and the third field ODD2 in the servo frame on the servo surface 38, and the core width W1 of the servo head 18 is substantially one cylinder. For example, when the track pitch is 7.5 μm, the core width W1 of the servo head 18 is about 7 μm. For such a core width W1 of the servo head 18, a servo pattern is recorded on the servo surface 380 at a 0.5 cylinder pitch in the radial direction. Since the servo head 18 always obtains a read signal while straddling two servo patterns, the detected amount changes linearly with respect to the head movement amount as shown by a characteristic 382.
[0232]
FIG. 62 shows a case where exactly the same servo pattern as the servo surface 380 of FIG. 61 is recorded on the data surface 384. Since the read head 410 used for servo reading of the data surface 384 uses an MR head, the core width W3 is smaller than that of the servo head 18, for example, W3 = 3 μm, which is half or less.
Therefore, when the same servo pattern as the servo surface is read by such a read head 410 having a small core width W3, the read head 410 completely enters the servo pattern having a 0.5 cylinder width, and the head position changes. However, dead zones 390, 392, and 394 in which the detected amount does not change at all are generated. Therefore, the relationship between the amount of movement of the head and the amount of detection is as shown by a characteristic 386, and the head position cannot be detected in accordance with the original characteristic 382 shown by the broken line.
[0233]
In order to solve this problem, in the present invention, as shown in FIG. 63, for example, the phase servo patterns of the second field ODD1 and the third field ODD2 are recorded while being shifted by 0.25 cylinder in the radial direction. As a result, even in the case of the read head 410 having a small core width W3, a dead zone in which the head continues to enter a specific phase servo pattern due to head movement does not occur. The detection amount can be obtained as shown by a linear characteristic 388. This point is the same between the first field EVEN1 and the fourth field EVEN2.
[0234]
As described above, in order to write the phase servo patterns shifted by 0.25 cylinders in the first and fourth fields EVEN1 and EVEN2 and the second and third fields ODD1 and ODD2 on the data surface, 16 types of phase patterns are required. Different write signals are required. That is, as shown in FIG. 57, the servo pattern in the first field 372 (EVEN1) and the second field 374 (ODD1) in the first half has a length of 0.5 cylinder in the radial direction, so that the servo surface Similarly, eight kinds of write signals having different phases shifted by 1τ are required. Further, the third field 376 (ODD2) in FIG. 57 and the fourth field 378 (EVEN2) in FIG. 58 are displaced in the radial direction by 0.25 cylinder, so that the phase is further different at the same write cylinder position. Eight types of write signals are required.
[0235]
Specifically, the first field EVEN1 and the second field ODD1 in the first half are shown in FIG.Synchronized with the rise of the reference clock in (A)Eight types of write signals of phase numbers 0, 2, 4, 6, 8, 10, 12, and 14 are used, and the third and fourth fields ODD2 and EVEN2 in the latter half are shown in FIG.Synchronized with the falling edge of the reference clock in (A)Eight types of write signals of phase numbers 1, 3, 5, 7, 9, 11, 13, 15 are used.
The above description is for the case where the number of cylinder repetitions of the servo information recorded on the servo surface is set to 4. However, when the number of cylinder repetitions is represented by N, which is a general expression, the data surface servo information writing means is: Generates 4N types of write pulses in which the reference clock is frequency-divided by 1 / N and whose phase is different from that of the reference clock by 0.25N cycles, and specified by the write cylinder from the write pulses The write pulse having a predetermined phase is selected and written as servo information in the servo area on the data surface.
[0236]
These 16 types of write signals having the phase numbers 0 to 15 are supplied from the master clock generation circuit 110 having the circuit configuration shown in FIG. 17 in the mode of writing servo information on the data surface.
FIG. 64 shows the phase number of the write signal when the phase servo pattern is written on the data surface shown in FIGS. 57 and 58 in the range of ± 2.5 cylinders in the range of ± 2.5 cylinders around cylinder number 0 as the target cylinder. Shown in cylinder units. Of these, the same pattern is repeated in an area exceeding ± 1.5 cylinders with respect to the cylinder position 0.00 as the target cylinder, and writing of effective phase servo information is provided within the range of ± 1.5 cylinders. .
[0237]
FIG. 64 shows a specific write operation in the on-track state to the target cylinder on the data surface based on the phase servo information on the servo surface, for example, seeking at −2.5 cylinders and 0.25 cylinder units from the offset position. The servo pattern is written at the timing of each servo frame while selecting the phase number of the servo write signal shown for each of the first to fourth fields.
[0238]
FIG. 65 shows the selected phase number of the master clock based on the cylinder switching used when the phase servo pattern on the data surface shown in FIGS. 57 and 58 is read by the read head provided on the data head and the position is detected. Shown for cylinders. Of course, the target cylinder is the cylinder relative number 0 when the data surface servo is read, and the ± 1 cylinder on both sides does not need to be on-tracked. Only the phase number may be used.
[0239]
FIG. 66 shows a process of writing a servo pattern on the data surface by the disk device of the present invention. As shown in FIG. 6, this write process is performed on the servo surface at the final stage of the production process before product shipment. This is performed after the writing of the phase servo information is completed and the automatic adjustment of the servo system is completed.
Referring to FIG. 66, first, in step S1, a seek to a data surface writing start cylinder, that is, a target cylinder is performed based on the phase information of the servo surface. The writing start cylinder on this data surface is a specific cylinder in the outer guard band area OGB1 for writing the phase servo information on the data surface for measuring the thermal offset.
[0240]
In addition, since the offset measurement on the inner side is also required for the yaw angle offset measurement, when the writing in the outer guard band area OGB1 is completed, the specific cylinder in the inner guard band area IGB1 is designated as the writing cylinder. . When the seek for the write start cylinder is completed in step S2, for example, the initial write pattern is selected from FIG. 64 in a state where the offset seek is performed for +2.5 cylinders or -2.5 cylinders.
[0241]
Next, in step S4, in synchronization with the servo state of the servo surface, the master clock of the selected write pattern phase number is selected, and the phase servo pattern is written for each phase servo area in the servo frame. Subsequently, in step S5, it is checked whether the writing of all the patterns has been completed. In step S6, the cylinder is offset-seeked for 0.5 cylinder, and the process returns to step S2 again. In step S3, the next write pattern is selected. Similarly, the servo pattern is written. The above processing is repeated until all patterns are written in step S5.
9. Read / write with phase servo pattern on data surface
As shown in FIG. 2, a relatively large disk device is composed of a disk enclosure 10 composed of a mechanical part including a head and a motor, and a drive controller 12 composed of a printed circuit board for controlling the disk enclosure. One drive module is integrated. Then, one disk system constitutes one device by combining a plurality of drive modules with an upper disk control unit.
[0242]
Such a magnetic disk storage device is configured using the printed circuit board of the disk enclosure 10 and the drive controller 12 as a minimum unit. However, even if the disk drive is of the same model, there are various types of the disk enclosure 10 and the drive controller 12. It must be a combination of the disk enclosure 10 and the drive controller 12.
[0243]
Therefore, in a conventional disk device, a dip switch or the like is provided on a printed circuit board on which the drive controller 12 is mounted so that the combination operation can be performed normally when the disk enclosure 10 to be combined is changed. However, in this case, it is necessary to artificially determine the board of the disk enclosure 10 and operate the DIP switch on the drive controller 12 side, and there is a risk of erroneous setting.
[0244]
Therefore, in the disk device of the present invention, an appropriate drive controller 12 is combined at the stage of completing the assembling of the disk enclosure 10 so that a specific cylinder on the data surface, for example, from the cylinder address 0 to the outer outer guard band area OGB1. The data necessary for the combination of the disk enclosure substrate and the like is written in the empty cylinder between the two using the phase servo information. Then, when the drive controller 12 is combined, the information of the disk enclosure is read by the drive controller 12 so that various settings associated with the combination can be automatically performed.
[0245]
The data writing to the specific cylinder on the data surface using the phase servo pattern is executed by the drive processor 30 using the function of the position signal creating circuit 36 shown in FIG.
FIG. 67 shows a phase servo pattern corresponding to data bit 0 recorded on the data surface and its read waveform. FIG. 68 shows a phase servo pattern for the data surface corresponding to data bit 1 and its read waveform.
[0246]
The phase servo pattern indicating the data bit 0 in FIG. 67A is a servo pattern corresponding to a servo pattern shifted by +1 cylinder on the normal servo surface with respect to the recording pattern of the cylinder number 0 serving as the target cylinder. Is commonly recorded in the range of ± 1.5 cylinders. Therefore, the read pulse shown in FIG. 67B is obtained for the first to fourth fields EVEN1, ODD1, ODD2, EVEN2.
[0247]
On the other hand, the master clock in FIG. 67C is a reference clock corresponding to cylinder number 0. Therefore, the duty pulse obtained by being set at the rise of the master clock and reset at the rise of the read pulse is as shown in FIG. 67 (D).
That is, in the case of the data bit 0, the duty pulse has a duty ratio of 25% in the first and fourth fields EVEN1 and EVEN2, and has a duty ratio of 75% in the second and third fields ODD1.2. This duty pulse is extracted by the data window signal shown in FIG. 67 (E), and the integration operation by the integration circuit yields an integrated voltage indicating −V data bit 0 shown in FIG. 67 (F).
[0248]
The phase servo pattern corresponding to data bit 1 in FIG. 68 (A) is -1 cylinder seek relative to the position of the original servo pattern for the target cylinder of cylinder number 0, contrary to the case of data bit 0 in FIG. The same phase servo pattern is recorded over a range of ± 0.5 cylinders at a position delayed by 1τ and a phase corresponding to the case.
[0249]
Therefore, the read pulse shown in FIG. 68 (B) is obtained, and the master clock in FIG. 68 (C) is set by setting the cylinder number 0 by the master clock corresponding to the target cylinder and reset by the read pulse. The duty pulse shown is obtained. That is, the duty pulse has a duty ratio of 75% in the first and fourth fields EVEN1 and EVEN2 and a duty ratio of 25% in the second and third fields ODD1 and EDD2, which is opposite to the case of the data bit 0. . Therefore, the integrated voltage based on the duty pulse extracted by the data window signal of FIG. 68 (E) finally becomes + V as shown in FIG. 68 (F).
[0250]
The flowchart of FIG. 69 shows a process of writing the phase servo pattern on the data surface corresponding to the data bits 0 and 1 shown in FIGS. 67 (A) and 68 (A).
Here, as shown in FIG. 8, the write operation of the data head 20 by the write head 400 according to the phase number pattern from the master clock creation circuit 110 is performed by the write operation of the servo head 18 as shown in FIG. Since it can be performed in parallel with the on-track control based on the head position signal by the read signal, the phase servo pattern indicating the data bit 0 or 1 can be written to all the servo frames of the specific cylinder on the data surface. However, the read processing of the data surface phase servo pattern uses the same position signal generation circuit as the on-track control based on the read signal of the servo head 18 and the restoration of the data bits 0 and 1 by the read signal from the read head 410 of the data head 20. At 36, time division processing must be performed.
[0251]
For example, when reading every 12 frames, the first time is read as frames 0, 13, 26,..., The second time is read as frames 2, 13, 27,. Finally, the frames are read as frames 12, 26, 38,. As a result, all of the 216 frames can be read.
FIG. 70 shows data based on the integrated voltage from the position signal generation circuit 36 for 216 servo frames per cylinder in a read process performed by switching between the servo head 18 and the read head 410 provided in the data head 20. This shows bit restoration, that is, read processing.
[0252]
Referring to FIG. 70, first, an integrated voltage is read in response to an interrupt based on a predetermined data surface servo frame, and it is checked in step S2 whether the voltage is a negative voltage equal to or more than a specified value. If the voltage is equal to or more than the specified value, the process proceeds to step S3, and the bit 0 is restored. On the other hand, if the voltage is not a negative voltage equal to or more than the specified value, the process proceeds to step S4, and it is checked whether the voltage is a positive voltage equal to or more than the specified value.
[0253]
If the positive voltage is equal to or higher than the specified value, the bit 1 is restored in step S5. The above processing is repeated until all the bits are read in step S6. In the above embodiment, 16 servo frames per cylinder on the data surface, that is, 16-bit data reading / writing are taken as an example. However, if it is desired to further increase the data amount, the number of cylinders to be written may be increased. .
10. Measuring and correcting yaw offset
In a magnetic disk drive using a small MR head as the read head of the data head, as shown in FIG. 71, the data head 20 is positioned at the innermost position 20 'and the data head 20 is positioned at the outermost position 22'. In this case, a position shift occurs with respect to the on-track state of the write head 400. This is called a yaw angle offset. That is, the data head 20 is provided with the inner maximum yaw angle α1 with respect to the neutral position of the rotation center 430 of the head arm 402 when the data head 20 is moved to the inner side end and the inner maximum yaw angle α2 in the opposite direction. Between the write head 400 and the read head 410.
[0254]
FIG. 72 is an enlarged view of the data head 20, in which a write head 400 using a magnetic head and a read head 410 using an MR head are provided integrally. The core width W2 of the write head 400 is about 6 μm, for example, when the track pitch is 7.5 μm. On the other hand, the core width W3 of the read head 410 using the MR head is 3 μm or less, which is half or less thereof. Although the centers of the write heads 410 are matched in design, they actually have a mechanical offset ΔW due to positional deviation.
[0255]
Writing data in the user area on the data surface is performed by on-track control of the write head 400 based on phase servo information on the servo surface. Therefore, when it is desired to switch to the read operation by the read head 410, the read operation is performed at a position shifted from the track center by a mechanical offset ΔW.
In addition to such a mechanical offset ΔW between the write head 400 and the read head 410 in the data head 20, as shown in FIG. 71, a different offset for each yaw angle due to the VCM 16 is provided between the write head 400 and the read head 410. Occurs.
[0256]
FIG. 73A shows the yaw angle offset of the read head 410 with respect to the track center 460 at the inner maximum yaw angle α1 in FIG. FIG. 72B shows the yaw angle offset of the read head 410 with respect to the track center 480 at the outer maximum yaw angle α2 in FIG.
As is apparent from a comparison between FIGS. 72A and 72B, a yaw angle offset in the opposite direction is generated on the innermost side and the outermost side with respect to the yaw angle offset 0 at the center position 402 in FIG.
[0257]
FIG. 74 shows an offset ΔW at the maximum yaw angle of the inner side on the left side and the outer side on the right side with the center cylinder address at which the yaw angle offset becomes 0 °, for example, the cylinder address 2000 as the origin._inAnd ΔW_outIs plotted. When the innermost and outermost head positions 424, 422 are determined, the offset between them can be estimated by a straight line 428 connecting them.
[0258]
Here, the yaw angle at the center position is 0 °, the outer side is plus, the inner side is minus, and the mechanical offset ΔW at the yaw angle of 0 ° is deducted, and the maximum value of the yaw angle offset on the inner side and the outer side is defined as As can be seen, the outer side has a relatively positive offset, and the inner side has a relatively negative offset.
Therefore, in the disk drive of the present invention, as shown in FIGS. 56 to 58, a phase servo pattern is previously assigned to a specific empty cylinder in the inner guard band area IGB1 and a specific empty cylinder in the outer guard band area OGB1 on the data surface. For example, as shown in FIG. 6, the correction table of the yaw angle offset table is created by performing the yaw angle offset processing at the final stage of the assembly before the product is shipped, as shown in FIG.
[0259]
The flowchart of FIG. 75 shows the yaw angle offset measurement processing by the disk device of the present invention.
In FIG. 75, first, in step S1, the data head 20 is sought to a specific cylinder in the inner guard band area IGB on the innermost side of the data surface based on the phase servo pattern on the data surface. Subsequently, the process proceeds to step S2, in which the inner yaw angle offset ΔW is shifted from the data surface phase servo pattern while switching from the servo head 18 to the read head 410 of the data head 20 at a constant servo frame interval._inIs measured.
[0260]
In the measurement process of the data surface phase servo pattern, for example, every time 13 servo surface servo frames out of 216 servo frames per cylinder are processed, switching to data surface servo frame reading is performed, and 16 points per cylinder are read. The yaw angle offset is measured, and finally, the yaw angle offset ΔW is calculated as an average value._inTo determine.
[0261]
The inner side yaw angle offset processing of step S2 is performed for all the heads while switching the data heads in step S4. After the measurement process of the inner yaw angle offset in steps S1 to S4 is completed, the process proceeds to step S5, where the phase of the outer guard band region OGB1 located at the outermost position on the data surface is moved to the data head 20 based on the phase servo pattern on the data surface. Seek to the specific cylinder where the servo pattern is being written.
[0262]
When the seek operation is completed, the process proceeds to step S6. As in the case of step S2, the servo head 18 is switched to the read head 410 at a constant servo frame interval, for example, from the phase servo pattern of 16 data plane servo frames per cylinder to the outer side. The yaw angle offset is measured as the average value of the yaw angle offset ΔW._outTo determine. The process of step S6 is repeated while switching the head in step S8, until all the heads are completed in step S7.
[0263]
When the measurement of the yaw angle offsets on the inner and outer sides is completed, in step S9, the innermost and outermost yaw angle offsets ΔW output for each data head._in, ΔW_out74, the yaw angle offset at each cylinder position is calculated, and a yaw angle offset table used for correction is created, as shown in FIG. FIG. 76 shows an example of a yaw angle offset correction table created by the yaw angle offset measurement processing of FIG. This correction table is, for example, a table in which one yaw angle offset is obtained for every 50 cylinder addresses.
[0264]
FIG. 77 shows a yaw angle offset correction performed in a read process during operation in which the disk device of the present invention is incorporated in a system.
In FIG. 77, first, seek is performed to a target cylinder in step S1, and a read operation is performed in step S2. In this read operation, if a read error is determined in step S3, the yaw angle offset corresponding to the address of the target cylinder is read in step S5 with reference to the yaw angle offset table shown in FIG. Position the data head to compensate for the angular offset.
[0265]
That is, the read error in step S3 occurs when the read waveform is degraded due to a large deviation of the read head from the recording pattern written by the write head due to the yaw angle. The position of the read head is corrected to the cylinder center side by performing the yaw angle offset, and the read operation is retried to make the read operation successful.
[0266]
If there is no read error in step S3, a normal end response is returned as a status response in step S4, and the process returns to the main processing. As described above, by preparing the correction table by measuring the yaw angle offset in advance, the read error can be reliably recovered by the yaw angle offset correction when the read error occurs.
11. Center value adjustment of VCM DA converter
FIG. 78 shows a drive circuit section of the VCM 16 provided in the drive controller 12 of the disk drive of the present invention. The current instruction data from the drive processor 30 to the VCM 16 is converted into an analog signal by the DA converter 40, and is converted into a drive current by the driver circuit 42 and supplied.
[0267]
Here, in the current control of the VCM 16, when the current instruction data by the drive processor 30 is output as digital data of several bits, a reference voltage generation circuit is provided to the driver circuit 42 in order to give the instruction data a positive / negative sign and an operation amount. 414 is provided to generate a drive voltage having a polarity and an operation amount by looking at the converted voltage from the DA converter 40 around the reference voltage, and drive the VCM 16 with positive and negative drive currents around the zero point.
[0268]
Ideally, the converted voltage when the command current 0 is instructed to the DA converter 40 and the reference voltage generated by the reference voltage generation circuit 414 match, and the drive current of the driver circuit 42 becomes zero. However, among the components of the DA converter 40 and the reference voltage generation circuit 414, there is a variation in accuracy such as a resistance value and a constant. For this reason, an error occurs between the center instruction voltage converted and output by the DA converter 40 and the reference voltage generated by the reference voltage generation circuit 414, and an unnecessary current corresponding to the error flows through the VCM 16, so-called center offset. And adversely affect the servo control.
[0269]
In order to solve this problem, in the disk drive of the present invention, as shown in step S2 of the flowchart of FIG. An error from the reference voltage by the creation circuit 414 is measured, and servo control in which the error is corrected is performed in the read / write processing after the initialization.
[0270]
In order to measure the error between the center instruction voltage and the reference voltage, in the embodiment of FIG. 78, a comparison circuit 416 for newly comparing the conversion voltage of the DA converter 40 with the reference voltage of the reference voltage generation circuit 414 is provided. The error is measured by the DAC center value adjustment unit 80 implemented as a function of the drive processor 30 using the comparison output of the circuit 416, and correction based on the measurement error is performed in a normal read / write operation.
[0271]
FIG. 79 shows a state of the measurement processing by the VCM DAC center value adjustment unit 80 of FIG. This measurement process is divided into mode 1 in the first half and mode 2 in the second half. In the measurement processing in mode 1, the lower limit center indicator V, which is a predetermined amount lower than the predetermined center instruction data for the DA converter 40, is used._CLIs set, the indicated value is increased stepwise, and the output voltage of the DA converter 40 is increased as shown in the figure.
[0272]
First, the lower-limit center instruction voltage V of the DA converter 40 with respect to the reference voltage_CLIs low, the output of the comparison circuit 416 is at the L level. When the instruction value for the DA converter 40 is increased, the output of the comparison circuit 416 is inverted to the H level when the converted voltage exceeds the actual reference voltage, and the voltage V when inverted to the H level is obtained._C1Is held as the measured value. In the mode 1, the same processing is repeated, for example, four times, and the first center voltage V_C1Ask for.
[0273]
Next, the mode 2 measurement is started. In the measurement in mode 2, the center upper limit instruction data higher than the planned center instruction data is set in the DA converter 40, and the center upper limit instruction voltage V_CHAnd gradually reduce the conversion voltage. First, the center upper limit voltage V_CHSince the reference voltage is higher than the actual reference voltage, the comparison circuit 416 generates an H level output. When the converted voltage is lowered, the output of the comparison circuit 416 is inverted to the L level when the converted voltage falls below the reference voltage.
[0274]
Therefore, the voltage V at this time_C2As the second center upper limit voltage. In mode 2, as in mode 1, four measurement processes are performed, and the final measured voltage V_C2Ask for. After the measurement in the modes 1 and 2 is completed, the measurement voltage V in the mode 1_C1The measured voltage V of mode 2_C2And the voltage V divided by 2_C, The center instruction data for the DA converter 40 is obtained, and is stored in the drive processor 30 as the corrected DAC center instruction data.
[0275]
The measured converted voltage of the center instruction data of the DA converter 40 almost completely matches the reference voltage of the reference voltage generation circuit 414, and the center voltage can be set accurately. The current instruction data in the VCM 16 in the drive processor 30 is the measured center instruction voltage V_CThe data corresponding to the sign and the amount of operation are generated with the data corresponding to the zero as the zero point, and output to the DA converter 40.
[0276]
FIG. 80 shows the center value adjustment processing of the DA converter in FIG. In FIG. 80, steps S1 to S5 correspond to the processing shown in mode 1 of FIG. Steps S6 to S10 correspond to the mode 2 shown in FIG. Then, in step S11, the final center value V_CIs calculated using the average value of the DA converter 40, and in step S12, the center position of the DA converter 40 that matches the reference voltage is set in the drive processor 30.
[0277]
By measuring and correcting the error between the conversion voltage based on the center instruction data for the DA converter 40 and the reference voltage from the reference voltage generation circuit 414 that sets the zero operating point in the driver circuit 42, the error is measured. Accurate servo control can be performed.
12. Rezero operation
In the disk device of the present invention, as shown in step S3 in FIG. 7, the cylinder address is formed by positioning the head in the outer guard band area OGB1 at the stage of the initialization processing at the power-on start. A rezero operation is performed to set the counter value to a zero address as an initial value. However, since the absolute cylinder address is not known at the stage of the rezero operation, there is a problem in the speed control for seeking the head in the innermost contact start / stop area (CSS area) 60 to the outer guard band area. There is.
[0278]
That is, in the seek control of the present invention using the phase servo pattern, the speed is detected at each sampling cycle of the head position detection, and the speed control is performed while predicting the head position at the next sampling time. At the stage where the actual cylinder address has not been determined, there is an error in the target cylinder address for cylinder switching based on the predicted cylinder position, and a normal seek operation cannot be expected.
[0279]
Therefore, in the re-zero operation of the present invention, after the head is pushed away from the innermost contact start / stop area to the outer side by acceleration control and driven, the cylinder address is relatively set to 0 with the first obtained integrated voltage of zero. The target speed is determined and the speed control is performed while obtaining the number of remaining cylinders up to the target cylinder by position prediction by speed detection based on the cylinder address.
[0280]
Then, an absolute rezero operation of setting the absolute value of the cylinder address to 0 at the time when the guard band detection signal is obtained by the arrival of the head in the outer guard band area OGB1 is performed.
The flowchart of FIG. 81 shows the details of the rezero processing in the disk device of the present invention. First, in step S1, the head flying in the contact start / stop area is driven to be separated from the inner side to the outer side by supplying an acceleration current to the VCM 16. In this state, the phase number of the master clock by the cylinder switching is fixed to 0 in step S2.
[0281]
Subsequently, in step S3, the movement time T for four cylinders is measured from the change in the integrated voltage. Specifically, the movement of the four cylinders changes the integrated voltage in four steps. Therefore, by detecting the change in the integrated voltage in the four steps, the movement time T for the four cylinders can be measured. Subsequently, in step S4, the number of cylinders moved per unit time, that is, the speed V is calculated by dividing the number of cylinders 4 by the measured movement time T.
[0282]
If the speed V can be calculated, it is checked in step S5 whether the integrated voltage is zero voltage, that is, whether the head reaches the cylinder corresponding to the master clock phase number 0, and the integrated voltage becomes zero. The process proceeds to step S6 at the timing. In step S6, the position value L indicating the amount of movement of the head with respect to the absolute position_posIs relatively zero.
[0283]
Subsequently, in step S7, the control is switched to speed control. In this speed control stage, since the head position is relatively obtained in step S6, the position at the next sampling point can be predicted in step S8. The position prediction may include an acceleration component as shown in FIG.
If the position at the next sampling time can be predicted in step S8, a master clock having a phase number corresponding to the cylinder at the predicted position is selected in step S9, and the target of the speed control pattern is determined from the number of remaining cylinders up to the target cylinder. The speed is obtained, and the speed control is repeated until the outer guard band OGB1 is detected in step S10.
[0284]
When the outer guard band OGB1 is detected in step S10, L indicating the position value is again detected in step S11._posPerform the original re-zero operation to make. This completes the rezero operation, and in step S12, switches to the fine control in which the outer guard band OGB1 is on-tracked to the detected cylinder address.
As described above, in the disk device of the present invention, even in the state of the re-zero operation in which the absolute position of the head is not determined, the speed control according to the prediction of the next head position based on the speed detection is reliably performed. Thus, the head can be reliably sought to the outer guard band region, and the rezero operation can be performed accurately.
13. Automatic adjustment of servo system
In order to optimize seek control in a magnetic disk drive, it is desirable to minimize the settling time when switching from core control, which performs speed control, to fine control. As a method of adjusting the servo system for suppressing the settling time to the minimum time, there is a method of measuring the absolute integral value of the position error shown in FIG. 82 and determining the acceleration / deceleration gain in the target speed pattern as the adjustment value.
[0285]
As another method, as shown in FIG. 83, there is an adjustment method of adjusting a speed gain in acceleration / deceleration of a target speed pattern as an adjustment value K so as to minimize the coace time as an evaluation function. The absolute value of the position error integrated value used as the evaluation function in FIG. 82 is obtained when the head moves to the target cylinder as shown in the target speed pattern in FIG. 85A, the seek current in FIG. 85B, and the position signal in FIG. In this case, the absolute value is obtained by integrating the error of the position signal until the vehicle enters the on-track state after switching from the coarse control to the fine control after reaching the position 0.5 cylinders before.
[0286]
As shown in FIG. 85 (C), the corus time Tc employed as the evaluation function in FIG. 83 is the time from the start of the speed control until the head reaches 0.5 cylinder before the target cylinder. The position error absolute integrated value ΔI and the coace time Tc used as these evaluation functions are the speed gains at the time of acceleration and deceleration in the target speed pattern of FIG. 85 (A), for example, the speed gains K1 and K2 indicating the slope at the time of acceleration. , K3.
[0287]
That is, as shown in FIG. 82, the position error absolute integral value ΔI has a characteristic 418 with respect to a change in the adjustment value K as a speed gain, and the optimum value of the evaluation function ΔI is obtained by two of the strong points 420 and 422. Can be Further, as shown in FIG. 83, the coace time Tc becomes a characteristic 424 with respect to the adjustment value K, and in this case, becomes an optimum evaluation function Tc at the singular point 426.
[0288]
However, when the position error absolute integrated value ΔI is used as the evaluation function in FIG. 82, even if the evaluation function ΔI becomes the minimum value, the coas time becomes too long and the seek performance is reduced as a whole. The adjustment status of the servo system cannot be obtained. Also, when the corus time Tc in FIG. 83 is used as the evaluation function, the corus time can be minimized, but the settling time until entering the on-track becomes long, so that optimization of the overall seek performance cannot be expected. .
[0289]
Therefore, in the automatic settling adjustment of the servo system according to the present invention, both the position error absolute integrated value ΔI in FIG. 82 and the corus time Tc in FIG. 83 are taken into the evaluation function to optimize the adjustment value K as the speed gain. Aim. More specifically, the seek operation is repeated while adjusting the speed gain as the adjustment value K, and the position error absolute integrated value ΔI and the core time Tc are measured for each seek operation, and the evaluation function (ΔI + Tc) obtained by adding the two values is used. Is used as an evaluation function, a characteristic 428 with respect to the adjustment value K shown in FIG. 84 is measured.
[0290]
If this characteristic 428 is obtained, the singular point 430 is determined as the optimal adjustment value that minimizes the evaluation function (ΔI + Tc), and the adjustment value K of the singular point 430 in the acceleration / deceleration of the target speed pattern shown in FIG. What is necessary is just to set a speed gain. As shown in FIG. 6, the automatic settling adjustment of the servo system is performed in the final step of the product shipping stage.
[0291]
By such settling adjustment in the seek control of the present invention, it is possible to obtain an optimal adjustment value that minimizes the coace time and the absolute value of the position error, thereby greatly improving the seek performance. In addition, since the automatic settling adjustment is performed for each disk device, it is possible to create an optimum adjustment state that also absorbs variations unique to the disk device.
14． Increase of on-track slice value during erase
In the disk device of the present invention, when a padding command is received from a higher-level disk controller unit, AC erase is performed using a write head in a section from an arbitrary record at a specified cylinder address until an index is detected. ing.
[0292]
Similarly to the read operation and the write operation, when the position error at the time of on-track by the servo head becomes larger than the preset on-track slice value during the erase operation in the padding process, it is determined that there is an error. In response to this error determination, a retry operation is performed in a read operation or a write operation. However, in the padding processing for erasing all data from the designated record to the index, if an error occurs due to an error with respect to the on-track, the padding processing is forcibly terminated.
[0293]
For this reason, the data of the record after the padding process was forcibly terminated remains on the cylinder without being erased, and the upper disk controller unit cannot detect abnormal termination during padding, and shifts to another process as it is. I do. As a result, a difference occurs between the recognition of the data management state in the upper disk controller unit and the actual data state in the disk device. For example, there is an ID having the same number in the same cylinder. There is a problem that an abnormal situation is caused and the apparatus ends abnormally as an abnormal state.
[0294]
Therefore, in the disk device of the present invention, in order to avoid abnormal termination due to an on-track error as much as possible during the padding process, the on-track slice value used in the read operation or the write operation is padded. It is characterized in that it is enlarged at the time of processing.
FIG. 86 shows a state where the write head 400 and the read head 410 provided on the data head are on-track at the cylinder center of the cylinder number 1. Here, assuming that the track pitch TP with respect to the adjacent cylinder center is, for example, 7.5 μm, the core width W1 of the write head 400 is smaller, for example, 6 μm, and the core width W3 of the read head 410 using the MR head is the same. It is about 3 μm, which is half.
[0295]
In the padding processing, the cylinder recording data is AC-erased by the write head 400, and the erasure range may be shifted from the track center as long as the read area of the read head provided in the adjacent cylinder is not erased. . That is, the write head 400 during the padding process is_S2It only has to be within the range. Where ± W_S2= ± 3 μm.
[0296]
FIG. 87 shows an on-track slice value ± W at the time of read / write in the disk device of the present invention._S186 and the on-track slice value ± W at the time of padding determined based on FIG._S2Is shown. On-track slice value ± W during read / write_S1Is usually about ± 1 μm. On the other hand, the on-track slice value ± W_S2Can be expanded to a maximum of 3 μm, for example, ± 2 μm.
[0297]
The flowchart in FIG. 88 shows the padding processing in the disk device of the present invention. In the padding process, first, in step S1, the head is sought to the target cylinder designated by the upper disk controller unit, and in step S2, when the head reaches 0.5 cylinder before the target cylinder, the process proceeds to step S3. , Then switch to fine control.
[0298]
In this fine control, the on-track slice value ± W used during normal read / write is used._S1Is used to monitor the on-track state, and the head position is ± W of the target cylinder._S1, The on-track detection signal is raised, this is determined in step S4, and the seek control is switched to on-track control.
Upon switching to the on-track control, in step S5, the expanded on-track slice value ± W for padding_S2And an erasing operation from the designated decoding to the detection of the index is performed in step S6. During the erase operation, in step S7, the enlarged on-track slice value ± W_S2Is checked to see if the head position signal exceeds, and if it does, the process ends abnormally in step S10.
[0299]
However, in the present invention, since the on-track slice value is enlarged sufficiently larger than the normal read / write value, it is unlikely that the on-track abnormality ends abnormally due to the on-track abnormality. The operation can be completed normally. When erasing is completed, in step S9, the on-track slice value is again returned to the original ± W_S1And returns to the main processing.
[0300]
In this way, during padding, by using the on-track slice value enlarged from the normal on-track slice value, it is possible to minimize the situation in which the padding process ends abnormally on the way.
15. Other
In the above embodiment, as shown in FIG. 8, a case where the peak detection circuit 100 is used as the first read pulse detection means and the zero-cross detection circuit 112 is used as the second read pulse detection means is exemplified. On the other hand, as a modification of the present invention, the zero-cross detection circuit 112 may be replaced with a peak pulse detection circuit as the second read pulse detection means.
[0301]
Specifically, except for the zero-cross detection circuit 112, the servo head 18 and the read head 410 are connected to the peak detection circuit 100 via the selection circuit 116, the output of the peak detection circuit 100 is input to the variable delay circuit 114, and the peak detection is performed. Input to the circuit 100.
In this case, a read pulse is generated by detecting the peak timing of all read signals in the training area, index guard band area, marker area, and servo area of the servo frame. In this case, the adjustment to the duty ratio of 50% by the shifter 108 and the variable delay circuit 114 guarantees the phase shift due to the circuit delay.
[0302]
Conversely, as another modification of the present invention, the peak detection circuit 100 may be replaced with a zero-cross detection circuit as the first read pulse detection means. In this case, a read pulse is generated by detecting the zero cross timing of all the read signals in the training area, index guard band area, marker area and servo area of the servo frame.
[0303]
Specifically, except for the peak detection circuit 100, the servo head 18 and the read head 410 are connected to the zero cross detection circuit 112 via the selection circuit 116, and the output of the zero cross detection circuit 112 is output to the PLL circuit 102, the marker detection circuit 014, The guard band index detection circuit 105 inputs the difference to the variable delay circuit 114. Also in this case, the adjustment to the duty ratio of 50% by the shifter 108 and the variable delay circuit 114 ensures the phase shift due to the circuit delay.
[0304]
Further, the disk device of the present invention is not limited to the above embodiments, and various combinations and modifications are possible within the scope described in the embodiments. The present invention is not limited by the numerical values shown in the embodiments.
[0305]
【The invention's effect】
As described above, according to the present invention, the following effects can be obtained.
First, since the phase servo pattern is read by zero-cross detection, the head position can be accurately detected without causing jitter due to noise such as peak detection.
[0306]
Further, the duty ratio of the ideal duty pulse at the time of on-track is shifted by 50% from the reference clock synchronously controlled by the peak detection by the zero-cross detection of the phase servo information. By performing the delay adjustment so that the measured value becomes 50%, a duty ratio of 50% is always obtained at the time of on-track, and the head position can be detected in a range of the target cylinder ± 2 cylinders.
[0307]
Even if various delays occur due to variations in circuit components, by adjusting the on-track duty ratio to 50%, variations in the detection range of the head position signal due to variations in the device can be reliably prevented.
In addition, in the speed control at the time of seeking using the phase servo pattern, the head position at the next sampling time is predicted from the speed. In the position prediction, in the present invention, in addition to the speed component, By adding the acceleration component, more accurate position prediction can be performed, and cylinder switching at the next sampling point and setting of the target speed based on the number of remaining cylinders can be performed accurately.
[0308]
Further, by performing cylinder switching stepwise in the first to fourth fields of the phase servo area for head detection during seek, the seek speed limited to ± 4 cylinders is expanded to a higher seek speed. The seek control can be performed at higher speed while detecting the head position, and the seek performance can be improved.
[0309]
In addition, by providing the disk device itself with a function of reading and writing phase servo information in a specific cylinder on the data surface, writing of phase servo information on the data surface before product shipment can be easily performed.
The writing of the phase servo pattern on the data surface is different from the data surface servo pattern because the read head of the data head is small. However, the generation of a simple write signal, that is, the phase servo pattern on the servo surface In addition to the 8-phase write signal used for writing the data, the 16-phase write signal obtained by adding the 8-phase signal basically generated by the same circuit is used to easily store the phase servo information on the data surface. Can write.
[0310]
Further, the phase servo information recorded on the specific cylinder on the data surface can be read out to easily perform the yaw angle offset correction and the thermal offset correction, thereby greatly improving the servo performance.
Further, the unique phase servo pattern corresponding to the data bits 0 and 1 is recorded by utilizing the function of writing and reading the phase servo information with respect to the data surface, so that the circuit on the disk enclosure side and the disk controller side can be realized by the disk device alone. The combination can be adjusted by reading and writing various information on the combination with the substrate.
[0311]
Other than this, automatic adjustment of the center value of the DA converter used for current limitation of the VCM, rezero operation peculiar to the use of phase servo information, automatic adjustment of settling of the servo system, and furthermore, when erasing in the padding process, By increasing the on-track slice value, the overall performance of the disk device can be significantly increased.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle of the present invention.
FIG. 2 is a block diagram showing a hardware configuration of the present invention.
FIG. 3 is a structural explanatory view of the disk enclosure of FIG. 2;
FIG. 4 is a side sectional view of the head actuator of FIG. 3;
FIG. 5 is a block diagram showing functions of the present invention.
FIG. 6 is a flowchart showing processing before shipment of a disk device according to the present invention;
FIG. 7 is a flowchart showing the overall processing operation of the disk device of the present invention.
FIG. 8 is a block diagram showing an embodiment of the position signal generating circuit of FIG. 2;
FIG. 9 is an explanatory diagram of magnetic recording of a servo pattern.
FIG. 10 is an explanatory diagram of a servo frame of the present invention recorded on a servo surface.
FIG. 11 is an explanatory diagram of a magnetic recording pattern in a training section and a marker section in FIG. 10;
FIG. 12 is an explanatory diagram of a magnetic recording pattern in a guard band index portion of FIG. 10;
FIG. 13 is an explanatory view of a magnetic recording pattern of the first two fields in the servo pattern section of FIG. 10;
14 is an explanatory diagram of a magnetic recording pattern in the latter two fields in the servo pattern portion of FIG. 10;
FIG. 15 is a timing chart of eight kinds of write signals having even numbers to be used for writing servo patterns;
FIG. 16 is a timing chart of eight kinds of write signals having odd numbers used for writing a servo pattern;
FIG. 17 is a block diagram showing an embodiment of the master clock generation circuit of FIG. 8;
FIG. 18 is an explanatory diagram showing combinations of phase numbers of write signals used for writing on a servo surface.
FIG. 19 is an explanatory diagram showing a combination of master clock phase numbers used for cylinder switching;
20 is a timing chart showing a determination state of a servo frame by the match determination circuit of FIG. 8;
FIG. 21 is an explanatory diagram showing position detection during on-track.
FIG. 22 is a circuit diagram showing an embodiment of the integration circuit of FIG. 8;
FIG. 23 is a timing chart showing a position detection operation by the integration circuit of FIG. 8;
FIG. 24 is a timing chart showing a difference in duty ratio between peak detection and zero-cross detection.
FIG. 25 is a block diagram illustrating a control unit of the integration circuit of FIG. 22;
26 is a timing chart showing the operation of measuring the duty ratio by the integration control unit in FIG. 2;
FIG. 27 is a block diagram showing an embodiment of the shifter of FIG. 8;
FIG. 28 is a timing chart showing the delay operation of the shifter of FIG. 27;
FIG. 29 is a block diagram showing an embodiment of the variable delay circuit of FIG. 8;
30 is a timing chart showing the delay operation of the variable delay circuit shown in FIG. 29;
FIG. 31 is an explanatory diagram showing a delay time of a delay element used in the variable delay circuit of FIG. 29;
FIG. 32 is an explanatory diagram of table information for determining a delay time of the variable delay circuit in FIG. 29;
FIG. 33 is a timing chart showing delay adjustment to a duty ratio of 50% by the shifter and the variable delay circuit of FIG. 8;
FIG. 34 is a flowchart showing a duty adjustment process of the present invention.
FIG. 35 is a flowchart showing a delay time setting process for a variable delay circuit;
FIG. 36 is a timing chart showing generation of a duty pulse used for error measurement of an integration circuit;
FIG. 37 is a timing chart showing an operation of measuring an integration error according to the present invention.
FIG. 38 is a timing chart showing a cylinder gain measuring operation according to the present invention.
FIG. 39 is a flowchart showing the integration circuit adjustment processing of the present invention.
FIG. 40 is an explanatory diagram showing position prediction using only velocity components.
FIG. 41 is an explanatory diagram showing position prediction including an acceleration component according to the present invention.
FIG. 42 is a timing chart showing prediction of an acceleration component using a VCM drive current according to the present invention.
FIG. 43 is a flowchart showing a seek process in the disk device of the present invention.
FIG. 44 is a flowchart showing a position prediction according to the present invention as a subroutine;
FIG. 45 is an explanatory diagram of a head moving speed having a speed range of +4 to -4 cylinders.
FIG. 46 is an explanatory diagram showing a relationship between a cylinder number used for cylinder switching and a master clock phase number.
FIG. 47 is an explanatory diagram showing a combination of master clock phase numbers used in each field of FIG. 45;
FIG. 48 is an explanatory diagram of a head moving speed having a speed range of +6 to −2 cylinders.
FIG. 49 is an explanatory diagram showing a combination of master clock phase numbers used in each field of FIG. 48;
FIG. 50 is an explanatory diagram of a head moving speed having a speed range of +7 to −1 cylinder.
FIG. 51 is an explanatory diagram showing a combination of master clock phase numbers used in each field of FIG.
FIG. 52 is an explanatory diagram of a head moving speed having a speed range of +10 to +4 cylinders.
FIG. 53 is an explanatory diagram showing a combination of master clock phase numbers used in each field shown in FIG. 52;
FIG. 54 is an explanatory diagram of a shift pattern of a seek speed according to FIGS. 45, 48, 50, and 52.
FIG. 55 is a flowchart showing a cylinder switching process according to a seek speed according to the present invention.
FIG. 56 is an explanatory diagram of a servo frame on a data surface according to the present invention;
FIG. 57 is an explanatory diagram of a magnetic recording pattern of the first to third fields of the servo pattern portion of FIG. 56;
FIG. 58 is an explanatory diagram of a magnetic recording pattern of the fourth field of the servo pattern section of FIG. 56;
FIG. 59 is an explanatory diagram showing the first and fourth fields of FIGS. 57 and 58 in comparison with each other;
60 is an explanatory diagram showing a comparison between the second and third fields in FIG. 58;
FIG. 61 is an explanatory diagram of position detection by a servo head on a servo surface.
FIG. 62 is an explanatory diagram showing a problem when the same pattern as the servo surface is recorded on the data surface and the position is detected by the read head.
FIG. 63 is an explanatory diagram of position detection using a data surface servo pattern according to the present invention.
FIG. 64 is a view for explaining a combination of phase numbers of write signals used for data surface servo writing according to the present invention;
FIG. 65 is an explanatory view showing a combination of master clock phase numbers used for data surface servo reading according to the present invention;
FIG. 66 is a flowchart showing a data surface servo pattern writing process according to the present invention;
FIG. 67 is a timing chart showing a phase servo pattern of data bit 0 and a read operation according to the present invention;
FIG. 68 is a timing chart showing a phase servo pattern of data bit 1 and a read operation according to the present invention.
FIG. 69 is a flowchart showing a write process of the present invention using a phase servo pattern.
FIG. 70 is a flowchart showing a read process of the present invention using a phase servo pattern.
FIG. 71 is an explanatory diagram showing a relationship between a yaw angle and a data head.
FIG. 72 is an explanatory diagram of a ride head and a read head provided in a data head.
FIG. 73 is an explanatory diagram showing the offset of the read head at the maximum yaw angle between the inner and the outer.
FIG. 74 is an explanatory diagram showing a change in the offset with respect to the yaw angle by linear interpolation.
FIG. 75 is a flowchart showing the yaw angle offset measurement of the present invention.
76 is an explanatory diagram of an offset correction table created by the yaw angle offset measurement of FIG. 75.
FIG. 77 is a flowchart showing a read process involving yaw angle offset correction;
FIG. 78 is a block diagram showing a VCM drive circuit system according to the present invention.
FIG. 79 is an explanatory diagram showing a center value measuring operation of the VCM DA converter;
FIG. 80 is a flowchart showing the center value adjustment processing of the VCM DA converter according to the present invention;
FIG. 81 is a flowchart showing a rezero process according to the present invention;
FIG. 82 is a characteristic diagram showing a relationship with an adjustment value when an evaluation function is a position error absolute integral value;
FIG. 83 is a characteristic diagram showing a relationship with an adjustment value when an evaluation function is set to a core time.
FIG. 84 is a characteristic diagram showing the servo system automatic adjustment of the present invention for determining an adjustment value by using an evaluation function as a sum of a position error absolute integral value and a coace time;
FIG. 85 is a timing chart showing the position error absolute integral value and the coace time in the seek control.
FIG. 86 is an explanatory diagram showing a relationship between a write head and a read head provided in a data head for an adjacent cylinder.
FIG. 87 is an explanatory diagram of an on-track slice value enlarged by padding processing according to the present invention;
FIG. 88 is a flowchart showing padding processing according to the present invention;
FIG. 89 is an explanatory diagram of a conventional phase servo pattern.
90 is a timing chart showing duty pulses in the first and third fields EVEN1 and EVEN2 when on-tracking is performed on each of cylinder numbers 1, 2, and 3 in FIG. 89.
FIG. 91 is a timing chart showing duty pulses in the second field ODD when on-tracking is performed on each of cylinder numbers 2 and 3 in FIG. 89;
[Explanation of symbols]
1: Duty adjustment means
2: Duty measuring means
3: Read pulse detection means
10: Disk enclosure
12: Drive controller
14: Spindle motor
16: Voice coil motor (VCM)
18: Servo head
20, 20-1 to 20-n: Data head
22: Servo head IC
24: Data head IC
26: Control processor (MPU)
28: Interface circuit
30: Drive processor (DSP)
32, 40: DA converter
34, 42: Driver
36: Position signal creation circuit
38: AD converter
44: Encoding / decoding circuit
46: bias current control circuit
48: Demodulation circuit
50, 50-1 to 50-11: Magnetic disk
52: Case
54: Rotation axis
56-1, 56-2: Bearing
58: Head actuator
60: Shaft
62: Block
64: coil
66-1 to 66-11: Arm
70: Servo system automatic adjustment unit
72: Data surface phase information writing unit
74: data side bit data write / read unit
76: yaw angle offset measuring unit
78: Yaw angle offset correction unit
80: DAC center value adjustment unit for VCM
82: Rezero processing unit
84: Duty delay adjustment processing unit
86: integration circuit adjustment processing unit
88: seek control unit
90: cylinder switching control unit
92: position prediction processing unit
94: Thermal offset measuring unit
96: Thermal offset correction unit
98: Padding processing unit
100: peak detection circuit
102: PLL circuit
104: marker detection circuit
105: guard band index detection circuit
106: PLL counter
108: Shifter
110: Master clock generation circuit
112: Zero cross detection circuit
114: Variable delay circuit
116, 118: selection circuit
120: Duty pulse creation circuit
122: Match detection circuit
122-1: Demodulation mode generator
122-2: Half mode generation section
122-3: Data window generator
122-4: Discharge control unit
124: integration circuit
126: condenser
128, 130, 132, 134: control switch
138, 140, 142, 144, 146: constant current source
148, 150: Operational amplifier
152: Differential amplifier
156: Servo frame
158: Training Department
160: Marker section
162: guard band index section
164: Servo pattern section
174: First majority decision section
176: Second majority decision unit
178: Third Majority Division
200: First field (EVEN1)
202: Second field (ODD1)
204: Third field (ODD2)
206: Fourth field (EVEN2)
300, 302, 304: D-FF
306: Selection circuit
308-1 to 308-8: Delay element
310-1 to 310-8: selection circuit
312: Inverting circuit
314, 322, 324: AND circuit
318, 320, 326, 328: OR circuit
316: Exclusive OR circuit (EOR)
350: Data surface servo frame
370: Data surface servo pattern section
400: Light head
410: read head (MR head)
414: Reference voltage generation circuit
416: Comparison circuit
500, 510: shift circuit
520: Inverting circuit
530: Multiplexer

Claims (46)

Each of a plurality of servo frames arranged in the circumferential direction of each cylinder with a plurality of cylinders as one unit is divided into four fields, and the first and fourth fields (EVEN1, 2) among them are used to determine the phase change of the position. A servo area in which servo information having opposite phase changes is recorded in the second and third fields (ODD1, 2), and a marker signal is provided in a marker area following the training area at the beginning of the servo frame. And the servo surface of the disk medium on which the phase servo signal is recorded in the servo pattern provided at the end of the servo frame ,
Servo head means (18) for reading the recorded information on the servo surface by moving in the radial direction of the disk medium;
Peak detection means (100) for detecting a peak detection pulse from a peak timing of the servo frame read signal;
Zero cross detection means (112) for detecting a phase servo signal from a zero cross timing of the servo frame read signal;
Clock generating means (102) for generating a reference clock synchronized in phase with the peak detection pulse detected by the peak detecting means (100) ;
A plurality of master clocks having different phases are generated using the reference clock of the clock generation means (102) as a reference phase, and a master clock having a phase corresponding to a target cylinder on-tracked by the servo head means (18) is selected. A master clock generating means (110) for outputting;
Duty pulse generation for generating a duty pulse having a duty ratio corresponding to a phase difference from a reference phase of a master clock output by the master clock generation means (102) to a timing of detecting the servo information by the zero cross detection means (112) Means (120);
Integration means (124) for integrating the duty pulse from the duty pulse creation means (120) to generate a position signal indicating the position of the servo head means (18);
A duty measuring means (1) for measuring a duty ratio of the duty pulse in an on-track state of the servo head means (18) with respect to a specific target cylinder in an initialization processing immediately after power-on;
Duty adjustment means (2) for creating an adjustment state for maintaining a duty ratio of the duty pulse at 50% in an on-track state of a target cylinder based on a measurement result of the duty measurement means;
A disk device comprising: 2. The disk device according to claim 1, wherein the duty measuring means inverts a portion of the duty pulse corresponding to the second and third fields of the servo information and integrates the duty pulse with the integrating means. A disc drive that obtains an integral signal indicating a duty ratio. 2. The disk device according to claim 1, wherein the duty adjustment unit includes a first delay unit that delays a reference phase of the master clock to reduce the duty ratio, and a duty cycle of the servo frame read signal. A disk device comprising: a second delay means (114) for delaying a zero-cross detection timing to increase a duty ratio. 4. The disk drive according to claim 3 , wherein said first delay means (108) includes a shift circuit for delaying stepwise by a predetermined time determined by said reference clock within one cycle of said master clock. A disk device for selecting a shift stage output of any one of the circuits and giving a desired delay amount to the master clock. 4. The disk device according to claim 3 , wherein the second delay means includes a plurality of delay elements having a determined delay amount, and selectively connects the plurality of delay elements in series to store the servo information. A disk device for providing a desired amount of delay to a read pulse. The disk device according to claim 1, further comprising:
The servo surface of the disk medium, to each of a plurality of servo frames arranged in the circumferential direction of the specific cylinder, a servo area for recording servo information having an inverted phase change records the servo information having a phase change of the position Switching means (116) for switching between a read signal of the servo head means (18) and a read signal of the data head means (20) and inputting the read signal to the zero cross detection means (112) ;
The duty measuring means (1) measures the duty ratio of the duty pulse obtained from the servo information on the servo surface, and the duty adjusting means (2) calculates the duty ratio of the duty pulse obtained from the servo information on the servo surface. A disk device for producing an adjustment state in which a ratio is maintained at 50% in an on-track state of a target cylinder. The disk device according to claim 1, further comprising:
At the time of initialization processing immediately after power-on, the servo head means (18) supplies a duty pulse corresponding to an on-track state to an arbitrary target cylinder position on the servo surface to the integration means (124) for integration. Integration error measuring means for measuring an error,
After completion of the initialization processing, an integration error correction means for correcting the position signal obtained from the integration means (124) with the integration error to obtain a correct position signal;
A disk device comprising: 8. The disk drive according to claim 7 , wherein the integral error measuring means generates the duty pulse such that the first to fourth fields of the servo information all have a duty ratio of 50%. 120) A disk device comprising a pseudo pulse generating means for supplying a pseudo read pulse of servo information to the disk drive. The disk device according to claim 1, further comprising:
At the time of initialization processing immediately after power-on, a duty pulse equivalent to moving one cylinder in one direction from the generation of a duty pulse equivalent to on-tracking the servo head means (18) to an arbitrary target cylinder on the servo surface. Measuring means for switching to the generation of a duty pulse equivalent to moving the cylinder by one cylinder in the opposite direction and causing the integrating means (124) to measure each position change;
Cylinder gain detection means for detecting a position change amount per cylinder as a cylinder gain based on a position change of the measurement means;
A disk device comprising: 10. The disk device according to claim 9 , wherein the measuring unit outputs a duty pulse having a duty ratio of 50% in all of the first to fourth fields of the servo information and a duty ratio of 25% in the first to fourth fields. %, 75%, 75%, 25% and varying the duty ratio of 75% by generating a first Filled to fourth field duty pulse, 25%, 25%, so as to perform the generation of the duty pulse that varies 75% the disk device according to claim wherein the relative master clock creating means (120) further comprising a pseudo pulse generating means for supplying a pseudo read pulse of the servo information. The disk device according to claim 1, further comprising:
A position prediction means for detecting the head position by adding the acceleration to the head moving speed in a seek operation rather based on the difference between the head position obtained for each sampling period,
A master clock selection means for selecting a master clock phase corresponding to the target cylinder at based on the head position, the master clock creating means (110) at the next sampling time obtained for each of the pulling cycle,
A disk device comprising: 12. The disk drive according to claim 11 , wherein the master clock selecting means switches a target cylinder in each of the first to fourth fields of the servo area according to a head moving speed and selects a master clock having a corresponding phase. A disk device characterized by causing the disk device to: In the disk device according to claim 12, wherein the master clock selecting means, the number of changes first to the target cylinder of each switching cylinder switching stages and the cylinder in the fourth field increases with the increase range of the head moving speed A disk device characterized in that the amount is determined . 13. The disk drive according to claim 12 , wherein , instead of said master clock selecting means, when the head moving speed defined by the number of moving cylinders per said sampling period is within the number of cylinders in which servo information is repeated, the first to fourth times. A disk device comprising first master clock selecting means for fixedly selecting a master clock of a corresponding phase without switching a target cylinder in a field. 13. The disk drive according to claim 12 , wherein when the number of repeating cylinders of the servo information is four, the master clock selecting means is replaced with the first to fourth cylinders when the head moving speed is between -4 and +4 cylinders. A disk device comprising second master clock selecting means for selecting a master clock having a phase corresponding to a target cylinder serving as a central cylinder without switching target cylinders in a field. 13. The disk drive according to claim 12 , wherein, instead of the master clock selecting means, when the head moving speed defined by the number of moving cylinders in the sampling period exceeds the number of repetitive cylinders of the servo information, A disk device comprising third master clock selecting means for selecting a master clock having a corresponding phase by switching a target cylinder in two stages in a field and third and fourth fields. 17. The disk drive according to claim 16 , wherein when the number of repeating cylinders of the servo information is four, the third master clock selecting means selects the first and second cylinders when the head moving speed is between -2 and +6 cylinders. In two fields, the target cylinder is switched to a target cylinder one cylinder less than the center cylinder, and in the third and fourth fields, the target cylinder is switched to a target cylinder one cylinder more than the center cylinder to select a master clock having a corresponding phase. Disk device. 13. The disk drive according to claim 12 , wherein the master clock selecting means is replaced by a first to fourth field when the head moving speed defined by the number of moving cylinders in the sampling period exceeds the number of repeating cylinders of servo information. And a fourth master clock selecting means for selecting a master clock having a corresponding phase by switching the target cylinder in a plurality of stages for each of the plurality of target cylinders. 20. The disk device according to claim 18 , wherein the position predicting means divides the target cylinder into a plurality of stages in units of one cylinder for each of the first to fourth fields, and selects a master clock having a corresponding phase. A disk device characterized by the above-mentioned. 19. The disk device according to claim 18 , wherein, when the number of repeating cylinders of the servo information is four, the position predicting means sets the center cylinder in the first field when the head moving speed is between -1 and +7 cylinders. On the other hand, switch to the target cylinder that is two cylinders less, switch to the target cylinder one cylinder less than the center cylinder in the second field, switch to the target cylinder one cylinder more than the center cylinder in the third field, and further switch to the target cylinder in the fourth field. A disk device characterized by switching to a target cylinder having two cylinders and selecting a master clock having a corresponding phase. 20. The disk device according to claim 18 , wherein the position predicting means switches the target cylinder in a plurality of stages in units of a plurality of cylinders for each of the first to fourth fields and selects a master clock having a corresponding phase. A disk device characterized by the above-mentioned. 22. The disk device according to claim 21 , wherein when the number of repeating cylinders of the servo information is four, the position predicting means determines whether or not the head movement speed is between +4 and +10 cylinders with respect to the center cylinder in the first field. Switch to a target cylinder that is three cylinders less, switch to a target cylinder one cylinder less than the center cylinder in the second field, switch to a target cylinder one cylinder more than the center cylinder in the third field, and switch three cylinders to the target cylinder in the fourth field. A disk drive characterized by switching to a target cylinder having more cylinders and selecting a master clock having a corresponding phase. In the disk apparatus of claims 11 to 22, wherein the master clock switching means, the disk apparatus characterized by detecting the speed and acceleration of the head movement of the head movement predicting the head position of the next sampling time point . In the disk apparatus of claims 11 to 22, wherein the master clock switching means, and calculating means calculates the predicted position is added to the current position of the number of mobile cylinders dependent on the head acceleration based on the head drive current Disk device to be used. The disk device according to claim 1, further comprising:
A data surface of a disk medium that rotates integrally with the servo surface;
Data head means (20) for reading the recorded information on the data surface by moving integrally with the servo head means (18) in the radial direction of the disk medium;
On each of a plurality of servo frames arranged in the circumferential direction of a specific cylinder on the data surface, servo information having a phase change in position and servo information having a reverse phase change are recorded to form a servo area. Data surface servo information writing means;
A disk device comprising: 26. The disk device according to claim 25 , wherein said data surface servo information writing means divides the servo area of the data surface into four fields, and divides the first and fourth fields (EVEN1, 2). ), Servo information having a phase change in position is recorded, and servo information having an opposite phase change is recorded in the second and third fields (ODD1, 2). 27. The disk device according to claim 26 , wherein when the number of cylinder repetitions of the servo information recorded on the servo surface is N, the data surface servo information writing unit includes:
The reference clock is frequency-divided by 1 / N, and 4N kinds of write pulses whose phases are different from each other by 0.25 N cycles are generated. A disk device wherein a specified write pulse having a predetermined phase is selected and written as servo information in a servo area on the data surface. 27. The disk device according to claim 26 , wherein when the number of cylinder repetitions of the servo information recorded on the servo surface is N, the data surface servo information writing unit starts at the rising edge of the reference clock of the reference clock generation unit. A disk drive for generating a write pulse having an even-numbered phase number corresponding to 2N phases and generating a write pulse having an odd-numbered phase number corresponding to the remaining 2N phases synchronized with the falling edge of the reference clock; . 29. The disk device according to claim 28 , wherein when the number of cylinder repetitions of the servo information recorded on the servo surface is four cylinders, the data surface servo information writing means divides the frequency of the reference clock by １ ／. A disk drive for generating write pulses for eight phases in synchronization with the rise of the reference clock, and generating write pulses for the remaining eight phases in synchronization with the fall of the reference clock. 27. The disk device according to claim 26 , wherein the data surface servo information writing means records servo information on the data surface at the same cylinder pitch as the servo information on the servo surface, and writes the servo information of the first and fourth fields. A disk device for writing servo information and phase information of the second and third fields with a shift of a predetermined cylinder pitch. 31. The disk device according to claim 30 , wherein, when servo information is recorded on the servo surface at a 0.5 cylinder pitch, the data surface servo information writing means includes the same data as the servo surface on the data surface. The servo information is written at a pitch of 5 cylinders, and the servo information of the first and fourth fields and the phase information of the second and third fields are written with a shift of 0.25 cylinder pitch. Disk device to be used. 27. The disk drive according to claim 26 , wherein said data surface servo information writing means writes servo information in a predetermined off-track area centered on a write target cylinder. 27. The disk device according to claim 26 , wherein said data surface servo information writing means writes servo information used for off-track measurement of a data surface to an outer peripheral cylinder outside a user area of said data surface. Disk device. 27. The disk device according to claim 26 , wherein the data surface servo information writing means is configured to measure a yaw angle offset of a head drive mechanism for each of an outer cylinder and an inner cylinder that are out of a user area of the data surface. A disk device for writing servo information to be used. The disk device according to claim 34 ,
At the time of initialization immediately after power-on, the data head means (20) integrally provided with a write head and a read head is moved to each of the outer cylinder and the inner cylinder of the data surface based on the servo information of the servo surface. A yaw angle offset measuring means for measuring the yaw angle offset of the read head associated with the rotation of the head arm by positioning the head arm;
Table creation means for obtaining a yaw angle offset at each cylinder position by interpolation calculation of each yaw angle offset of the inner circumference and the outer circumference measured by the yaw angle offset measurement means, and creating a correction table using a cylinder address as an index,
A disk device comprising: 36. The disk device according to claim 35 , wherein said correction table creating means creates a correction table storing a yaw angle offset in units of a predetermined number of cylinders. 36. The disk device according to claim 35 , further comprising: a yaw angle offset correction unit that reads a yaw angle offset of the correction table and corrects a head position when reading the data surface. . 38. The disk device according to claim 37 , wherein the yaw angle offset correction means corrects the yaw angle offset when a data surface read error occurs and performs a retry operation. In the disk device according to claim 1,
Data writing means for writing data using servo information to a specific cylinder outside the user area on the data surface;
Data reading means for reading servo information written by the data writing means and restoring data;
A disk device comprising: 40. The disk device according to claim 39 , wherein said data writing means has different duty ratios between the first and fourth fields and the second and third fields corresponding to write data bits 0 and 1. A disk device for writing servo information using a duty pulse. 41. The disk device according to claim 40 ,
The data writing means includes a duty pulse having a duty ratio of 25%, 75%, 75%, 25% for the first to fourth fields, and a duty pulse having a duty ratio of 75%, 25%, 25% for the first to fourth fields. A disk device for writing servo information corresponding to write data bits 0 and 1 using one of two types of duty pulses of% and 75%. 40. The disk device according to claim 39 , wherein the data reading means supplies a read signal of the servo information on the data surface to the master clock generating means (120) to generate a duty pulse, and further comprises the integration means ( 120) A disk device for restoring data bit 0 or 1 from a signal obtained by integrating a duty pulse in step 120). The disk device according to claim 1, further comprising:
DA conversion means for converting head drive data during servo control to an analog signal, reference voltage generation means for generating a reference voltage for setting a conversion center value of a center value of the DA conversion means,
A drive unit that supplies a drive current to a head drive unit according to the polarity and magnitude of a conversion signal of the DA conversion unit with respect to the reference voltage;
A center error measuring unit that changes the head drive data from a center value to obtain an error until a DA conversion signal matches the reference voltage during an initialization process immediately after power-on;
A center error correction unit that corrects the head drive data for the DA conversion unit so as to remove the sensor error after the initialization process;
A disk device comprising: The disk device according to claim 1, further comprising:
Coarse time measuring means for measuring coarse time until switching from coarse control to fine control in seek operation while varying a gain for determining acceleration / deceleration of a target speed pattern used for speed control as an adjustment value;
Integral measuring means for measuring an absolute integral value of a position error from switching to fine control in a seek operation to on-track while varying a gain for determining acceleration / deceleration of a target speed pattern used for speed control as an adjustment value;
Adjustment means for automatically adjusting the servo system by detecting the sum of the absolute integral values of the Coass time and the position error obtained by each of the measurement means as the evaluation function and the adjustment value serving as the minimum value as the optimum value,
A disk device comprising: The disk device according to claim 1, further comprising:
A disk device comprising means for changing an on-track slice value for judging an on-track state at the time of erasing to a value enlarged from the on-track slice value at the time of reading and writing. 2. The disk device according to claim 1, wherein an index guard band area in which a plurality of sets of index information and card band information are simultaneously recorded is provided between the marker area and the servo area, and the plurality of sets of index information and card band information are provided. And a detecting means for detecting each information based on a majority decision of the read result.

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