JP3566342B2 - Parallel operation high-speed counter device - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a parallel operation high-speed counter device used for controlling test patterns and accumulating test results of an LSI test device.
[0002]
[Prior art]
FIG. 4 is a block diagram showing a conventional example in which a carry look-ahead (carrying method) is used as an n-bit counter used for controlling test patterns and accumulating test results of an LSI test apparatus.
For example, when configuring an n-bit counter, an n-bit flip-flop and a logic circuit for increasing the output of the flip-flop by +1 are combined. Each time a clock is input to the flip-flop, the counter output increases by one. When the number of bits of the counter increases, even if carry-look ahead is taken, there is a disadvantage that the propagation delay increases and the operating frequency of the counter decreases.
The propagation delay time of the adder circuit and the setup time of the flip-flop determined the upper limit of the operating frequency of the counter.
[0003]
[Problems to be solved by the invention]
It is systematically difficult to increase the operating frequency of the counter by, for example, n times in a system employing a carry look ahead.
Even if the LSI test apparatus has a performance of 500 MHZ, the performance of the LSI test apparatus cannot be simply shown unless 500 MHZ can be counted. For this reason, for example, it is required that a performance of 500 MHZ can be obtained by using a counter having a performance of 250 MHZ (n times as large).
In view of the above, an object of the present invention is to realize a high-speed counter by combining a serial / parallel conversion unit, a toggle flip-flop, a counter increment control circuit, an odd counter, an even counter, and a MUX unit in order to improve the counter performance. did.
Then, two systems of counters are operated in parallel to enable high-speed counting which is impossible with one counter.
[0004]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, a counter enable input 100 for receiving a high-speed counter signal, a clock input 200 as an operation reference of the parallel operation high-speed counter device, and a reset input 300 as a command for driving the present device are input to each input. Signal. The counter enable flip-flops 61, 62, 63, the toggle flip-flop 51, and the even flip-flops 71, 72, 73 convert the counter enable data inputted in synchronization with the clock into n parallel data in a cycle obtained by dividing the clock by n. It becomes a means to rearrange.
The counter increment control circuit 80 receives each of the above parallel data and generates a control signal for n counters based on a fixed truth table.
The odd counter 91 and the even counter 92 are n parallel operation counters to which +1 or +2 is added by a signal from the counter increment control circuit 80.
The MUX 93 performs parallel-to-serial conversion of the output of each of the above-described parallel counters, and can output the total count at high speed.
[0005]
[Action]
As the serial / parallel conversion stage, the counter enable flip-flops 61, 62, 63, the toggle flip-flop 51, and the even flip-flops (71, 72, 73) divide the input counter enable data in synchronization with the clock by n. It operates so as to be rearranged into n parallel data in the cycle.
The counter increment control circuit 80 receives the respective parallel data and operates to generate control signals for the n counters.
The odd counter 91 and the even counter 92 are operated by a signal from the counter increment control circuit 80, and are n counters which operate in parallel and are incremented by +1 or +2.
The MUX 93 operates so that the whole count can be counted at a high speed as a result of the above-mentioned n-parallel counter being converted from parallel to serial.
[0006]
【Example】
A block diagram according to an embodiment of the present invention is shown in FIG. FIG. 2 is a timing chart according to the embodiment of the present invention. FIG. 3 shows a truth table of the counter increment control circuit.
As an embodiment according to the present invention, an example is shown in which two 2-system counters are operated in parallel to enable high-speed counting which is impossible with one counter.
(1) The counter enable input 100, the clock input 200, and the reset input 300 are input signals. The reset input initializes the flip-flop of each stage and each counter.
(2) Counter enable flip-flops 61 and 6263 that output a todd signal, a toggle flip-flop 51, an even flip-flop 71, a flip-flop 72 that outputs a teven signal, and an even flip-flop 73 that outputs a t-1 even signal are provided. The stage performs the following operations.
The counter enable flip-flops 61, 62, and 63, the toggle flip-flop 51, and the even flip-flops 71, 72, and 73 rearrange the data into serial-parallel conversion, that is, two-parallel data in the cycle of dividing the clock by two.
(3) An odd counter 91 and an even counter 92 are provided between the counter increment control circuit 80 and the MUX 93, and an odd counter output 400 from the odd counter 91, an even counter output 500 from the even counter 92, and a double speed counter output 600 from the MUX 93 are taken out, respectively. . The stage performs the following operations.
The counter increment control circuit 80, which has received the todd, teven, and t-1even signals from the previous stage, generates a control signal for the odd counter 91 and the even counter 92 as shown in the truth table shown in FIG. The odd counter 91 and the even counter 92 perform an operation of +1 or +2 according to a signal from the counter increment control circuit 80, and output an addition result.
The MUX 93 performs parallel-to-serial conversion of the parallel counter output, and operates so that the entire apparatus can count at high speed.
[0007]
Numerals between the stages in the reference numerals of the block diagram shown in FIG. 1 indicate points for explanation in FIGS.
In the timing chart of FIG. 2, a reset is input, a clock is input, the operation of the entire apparatus is determined, and a high-speed counting signal is input from the counter enable 2.
Points 3 and 4 show how the fast counting signal is divided by n. Point 18 indicates that the data is integrated by the MUX 93 and multiplied by n.
Then, the device according to the present invention performs the logical operation shown by the timing charts of numerals 2 to 18.
FIG. 3 shows a truth table of the counter increment control circuit 80, and shows outputs 11, 12, 13, and 14 for input points 8, 9, and 10.
[0008]
【The invention's effect】
The present invention is configured as described above, and has the following effects.
(1) When a high-speed counting signal is input from the counter enable input 2, each serial / parallel conversion stage operates. The outputs of the respective counters are integrated in parallel serial by the MUX 93, and are read out as the double speed counter output 600.
(2) Two systems of counters are operated in parallel to enable high-speed counting which is impossible with one counter.
[Brief description of the drawings]
FIG. 1 is a block diagram of one embodiment of the present invention.
FIG. 2 is a timing chart of the present invention.
FIG. 3 is a truth table of the counter increment control circuit of the present invention.
FIG. 4 is a block diagram of a conventional example.
[Explanation of symbols]
100 Counter enable input 200 Clock input 300 Reset input 51 Toggle flip-flop 61 Counter enable flip-flop 62 Counter enable flip-flop 63 Counter enable flip-flop 71 even FF
72 t even FF
73 t-1 even FF
80 counter increment control circuit 91 odd counter 92 even counter 93 MUX
400 odd counter output 500 even counter output 600 double speed counter output

Claims (1)

A toggle flip-flop (51) for performing a toggle operation in response to a clock input (200) signal;
A counter enable flip-flop (61, 62, 63) for receiving a counter enable input (100) signal and outputting a todd signal;
An even flip-flop (71, 72) that receives the counter enable input (100) signal and outputs a teven signal, and an even flip-flop (73) that outputs a t-1 even signal,
A counter increment control circuit (80) for receiving the output of each flip-flop and outputting based on a certain truth table;
An odd counter (91) and an even counter (92) for receiving the output of the counter increment control circuit (80) and performing +1 operation and +2 operation;
A multiplexer (93) for multiplexing and outputting the output of the odd counter (91) and the output of the even counter (92);
A parallel operation high-speed counter device comprising the above.

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