JP3655812B2 - Decoding circuit, decoding method, and timing pulse generation circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a decoding circuit and a decoding method used in a timing pulse generation circuit and the like, and a timing pulse generation circuit using them.
[0002]
[Prior art]
In recent years, LSI power consumption has been increasing due to the increase in scale and speed associated with process miniaturization. In an LSI, a decode circuit used in a timing pulse generation circuit or the like that uses a sequential circuit output such as a counter is configured by a circuit that combines logic gates such as AND and OR.
[0003]
For example, in the timing pulse generation circuit shown in FIG. 10, a decoding circuit comprising a 2-bit binary up counter 1, a 2-input OR gate 2 for decoding the outputs “1” and “0”, and a retiming circuit A flip-flop circuit 3 is provided. Japanese Patent Laid-Open No. 1-190128 discloses a decoding circuit that uses a shift counter-structured ring counter using a plurality of flip-flop circuits for a sequential circuit as a timing generation source, and introduces the output to a logical operation circuit. Yes.
[0004]
[Problems to be solved by the invention]
However, in the timing pulse generation circuit of FIG. 10, when the output delay relationship between Q0 and Q1B of counter 1 is Q0 << Q1B, that is, as shown in the timing chart of FIG. When Q1B and the delay time differ from each other, a hazard (output change corresponding to the delay time difference of Q1B-Q0) occurs in the output of the 2-input OR gate 2. In the case of a CMOS process device, the hazard consumes power due to a change in gate output, and thus generates extra power.
[0005]
On the other hand, the decoding circuit using a ring counter disclosed in Japanese Patent Laid-Open No. 1-190128 has no phase shift and does not cause the above hazard. However, when generating n timings, n flip-flop circuits are required. The flip-flop circuit consumes a large amount of power, and when applied to a large-scale timing pulse generation circuit, the total power consumed by many flip-flop circuits is large.
[0006]
In view of this problem, an object of the present invention is to provide a decoding circuit that has no hazard and consumes less power.
[0007]
[Means for Solving the Problems]
A decoding circuit of the present invention that solves the above-described problem is a decoding circuit including at least one n-input OR gate (n is an integer of 3 or more), and one of the input signals is a clock signal , and the clock signal is The other operation signal is an output from the counter. In the decoding method of the present invention, when there is a delay time difference between the data signals input from the counter of the preceding stage in the n input OR gate (n is an integer of 3 or more), the OR gate has a timing preceding the data signal. Input the operation clock. Further, the timing pulse generation circuit of the present invention includes a counter and at least one n-input OR gate (n is an integer of 3 or more), and an operation clock of the counter and a counter output signal are input to the n-input OR gate.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a basic configuration example of a timing pulse generation circuit using a decoding circuit of the present invention. In FIG. 1, the OR gate to which the outputs Q and Q1B of the counter 1 are input is a three-input OR gate 4. The 3-input OR gate 4 receives a counter operation clock (CLK) in addition to the above two signals. The output of the 3-input OR gate 4 is input to the retiming flip-flop circuit 3.
[0009]
FIG. 2 is a timing chart of the above circuit. With respect to CLK, Q of 1/2 frequency and Q1B of 1/4 frequency are delayed by different delay times, and Q1B is delayed more greatly. The delay time difference between Q and Q1B should cause a hazard in the output signal of the 3-input OR gate 4, but the hazard factor part shown by the broken line in FIG. 2 is masked by "1" with the H pulse of CLK. For this reason, no hazard occurs in the output of the OR gate 3. At this time, in order to mask the delay time difference portion reliably, it is necessary that CLK is not delayed from Q and Q1B, and it is desirable that the delay is earlier.
[0010]
FIG. 3 shows an example of a timing pulse generation circuit having a 5-input OR gate decoding circuit. This circuit generates an “L” pulse once during CLK16 period. Counter 1 is a 4-bit binary up counter. The 5-input OR gate 5 receives four outputs Q0 to Q3 of the counter 1 and CLK for counter operation. Connected to the 5-input OR gate 5 is a retiming flip-flop circuit 3 for retiming the decoded pulse.
[0011]
FIG. 4 is a timing chart of this timing pulse generation circuit. The 4-bit binary up counter operation that operates at the rising edge of the clock is indicated by a decimal number (Q (3; 0)) of 0 to 15 in the bus format. The counter 1 repeats counting with 0 to 15 as one period. The waveform for each bit of Q0 to Q3 of the counter 1 is as shown in FIG. Here, the portion indicated by the broken line is a hazard factor in the conventional decoding circuit. That is, when the reverse change of the Q0-Q1 data and the delay relationship of Q0 << Q1 are established, both Q0 and Q1 become “0” and a hazard occurs. In this case, there is a possibility that a maximum of seven hazards occur as indicated by vertical lines in the conventional OR gate output chart. However, in the present invention, since the hazard factor portion is masked to “1” in the “H” pulse portion of CLK, no hazard is generated. As described above, it is desirable that CLK precede Q0 to Q3 (that is, earlier in delay).
[0012]
FIG. 5 is an enlarged view of a part of FIG. When Q0 and Q1 change in opposite directions with respect to CLK and have different delay times, hazards occur in the conventional OR circuit, but in the present invention, hazards occur because they are masked to "1" by CLK punching do not do.
[0013]
Next, a reference example of the decoding circuit of the present invention is shown. FIG. 6 shows an example of a timing pulse generation circuit using a NAND gate 6 in the decode circuit portion. This decoding circuit includes an inverter 7 in order to mask a data change point with an “L” pulse of inverted CLK. Further, as described above, it is desirable that CLK has an earlier timing than other data. A delay gate 8 is provided at the CLK input portion of the counter 1 in order to cancel the delay caused by the inverter 7. In addition, in order to decode “1” and “0” of the counters Q1 to Q0 by the NAND gate, Q1 and Q0B which are different from the case of the OR gate are input to the input of the NAND gate.
[0014]
FIG. 7 is a time chart of the timing pulse generation circuit. The “L” pulse of the clock inverted by the inverter 7 masks the hazard factor part (the part surrounded by the broken line in the figure) based on the delay time difference between Q0B and Q1, and no hazard appears in the NAND output.
[0015]
FIG. 8 shows an example of a timing pulse generation circuit having a decoding circuit having a multi-stage OR gate. This decoding circuit is composed of two 3-input OR gates 9 and 10 to which CLK is input and one 2-input OR gate 11. Q0 and Q1 of the 4-bit binary up counter 1 are input to one 3-input OR gate 9, and Q2 and Q4 are input to the other 3-input OR gate 10. The outputs of these two three-input OR gates 9 and 10 are input to the two-input OR gate 11.
[0016]
FIG. 9 is a timing chart of the circuit of FIG. The hazard factor portion due to Q0 and Q1 and the hazard factor portion due to Q2 and Q3 (both indicated by broken lines in FIG. 9) are masked by the “H” pulse of CLK. Since the clock has already been punched out by the three-input OR gates 9 and 10, there is no hazard at the output, and no hazard occurs at the output of the two-input OR gate 11.
[0017]
When the timing pulse generated by the timing pulse generation circuit is directly used as a clock of another flip-flop circuit, the conventional timing pulse generation circuit (for example, FIG. 10) has a hazard in the output of the decoding circuit. A flip-flop circuit is required. However, the timing pulse generation circuit using the decoding circuit of the present invention does not require a retiming flip-flop circuit because no hazard occurs in the output of the decoding circuit. The decoding circuit of the present invention further contributes to reduction of power consumption in that a retiming flip-flop circuit that always consumes power is not required.
[0018]
In a CMOS process device, power consumption can often be expressed as (frequency) × (unit power consumption per 1 MHz) × (number of gates) × (operation rate). In the example shown in FIG. 4, when comparing only the operation rate, if it is considered that the change of the conventional OR gate output 1 → 0 and the change of 0 → 1 occur once for each hazard, one cycle There is a maximum of 16 hit changes. When the decoding circuit of the present invention is applied, this change is twice per cycle, and the effect of reducing the power consumption to a maximum of 1/8 can be obtained.
[0019]
【The invention's effect】
In the present invention, the clock is input to the logic circuit constituting the decode circuit portion in the timing pulse generation circuit, and the delay time difference portion of the other input signals is masked with the clock, so that no hazard is generated. For this reason, it is possible to suppress excessive power consumption based on the operation of the logic circuit.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a timing pulse generation circuit using a decoding circuit of the present invention.
FIG. 2 is a timing chart of the timing pulse generation circuit of FIG.
FIG. 3 is a block diagram showing a configuration example of a timing pulse generation circuit using another decoding circuit of the present invention.
4 is a timing chart of the timing pulse generation circuit of FIG.
FIG. 5 is a timing chart in which a part of the timing chart of FIG. 4 is enlarged.
FIG. 6 is a block diagram showing a configuration example of a timing pulse generation circuit using a decoding circuit according to a reference example of the present invention.
7 is a timing chart of the timing pulse generation circuit of FIG.
FIG. 8 is a block diagram showing a configuration example of a timing pulse generation circuit using still another decoding circuit of the present invention.
9 is a timing chart of the timing pulse generation circuit of FIG.
FIG. 10 is a block diagram illustrating a configuration example of a timing pulse generation circuit using a conventional decoding circuit.
11 is a timing chart of the timing pulse generation circuit of FIG.
[Explanation of symbols]
1 Counter 2, 11 2-input OR gate 3 Retiming flip-flop circuit 4, 9, 10 3-input OR gate 5 5-input OR gate 6 NAND gate 7 Inverter 8 Delay gate

Claims (4)

A decoding circuit having at least one n-input OR gate (n is an integer of 3 or more) , wherein one of the input signals is a clock signal , and the clock signal is a clock for operating a counter arranged in the preceding stage. The other input signal is an output from the counter . 2. The decoding circuit according to claim 1, wherein the clock signal has a timing preceding other data input to the n-input OR gate . When there is a delay time difference between the data signals input from the counter of the preceding stage in the n-input OR gate (n is an integer of 3 or more), the operation clock of the counter whose timing precedes the data signal is input to the OR gate. A decoding method characterized by the above. A timing pulse generation circuit comprising a counter and at least one n-input OR gate (n is an integer of 3 or more), and an operation clock of the counter and a counter output signal are input to the n-input OR gate.

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