JP3570905B2 - Multiprocessor and multiprocessor control method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multiprocessor, and more particularly, to a multiprocessor that achieves low power consumption.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a multiprocessor has a plurality of processors and can perform a plurality of operations in parallel. Therefore, a multiprocessor is widely used to improve a processing speed.
[0003]
[Problems to be solved by the invention]
However, in the conventional multiprocessor as described above, even when the load on the entire system is extremely small, the clocks in all the processors operate in the same manner as at the peak, so that the operation is suspended (instructions are not executed). There is a problem that unnecessary power is consumed in the processor of (2).
[0004]
In recent years, the scale of the system has been increased, and the number of processors has increased, which has tended to further increase power consumption.
[0005]
On the other hand, socially, reduction of power consumption has been widely taken up as an environmental problem, and it has been required to suppress power consumption in spite of an increase in the scale of the device.
[0006]
Therefore, in a bus-connected multiprocessor system, there is a method of monitoring the bus and controlling the power. However, in order to realize a bus monitoring device, it is necessary to consider the configuration of the device connected to the bus, and a complicated HW is required. Is needed.
[0007]
The present invention has been made in view of the above-described problems of the conventional technology, and has as its object to provide a multiprocessor that can reduce power consumption.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a plurality of processors for processing a process generated when a program is executed, a memory unit for storing data required when the processes are executed by the plurality of processors, A multiprocessor including a network unit that connects each of the plurality of processors and the memory unit, and a clock generator that supplies a clock synchronized with a system to the plurality of processors and the memory unit; Each of the processors includes an instruction execution control unit that generates and controls an instruction for executing the process, an instruction idle counter that counts execution instruction stop time in the instruction execution control unit, and another processor via the network unit. And the memory unit At performs transmission and reception of data, when the count value in said instruction idle counter reaches a predetermined value or more, the flag indicating that the instruction execution control unit is an instruction execution stopped on the processor state flags A network interface unit that sets and releases the flag of the processor status flag when a process start notification is received via the network unit; and a clock supplied from the clock generator based on a status of the processor status flag. And a clock distribution control unit that controls supply to components of the processor except for the network interface unit .
[0009]
The clock distribution control unit may stop supplying a clock to components of the processor except the network interface unit when the flag is set in the processor state flag .
[0010]
Further, the clock distribution control unit restarts the supply of the clock to the components of the processor when the flag set in the processor state flag is released .
[0011]
Further, a plurality of processors for processing a process generated at the time of executing the program, a memory unit for storing data required when the processes are executed by the plurality of processors, and the plurality of processors and the memory unit. In a multiprocessor control method including a network unit connected to each of the plurality of processors and a clock generator that supplies a clock synchronized with a system to the plurality of processors and the memory unit, an execution instruction suspension time is predetermined. If the time is equal to or longer than the time, a flag indicating that the processor is in the instruction execution suspended state is set in the processor status flag, and when the processor receives a process start notification via the network unit, the processor status is set. releasing the flag in the flag , Characterized in that the clock supply to the processor is stopped when the flag to the processor state flag is set.
[0012]
Further, when the flag is set in the processor state flag, the supply of the clock supplied from the clock generator to the processor is stopped.
[0013]
When the flag set in the processor status flag is released, the supply of the clock supplied from the clock generator to the processor is restarted .
[0014]
(Action)
In the present invention configured as described above, in each of the plurality of processors constituting the multiprocessor system, the instruction execution state in the own device is monitored, and when a continuous stop state for a predetermined time is detected. Since the clock in the processor is stopped, unnecessary power is not consumed in the processor in the operation halt state.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0016]
FIG. 1 is a block diagram showing an embodiment of the multiprocessor of the present invention.
[0017]
In this embodiment, as shown in FIG. 1, a plurality of processors 1-1 to 1-n for processing a process generated when a program is executed, and a plurality of processors 1-1 to 1-n are required when the processes are executed. A memory unit 2 for storing data, a network unit 3 for connecting the processors 1-1 to 1-n and the memory unit 2, respectively, and a system for synchronizing the processors 1-1 to 1-n and the memory unit 2 with the system. And a clock generator 4 for supplying the generated clock. Since the form of the network unit 3 is not the essence of the present invention, any form such as a bus form or a crossbar form may be used.
[0018]
FIG. 2 is a block diagram showing a configuration of the processor 1-m shown in FIG. The processors 1-1 to 1-n all have the same configuration.
[0019]
As shown in FIG. 2, the processor 1-m according to the present embodiment includes an instruction execution control unit 11 for generating and controlling an instruction for executing a designated process allocated by an operating system (hereinafter, referred to as an OS), and an instruction execution control unit. 11, an instruction idle counter 12 for counting the execution instruction stop time, and data between the other processors 1-1 to 1-n and between the processor 1-m and the memory unit 2 via the network unit 3. A network interface unit 13 for outputting, a processor status flag 131 indicating a clock operating state in the processor 1-m, and a clock for monitoring the processor status flag 131 and controlling a clock supplied to a subunit in the own processor 1-m And at least a distribution control unit 14. 5 and VPU16 are provided.
[0020]
The network interface unit 13 transmits and receives data to and from the other processors 1-1 to 1-n or the memory unit 2.
[0021]
The processor status flag 131 refers to the processor halt status report sent from the instruction idle counter 12 and the process start notification received from the network unit 3 to determine the clock operation status in the processor 1-m and the clock distribution control unit 14. Output to
[0022]
The instruction execution control unit 11 refers to the process start notification received via the network interface unit 13 and performs generation and execution control of an instruction for executing an arbitrary process specified by the OS.
[0023]
The instruction idle counter 12 receives the instruction execution state transmitted from the instruction execution control unit 11 and counts a continuous instruction execution stop time. When the instruction execution suspension state has continued for a certain period of time, the processor 1-m determines that the processor 1-m is in the idle state, and transmits a processor suspension state report to the processor state flag 131.
[0024]
Further, the clock distribution control unit 14 receives a clock synchronized in the entire system from the clock generator 4, refers to the processor state flag 131, and controls the distribution of the clock to each subunit in the processor 1-m.
[0025]
Hereinafter, the operation of the multiprocessor configured as described above will be described.
[0026]
The clock generator 4 sends a synchronized clock to each unit. The plurality of processors 1-1 to 1-n and the memory unit 2 receive the clock output from the clock generator 4, and operate in synchronization with the clock.
[0027]
The OS manages a plurality of processes executed by the processors 1-1 to 1-n. When the execution of the program is started, the OS performs scheduling of a group of processes constituting the program, and allocates a process to the processor 1-m. The process activation method for the processor is not the essence of the present invention.
[0028]
In the present embodiment, a process starting method by inter-processor communication via a network will be described as an example of a process starting method.
[0029]
When the scheduling of the process group is performed in the OS and the process is allocated to the processors 1-1 to 1-n, the process start communication data is transmitted to the processor 1-m via the network unit 3.
[0030]
When the processor 1-m receives the process start communication data addressed to itself transmitted via the network unit 3, the processor 1-m starts the process processing by referring to the process start communication data.
[0031]
After the completion of the process processing, when the processor 1-m detects that there is no instruction executed in the own processor within a predetermined time, a part of the clock in the processor 1-m is stopped, and the clock is stopped. Transitions to.
[0032]
Thereafter, when the processor 1-m in the clock stopped state receives the process start communication data addressed to itself, the stopped clock path inside the processor is reactivated, and the process allocated by the OS is executed. .
[0033]
Next, the operation in the processor 1-m will be described in detail.
[0034]
When the execution of the program is started, scheduling is performed on the generated process in the OS, and the generated process is assigned to the processor 1-m.
[0035]
When the process assignment is completed, process start communication data is transmitted to the processor 1-m via the network unit 3.
[0036]
The process start communication data transmitted to the processor 1-m is received by the network interface 13 in the processor 1-m.
[0037]
When the process start communication data is received by the network interface 13, the received process start communication data is transmitted from the network interface 13 to the instruction execution control unit 11 in the processor 1-m.
[0038]
When the process start communication data transmitted from the network interface 13 is received by the instruction execution control unit 11, the instruction execution control unit 11 sends a data load request for the memory address specified by the process start communication data to the memory unit 2. Issued for
[0039]
The data load request issued by the instruction execution control unit 11 is received by the memory unit 2 via the network interface unit 13 and the network unit 3 and is sent to the memory unit 2 at the address specified by the data load request. The stored data is extracted and output to the processor 1-m via the network unit 3.
[0040]
The load data output from the memory unit 2 is received by the instruction execution control unit 11 via the network unit 3 and the network interface unit 13, and the instruction execution control unit 11 refers to the received load data, and the OS executes The assigned process is executed at the instruction level.
[0041]
Here, in the instruction idle counter 12, the instruction issue state in the instruction execution control unit 11 is monitored, and the instruction execution stop time in the processor 1-m is counted.
[0042]
If the next process does not occur for a long time after the completion of the process, the processor 1-m is determined to be in an idle state when the instruction idle counter 12 detects a predetermined number of continuous instruction execution suspension times. Then, idle state notification data is output to the network interface unit 13.
[0043]
When the idle state notification data output from the instruction idle counter 12 is received by the network interface unit 13, the processor state flag 131 is set in the network interface unit 13. Although the processor status flag 131 is provided in the network interface 12 in the present embodiment, the processor status flag 131 is not necessarily provided in the network interface unit 13 at the position of the processor status flag 131.
[0044]
The clock distribution control unit 14 receives the clock generated by the clock generator 4, and distributes and controls the clock to the subunits constituting each processor.
[0045]
When the processor status flag 131 provided in the network interface unit 13 is set, in the clock distribution control unit 14, the sub-units (in the present embodiment, the instruction execution control unit 11, the Cache 15, and the VPU 16) except the network interface unit 13 are set. The clock is fixed in the HI state (or the LO state) with respect to the clock distribution path. In the memory / register in the sub-unit where the clock is stopped, the state at the time when the clock is fixed is held.
[0046]
Thereafter, when a new process occurs, scheduling of the generated process is performed in the OS, and process activation communication data is transmitted to the processor 1-m.
[0047]
The network interface unit 13 in the processor 1-m receives the process start communication data addressed to itself via the network unit 3.
[0048]
When the processor 1-m is in the clock stop state, the processor state flag 131 is reset in the network interface unit 13 when the process start communication data is received.
[0049]
In the clock distribution control unit 14, the processor state flag 131 is monitored, and the held clock path is activated.
[0050]
When the clock is activated, the process start communication data is transmitted from the network interface unit 13 to the instruction execution control unit 11.
[0051]
When the process start communication data transmitted from the network interface 13 is received by the instruction execution control unit 11, the instruction execution control unit 11 stores the data in the memory unit 2 at the memory address indicated in the process start communication data. The requested data load request is issued, and the instruction sequence of the designated process is executed in the same manner as the above-described operation.
[0052]
【The invention's effect】
As described above, in the present invention, in each of a plurality of processors constituting a multiprocessor system, an instruction execution state in the own apparatus is monitored, and when a continuous stop state for a predetermined time is detected, the processor Since the internal clock is stopped, useless power is not consumed in the processor in the operation halt state, and power consumption can be reduced.
[0053]
2. Description of the Related Art In a synchronous circuit employing a CMOS circuit, which is often used in recent technologies, power consumption can be reduced by stopping a clock supplied to the synchronous circuit and fixing circuit data.
[0054]
In a multiprocessor system, by controlling the internal clock operation for each processor with a relatively simple circuit, delicate power consumption control can be performed even in a large-scale system.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an embodiment of a multiprocessor according to the present invention.
FIG. 2 is a block diagram illustrating a configuration of a processor illustrated in FIG. 1;
[Explanation of symbols]
1-1 to 1-n Processor 2 Memory unit 3 Network unit 4 Clock generator 11 Instruction execution control unit 12 Instruction idle counter 13 Network interface unit 14 Clock distribution control unit 15 Cache
16 VPU

Claims (5)

A plurality of processors that process processes that occur during program execution, a memory unit that stores data required when the processes are executed by the plurality of processors, and a connection between the plurality of processors and the memory unit, respectively A multi-processor comprising a network unit and a clock generator that supplies a clock synchronized with a system to the plurality of processors and the memory unit.
Each of the plurality of processors,
An instruction execution control unit for generating and controlling instructions for executing the process;
An instruction idle counter for counting an execution instruction stop time in the instruction execution control unit;
While transmitting and receiving data to and from another processor and the memory unit via the network unit, when the count value in the instruction idle counter is equal to or greater than a predetermined value, the instruction execution control unit A network interface unit that sets a flag indicating that the instruction execution is stopped in the processor status flag, and releases the flag of the processor status flag when a process start notification is received via the network unit.
A multiprocessor comprising: a clock distribution controller configured to control supply of a clock supplied from the clock generator to components of the processor except the network interface unit based on a state of the processor state flag. The multiprocessor according to claim 1,
The multiprocessor according to claim 1, wherein the clock distribution control unit stops supplying a clock to components of the processor except the network interface unit when the processor status flag is set. The multiprocessor according to claim 2,
The multiprocessor according to claim 1, wherein the clock distribution control unit restarts supply of a clock to a component of the processor when the flag set in the processor state flag is released. A plurality of processors that process processes that occur during program execution, a memory unit that stores data required when the processes are executed by the plurality of processors, and a connection between the plurality of processors and the memory unit, respectively A multi-processor control method, comprising: a network unit that performs the operation and a clock generator that supplies a clock synchronized with a system to the plurality of processors and the memory unit.
Each of the plurality of processors has an instruction idle counter for counting an execution instruction stop time in the instruction execution control unit, and a network interface unit,
If the count value in the instruction idle counter is equal to or greater than a predetermined value , the network interface unit sets a flag indicating that the processor is in the instruction execution suspended state in a processor state flag, and the processor sets When the process start notification is received via the network unit, the flag of the processor state flag is released,
Control method for a multiprocessor, characterized in that stops the clock supply for the components of this the processor except for the network interface unit if the flag to the processor state flag is set. The method for controlling a multiprocessor according to claim 4 ,
When the flag set in the processor status flag is released, the supply of the clock supplied from the clock generator to the processor is restarted.

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