JP3582666B2 - Orthogonal frequency multiplex signal demodulator - Google Patents

Description

ただしｍは整数であり、ｘも整数となる様にする。実用的には窓移相量ｘが大きいと窓位相制御に対し誤差を発生するのでｍはあまり大きな値は望ましくない。
【００４１】
以上の構成によれば、前述の第１〜第３の実施例同様、従来回路のようにＤＦＴ時間窓生成回路による位相制御がクロツク再生回路において位相誤差として誤検出されるおそれのない直交周波数多重復号装置を得ることができる。
【００４２】
（５）他の実施例
なお上述の第１の実施例〜第３の実施例においては、窓移相量ｘを時間経過に対して任意に可変する場合について述べたが、本発明はこれに限らず、窓移相量ｘを時間経過に対して一定としても良い。このようにすれば位相制御信号Ｐ_ＣＯＮＴを省略することができる。ただし第３の実施例の場合には第４の実施例と同じ構成となる。また第１及び第２の実施例については位相回転量が一定となるので位相誤差補正回路における処理を固定にすれば良い。
【００４３】
また上述の第１〜第３の実施例においては、ＤＦＴ時間窓生成回路による窓位相の移相量に応じてクロツク再生回路内における位相誤差検出回路部の位相誤差を補正し、また上述の第４の実施例においてはＤＦＴ時間窓生成回路による窓位相の移相量としてクロツク再生回路内における位相誤差検出回路部への位相誤差を生じさせないものを選択する場合について述べたが、本発明はこれに限らず、搬送波再生回路内に設けられる位相誤差検出回路についても位相誤差を補正し又は位相誤差を生じさせない一定の関係に制御しても良い。
【００４４】
【発明の効果】
上述のように本発明によれば、窓位相制御手段が時間窓の位相を移相する場合にはこれに同期して位相誤差検出部が検出する位相誤差を補正することにより、時間窓の移相によつて位相誤差検出部における判定結果に誤差が重畳されないようにすることができる。これにより短時間のうちに正確なクロツク信号を再生することができる。
【００４５】
また上述のように本発明によれば、窓位相制御手段による時間窓の移相量及び位相誤差検出部が位相誤差の検出に用いる搬送波を一定の関係を有するものに限定したことにより、時間窓の移相が位相誤差検出部において位相誤差として現れないようにすることができる。これにより短時間のうちに正確なクロツク信号を再生することができる。
【図面の簡単な説明】
【図１】本発明による直交周波数多重復調装置の一実施例を示すブロツク図である。
【図２】本発明による直交周波数多重復調装置の一実施例を示すブロツク図である。
【図３】本発明による直交周波数多重復調装置の一実施例を示すブロツク図である。
【図４】本発明による直交周波数多重復調装置の一実施例を示すブロツク図である。
【図５】直交周波数多重方式による各搬送信号を示す略線図である。
【図６】従来の直交周波数多重変調装置の構成を示すブロツク図である。
【図７】従来の直交周波数多重復調装置の構成を示すブロツク図である。
【図８】従来用いられているＤＦＴ時間窓生成回路及びクロツク再生回路の構成を示すブロツク図である。
【符号の説明】
１……直交周波数多重変調装置、２１……直交周波数多重復調装置、４２、５２、６２、７２……クロツク再生回路、４２Ａ、７２Ａ、８２Ａ……選択回路、４２Ｂ……位相誤差検出回路、４２Ｃ……ローパスフイルタ、４２Ｄ……ＶＣＯ回路、４３、５３、６３、７３、８３……ＤＦＴ時間窓生成回路、５２Ａ、６２Ａ……位相誤差補正回路。[0001]
【table of contents】
The present invention will be described in the following order.
Industrial application field Conventional technology (FIGS. 5 to 8)
Means for Solving the Problems to be Solved by the Invention (FIGS. 1 to 4)
Working Example (FIGS. 1 to 4)
(1) First embodiment (FIG. 1)
(2) Second embodiment (FIG. 2)
(3) Third embodiment (FIG. 3)
(4) Fourth embodiment (FIG. 4)
(5) Effects of other embodiments of the invention
[Industrial applications]
The present invention relates to an orthogonal frequency division multiplex signal demodulation apparatus, and more particularly to a DFT time window generation circuit and a clock signal reproduction circuit for converting an orthogonal frequency division multiplex (OFDM) signal from a time domain signal to a frequency band signal. It is.
[0003]
[Prior art]
When transmitting a digital signal, a method of phase-modulating and amplitude-modulating a single-frequency carrier signal based on the digital signal is generally used.
As such a modulation method, a phase shift keying (PSK) method that changes only the phase and a quadrature amplitude modulation (QAM) method that changes both the phase and the amplitude are often used.
[0004]
In each of these modulation methods, a carrier signal of a single frequency is modulated so as to have an occupied bandwidth that can be accommodated in a transmission band. On the other hand, recently, a modulation scheme called an orthogonal frequency multiplexing scheme has been proposed as a new modulation scheme.
This orthogonal frequency multiplexing system generates a plurality of orthogonal carrier signals within a transmission band, divides the transmission band, and modulates each carrier signal based on a digital signal by phase modulation (PSK) or quadrature modulation (QAM). It is.
[0005]
In the case of this modulation method, the transmission band is divided by a plurality of carrier signals, so that the bandwidth per carrier signal is reduced. Therefore, the modulation speed per carrier signal becomes slow. However, when the transmission bands are the same, the overall transmission speed obtained as a result of modulating a plurality of carrier signals is not different from that of the conventional modulation.
[0006]
Also, in this method, a number of carrier signals are transmitted in parallel, so that the speed per symbol is reduced. Therefore, it is possible to reduce the delay time of the multipath interference wave relative to the symbol time length in the transmission path where the multipath interference exists. Therefore, this system is less susceptible to multipath interference, and due to this feature, particular attention is paid to the transmission of digital signals by terrestrial waves.
[0007]
The orthogonal frequency multiplexing signal processing requires high-speed discrete Fourier transform and discrete inverse Fourier transform. In this regard, recent advances in semiconductor technology have provided semiconductor devices capable of performing discrete Fourier transform and inverse discrete Fourier transform by hardware-based processing, which have been difficult in the past. By using such an element, it is possible to easily perform orthogonal frequency multiplexing modulation or demodulate a signal modulated by this modulation method. Such advance in semiconductor technology is also one of the reasons why the orthogonal frequency multiplexing system is receiving attention.
[0008]
Next, a general orthogonal frequency multiplexing method will be described. Orthogonal frequency multiplexing is characterized by generating a carrier signal that is orthogonal for each predetermined bandwidth obtained by dividing the transmission channel (transmission band), and is a digital signal with a low data rate such that the modulated signal fits in each bandwidth. The point is that modulation of all carrier signals is performed collectively by discrete inverse Fourier transform (IDFT) instead of modulating each carrier signal with a digital signal.
[0009]
Hereinafter, the orthogonal frequency multiplexing method will be described with reference to FIG. The figure shows how information is transmitted by each carrier signal in the orthogonal frequency multiplexing system. Here #k (k is an integer) indicates a carrier signal waveform of the period T _{s /} k in the signal each time interval (symbol interval) T _s as shown in, be transmitted each column of (a), (b) 3 shows a carrier signal waveform when power information values are 1 and 0. And symbol time time interval T _s with a predetermined In this connection.
[0010]
#. 1 to # n is the carrier signal with a period _{T s} ~ period _T s / n, respectively. Assuming that such carrier signals # 1 to #n are arranged in order, if the amplitude and phase of each of these carrier signals is defined by the information to be transmitted, the symbol waveform is defined by the information to be transmitted (digital signal). can do.
For example, if a signal having a waveform shown in FIG. 5A is associated with a logical value 1 and a signal having a waveform shown in FIG. 5B is associated with a logical value 0, information (digital signal) is transmitted for each carrier signal. be able to.
[0011]
In the example shown in FIG. 5, each carrier signal is modulated by a so-called BPSK defined in two phase states, and one bit of information is transmitted for each carrier signal, but more phase signals are transmitted for each carrier signal. It is also possible to define multi-values and amplitudes and transmit them. That is, the waveform can be obtained by defining the amplitude and phase of each carrier signal.
[0012]
The processing operation for obtaining this waveform is a so-called inverse Fourier transform. Therefore, in the orthogonal frequency multiplexing method, a method of obtaining an orthogonal frequency multiplexing signal using a discrete inverse Fourier transform circuit is used.
Hereinafter, the modulation operation by the orthogonal frequency multiplex modulation apparatus 1 will be described with reference to FIG. First, the serial / parallel conversion circuits 2 and 3 convert the I-channel signal and the Q-channel signal in the serial data format into parallel data format, respectively. A discrete inverse Fourier transform (IDFT) circuit 4 receives an I-channel signal and a Q-channel signal converted into a parallel data format, and converts them into a time-domain signal by performing a discrete inverse Fourier transform. I do.
[0013]
The parallel / serial conversion circuits 5 and 6 convert the time domain signal in the parallel data format input from the discrete inverse Fourier conversion circuit 4 into a serial signal in time, and provide the signals to the buffer memories 7 and 8. Buffer memories 7 and 8 add guard intervals to the input signals and provide the signals to digital / analog conversion circuits 9 and 10. These signals to which the guard intervals are added are converted into analog signals by digital / analog conversion circuits 9 and 10 and input to low-pass filters 11 and 12.
[0014]
The low-pass filters 11 and 12 remove aliasing signal components from these signals and supply the signals to the multiplication circuits 13 and 14.
Here, the multiplying circuit 13 multiplies the signal input from the low-pass filter 11 by the carrier signal output from the local oscillator 15 and outputs the result. Further, the multiplying circuit 14 multiplies the signal output from the low-pass filter 12 by a carrier signal obtained by shifting the carrier signal output from the local oscillator 15 by 90 ° through a 90 ° phase shift circuit 16 and outputs the result.
[0015]
The addition circuit 17 receives the multiplication outputs from the multiplication circuits 13 and 14, performs addition and synthesis, and outputs the result to the bandpass filter 18.
The bandpass filter 18 limits the input synthesized signal to a predetermined bandwidth and outputs the resultant signal to the RF converter 19. The RF converter 19 converts the frequency of the band-limited signal to a desired frequency and outputs the signal via the transmission antenna 20. A desired signal is subjected to orthogonal frequency multiplex modulation by these series of processing operations and transmitted.
[0016]
Subsequently, the processing operation of the orthogonal frequency multiplex demodulation device 21 for decoding the orthogonal frequency multiplex modulation signal will be described with reference to FIG.
The RF signal captured by the antenna 22 is input to the tuner 23, where it is frequency-converted and converted into an intermediate frequency band signal. Further, the tuner 23 amplifies the frequency-converted signal and supplies it to the multiplication circuits 24 and 25. The multiplying circuit 24 multiplies the signal received from the tuner 23 by the carrier signal output from the local oscillator 26 and outputs the result. On the other hand, the multiplying circuit 25 multiplies the signal fetched from the tuner 23 by the carrier signal output from the local oscillator 26 by a 90 ° phase shift circuit 27 by a 90 ° phase shifter, and outputs the product.
[0017]
The signals in the intermediate frequency band are converted into baseband signals by the multiplier circuits 24 and 25. Unnecessary harmonic components are removed from these baseband signals by low-pass filters 28 and 29, respectively, and are input to analog / digital conversion circuits 30 and 31. The analog / digital conversion circuits 30 and 31 convert the baseband signals into digital signals and output the signals to serial / parallel conversion circuits 32 and 33, respectively.
[0018]
The discrete Fourier transform circuit 34 performs discrete Fourier transform (DFT) on the signal converted into the parallel data format, and provides the signals to parallel / serial converters 35 and 36. The parallel data format signals are converted into serial data format signals by the parallel / serial conversion circuits 35 and 36 and supplied to buffer memories 37 and 38. The buffer memories 37 and 38 execute various processes such as a guard interval elimination process and output as digital channel I-channel signals and Q-channel signals. The orthogonal frequency multiplexing decoding device 21 decodes the orthogonal frequency multiplexing signal by a series of these processes.
[0019]
By the way, in order for the orthogonal frequency multiplexing decoding device 21 to accurately demodulate the received signal, the local oscillator 26 can oscillate at an appropriate oscillation frequency, the sampling timing of the analog / digital conversion circuit 30 is accurate, and the discrete Fourier Three requirements are required that the window synchronization phase in the conversion circuit 34 be accurate.
[0020]
Therefore, the orthogonal frequency multiplexing decoding device 21 supplies the DFT-processed signals output from the parallel / serial conversion circuits 35 and 36 to the carrier recovery circuit 39, the digital / analog conversion circuit 40, The signal is fed back to the local oscillator 26 via a Costas loop constituted by a low-pass filter 41. The configuration using this Costas loop is general, and the local oscillator 26 can reproduce a carrier signal having the same frequency as the transmitting side.
[0021]
The orthogonal frequency multiplexing decoding device 21 is provided with a clock reproduction circuit (BTR) 42 and a DFT time window generation circuit (WR) 43 for the second and third requirements. The detailed configuration is shown in FIG.
The DFT time window generation circuit (WR) 43 detects a window synchronization signal included in the orthogonal frequency multiplexed signal from the signal after the DFT processing, and discretely _converts a window phase control signal W _CONT corresponding to the window phase state. By outputting the data to the Fourier transform circuit 34, the timing at which data is converted from the time domain to the frequency domain is not shifted. The window synchronization signal is a signal inserted at the transmission side as a no-signal at the head of the frame.
[0022]
On the other hand, the clock reproduction circuit 42 supplies the phase control signal selected by the first-stage selection circuit 42A to the phase error detection section 42B, and compares the phase control signal with a predetermined reference signal in the phase error detection circuit 42B. Is detected. The detected phase shift signal is supplied to the VCO circuit 42D via the low-pass filter 42C, and the oscillation phase of the VCO circuit 42D is controlled so that the clock CK has an appropriate phase.
[0023]
[Problems to be solved by the invention]
By the way, in the case of the conventional circuit, the DFT time window generating circuit 43 and the clock reproducing circuit 42 operate independently. Moreover, there is no relationship between the window phase shift amount based on the window phase control signal W _CONT and the phase error information output from the phase error detection circuit 42B. Accordingly, the phase rotation of the phase control signal caused by the window phase control may be judged as a phase error of the input signal in the clock reproducing circuit 42. This means that it is inevitable that the phase of the clock CK is shifted while the correct processing operation can be performed by controlling the window phase.
[0024]
The present invention has been made in view of the above points, and has as its object to propose an orthogonal frequency multiplexed signal demodulation apparatus capable of performing signal processing with a smaller phase error than in the related art.
[0025]
[Means for Solving the Problems]
In order to solve such a problem, in the present invention, frequency conversion means (24) and (25) for converting an orthogonal frequency multiplexed signal to a baseband signal, and arithmetic means (34) for converting the baseband signal from a time domain to a frequency domain. And a window phase control means (53) for controlling a phase of a time window used to cut out a signal of a processing unit from a baseband signal based on an output signal of the calculation means (34). And a clock recovery circuit (52) for inputting an output signal of the calculating means (34) to recover a clock signal (CK) and / or for inputting an output signal of the calculating means (34) and receiving a carrier of an orthogonal frequency multiplexed signal. Phase error correction means for correcting the phase error detected by the phase error detection unit in the carrier wave recovery circuit for recovering the phase error in accordance with the phase shift amount of the time window by the window phase control means (53). Kick.
[0026]
Further, in the present invention, frequency conversion means (24) and (25) for converting an orthogonal frequency multiplexed signal to a baseband signal, calculation means (34) for converting a baseband signal from a time domain to a frequency domain, and a calculation means (34) a quadrature frequency division multiplexing signal demodulation device having a window phase control means (83) for controlling a phase of a time window used to cut out a signal of a processing unit from a baseband signal based on the output signal of (34); The control amount for controlling the phase shift amount of the window phase given by the means (83) to the calculating means (34) is a fixed value, and the output signal of the calculating means (34) is input to reproduce the clock signal (CK). A carrier to be taken into a phase error detection unit in a carrier recovery circuit that receives the output signal of the recovery circuit (82) and / or the arithmetic means (34) and recovers the carrier of the orthogonal frequency multiplexed signal is The value to be limited to the particular carrier with a certain relationship.
[0027]
[Action]
When the window phase control means (53) shifts the phase of the time window, the phase error detected by the phase error detection unit can be corrected in synchronization with the phase shift. This eliminates the possibility that the phase error detection section makes an erroneous determination as if there is a phase error even though the phase of the clock signal (CK) is controlled to be accurate.
[0028]
Further, the phase shift amount of the time window by the window phase control means (83) and the carrier used by the phase error detection unit for detecting the phase error are limited to those having a fixed relationship, so that the phase shift of the time window is detected by the phase error detection. In such a case, it is possible to prevent the phase error from appearing in the section.
[0029]
【Example】
An embodiment of the present invention will be described below in detail with reference to the drawings.
[0030]
(1) First Embodiment In FIG. 1, parts corresponding to those in FIG. 8 are denoted by the same reference numerals, and reference numerals 52 and 53 denote a clock reproduction circuit and a DFT time window generation circuit among the circuit blocks constituting the orthogonal frequency multiplexing decoder. Each circuit is shown.
The clock reproduction circuit 52 used in this embodiment has the same configuration as that of the clock reproduction circuit 42 except that a phase error correction circuit 52A is provided between the selection circuit 42A and the phase error detection circuit 42B.
The DFT time window generation circuit 53 is the same as the DFT time window generation circuit 43 except that the DFT time window generation circuit 53 is configured to output a phase correction control signal P _CONT corresponding to the window phase control signal W _CONT to the clock reproduction circuit 52. It has a configuration.
[0031]
In the above configuration, the clock reproduction operation and the time window phase shift operation by the clock reproduction circuit 52 and the DFT time window generation circuit 53 will be described.
When the DFT time window generation circuit 53 receives the window synchronization signal from the outputs of the parallel / serial conversion circuits 35 and 36, the DFT time window generation circuit 53 generates a window phase corresponding to the state of the window phase in the DFT circuit 34 based on the input window synchronization signal. The control signal W _CONT is output from the output terminal. The phase correction control signal P _CONT corresponding to the window phase control signal W _CONT is output to the phase error correction circuit 52A of the clock reproduction circuit 52.
[0032]
At this time, the phase error correction circuit 52A corrects the phase of the phase control signal selected by the selection circuit 42A based on the phase correction control signal P _CONT and outputs this to the phase error detection circuit 42B. As a result, a phase control signal corrected in advance by an amount corresponding to the phase shift of the window phase by the phase correction control signal P _CONT is input to the phase error detection circuit 42B.
Accordingly, in the phase error detection circuit 42B, only the phase error that cannot be removed even by the phase shift of the window phase is detected, and this is supplied to the low-pass filter 42C as the phase error information. As a result, the phase of the clock signal CK output from the VCO circuit 42D quickly shifts to an accurate phase state.
[0033]
According to the above configuration, it is possible to obtain an orthogonal frequency multiplexing decoding device that can further increase the operation speed as compared with the related art and can realize accurate reference signal reproduction in a short time. Further, the detection error of the phase error detection circuit 42B can be suppressed as compared with the related art, and the accuracy can be improved.
[0034]
(2) Second Embodiment In this embodiment, as shown in FIG. 2, the phase error correction circuit 62A is not provided between the selection circuit 42A and the phase error detection circuit 42B, but is provided between the phase error detection circuit 42B and the low-pass filter 42C. The configuration is the same as that of FIG. The difference from FIG. 1 is that the detection result of the phase error detection circuit 42B still includes the error caused by shifting the window phase, and the phase shift error information based on the phase shift of the window phase is a low-pass filter. This is a point that is corrected immediately before being given to 42C.
With the above configuration, the same effect as that of the first embodiment can be obtained.
[0035]
(3) Third Embodiment In FIG. 3, parts corresponding to those in FIG. 8 are denoted by the same reference numerals, and 72 and 73 are a clock reproduction circuit and a DFT time window generation circuit among the circuit blocks constituting the orthogonal frequency multiplex decoding apparatus. Each circuit is shown.
The clock reproducing circuit 72 used in this embodiment is characterized in that a phase control signal used for reproducing the clock signal CK is appropriately selected based on the phase correction control signal P _CONT input from the DFT time window generating circuit 53. Incidentally, the phase correction control signal P _CONT is a signal output corresponding to the window phase control signal W _CONT , and the phase control signal is a plurality of carrier signals in which an orthogonal relationship is established.
[0036]
For example, when the DFT time window generation circuit 53 advances the window phase, the clock recovery circuit 72 selects a carrier signal having a higher frequency by an amount corresponding to the phase shift amount of the window phase based on the phase correction control signal P _CONT. On the other hand, when the DFT time window generation circuit 73 delays the window phase, the clock reproduction circuit 72 selects a carrier signal having a lower frequency by an amount corresponding to the phase shift amount of the window phase based on the phase correction control signal P _CONT. Works.
Also in this case, as in the first and second embodiments, the orthogonal frequency multiplexing decoding device can further increase the operation speed as compared with the related art, and can realize accurate reference signal reproduction in a short time. Can be obtained. Further, the detection error of the phase error detection circuit 42B can be suppressed as compared with the related art, and the accuracy can be improved.
[0037]
(4) Fourth Embodiment FIG. 4 shows a fourth embodiment. In this embodiment, the value of the window phase control signal W _CONT output from the DFT time window generation circuit 83 is fixed to a constant value instead of an arbitrary value, and the phase control signal (carrier wave) selected by the selection circuit 82A of the clock reproduction circuit 82 is selected. ) Is limited to those having a fixed relationship with the window phase control signal. In other words, a feature is used in which the window phase shift amount by the window phase control signal W _CONT does not appear as a phase error (= correction amount 0) in relation to the phase control signal selected by the selection circuit 82A.
[0038]
For example, if the phase shift amount of the window phase is ± 5 ° and the phase shift appearing in the phase control signal f is not detected as a phase error, even if the window phase shift detected by the DFT time window generation circuit 38 is, By instructing a delay of 5 ° as the window phase control signal W _CONT even for a lead of 3 °, the phase control of the DFT time window generating circuit 83 is prevented from affecting the phase detection of the clock reproducing circuit 82. ing.
[0039]
A method for obtaining the window phase shift amount x and the phase control signal (n-times carrier) satisfying the above relationship will be described below. When a Costas loop is used to detect a phase error, phase control is performed in units of 90 °. When 1024 points of conversion are performed in the DFT processing used for demodulation, the lowest carrier shows 360 ° at 1024 points. For this double carrier, 512 points indicate 360 °. When k-point conversion is used for demodulation in this way, 360 degrees are shown at k / n points for an n-times carrier. That is, this is a case where the n-th data is selected by the selection circuit 82A.
[0040]
When the window phase shift amount is x points, the amount of phase rotation applied to the n-times carrier by this control is (360 ° / (k / n)) × x. The value obtained by converting the rotation amount in units of 90 ° is the error correction amount. The converted value is the remainder when the phase rotation amount is divided by 90 °. A third embodiment is a case where the error correction amount is 0 ° and n and x are constant. That is, this is the case where the window phase shift amount x is (mk) / (4n) points. This is obtained from the following equation.
(Equation 1)

However, m is an integer and x is also an integer. Practically, if the window phase shift amount x is large, an error occurs in the window phase control, so that a too large value of m is not desirable.
[0041]
According to the above configuration, similarly to the above-described first to third embodiments, the orthogonal frequency multiplexing in which the phase control by the DFT time window generating circuit is not likely to be erroneously detected as a phase error in the clock reproducing circuit as in the conventional circuit. A decoding device can be obtained.
[0042]
(5) Other Embodiments In the first to third embodiments described above, the case where the window phase shift amount x is arbitrarily changed with the passage of time has been described. The present invention is not limited to this, and the window phase shift amount x may be constant with time. By doing so, the phase control signal P _CONT can be omitted. However, in the case of the third embodiment, the configuration is the same as that of the fourth embodiment. In the first and second embodiments, since the amount of phase rotation is constant, the processing in the phase error correction circuit may be fixed.
[0043]
In the first to third embodiments, the phase error of the phase error detecting circuit in the clock reproducing circuit is corrected in accordance with the amount of phase shift of the window phase by the DFT time window generating circuit. In the fourth embodiment, a case is described in which the phase shift amount of the window phase by the DFT time window generation circuit is selected so as not to cause a phase error to the phase error detection circuit in the clock reproduction circuit. However, the present invention is not limited to this, and the phase error detection circuit provided in the carrier wave recovery circuit may be controlled so as to correct the phase error or to have a fixed relationship that does not cause the phase error.
[0044]
【The invention's effect】
As described above, according to the present invention, when the window phase control means shifts the phase of the time window, the phase error detected by the phase error detection unit is corrected in synchronization with the shift, thereby shifting the time window. It is possible to prevent the error from being superimposed on the judgment result in the phase error detecting section depending on the phase. As a result, an accurate clock signal can be reproduced in a short time.
[0045]
As described above, according to the present invention, the phase shift amount of the time window by the window phase control means and the carrier used for the phase error detection by the phase error detection unit are limited to those having a fixed relationship, so that the time window Can be prevented from appearing as a phase error in the phase error detection unit. As a result, an accurate clock signal can be reproduced in a short time.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of an orthogonal frequency multiplex demodulator according to the present invention.
FIG. 2 is a block diagram showing an embodiment of an orthogonal frequency multiplex demodulator according to the present invention.
FIG. 3 is a block diagram showing an embodiment of an orthogonal frequency multiplexing demodulator according to the present invention.
FIG. 4 is a block diagram showing an embodiment of an orthogonal frequency multiplex demodulator according to the present invention.
FIG. 5 is a schematic diagram illustrating carrier signals according to the orthogonal frequency multiplexing method.
FIG. 6 is a block diagram showing a configuration of a conventional orthogonal frequency multiplex modulation apparatus.
FIG. 7 is a block diagram showing a configuration of a conventional orthogonal frequency multiplexing demodulator.
FIG. 8 is a block diagram showing a configuration of a conventionally used DFT time window generation circuit and a clock reproduction circuit.
[Explanation of symbols]
1 orthogonal frequency multiplex modulation device, 21 orthogonal frequency multiplex demodulation device, 42, 52, 62, 72 clock recovery circuit, 42A, 72A, 82A selection circuit, 42B phase error detection circuit, 42C ... Low-pass filter, 42D VCO circuit, 43, 53, 63, 73, 83 DFT time window generation circuit 52A, 62A phase error correction circuit.

Claims (5)

Frequency conversion means for converting an orthogonal frequency multiplexed signal into a baseband signal, calculation means for converting the baseband signal from the time domain to the frequency domain, and processing units from the baseband signal based on an output signal of the calculation means. In a quadrature frequency multiplexed signal demodulator having window phase control means for controlling the phase of a time window used to cut out a signal,
A clock recovery circuit for inputting an output signal of the arithmetic means and reproducing a clock signal, and / or a phase error detection in a carrier recovery circuit for inputting an output signal of the arithmetic means and reproducing a carrier of the orthogonal frequency multiplexed signal. A quadrature frequency multiplexing signal demodulation device, comprising: a phase error correction unit that corrects a phase error detected by a unit in accordance with a phase shift amount of the time window by the window phase control unit. 2. The quadrature according to claim 1, wherein the phase error correction unit shifts a phase of an output signal of the calculation unit input to the phase error detection unit according to a phase shift amount of the time window. Frequency multiplex signal demodulator. 2. The quadrature frequency multiplexed signal demodulator according to claim 1, wherein the phase error correction unit corrects a phase error detection output output from the phase error detection unit according to a phase shift amount of the time window. . 2. The orthogonal frequency multiplexed signal demodulator according to claim 1, wherein the phase error correction unit switches a carrier input to the phase error detection unit according to a phase shift amount of the time window. Frequency conversion means for converting an orthogonal frequency multiplexed signal into a baseband signal, calculation means for converting the baseband signal from the time domain to the frequency domain, and processing units from the baseband signal based on an output signal of the calculation means. In a quadrature frequency multiplexed signal demodulator having window phase control means for controlling the phase of a time window used to cut out a signal,
A clock recovery circuit for controlling the amount of phase shift of the window phase given to the arithmetic means by the window phase control means to a fixed value, and inputting an output signal of the arithmetic means to reproduce a clock signal; and / or a carrier incorporating the phase error detector in the carrier recovery circuit for reproducing a carrier of the output signal to input the OFDM modulated signal of the operation means that were limited to a specific carrier with a constant relationship between the fixed value An orthogonal frequency division multiplexing signal demodulator characterized by the above-mentioned.

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