JP3582682B2 - Failure analysis method and device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an apparatus for displaying fail data at the time of failure analysis of a memory device on a screen at high speed.
[0002]
[Prior art]
FIG. 4 is a block diagram showing a configuration example of a conventional failure analysis device.
[0003]
In this conventional example, as shown in FIG. 4, a pattern generator 101 for generating and outputting a pattern program for performing a test on a failure analysis memory 102 to be tested, and test data based on the pattern program are extracted from the failure analysis memory 102. Then, the selection unit 103 for selecting specific I / O data from the failure analysis memory 102, and all the addresses of the I / O data specified by the selection unit 103 are equally divided into several address portions, and the divided It comprises a fail counter 104 for counting the number of failed addresses in each part, and a buffer (RDBM) 105 for storing information counted by the fail counter 104.
[0004]
Hereinafter, the operation of the device configured as described above will be described.
[0005]
When the pattern program generated by the pattern generator 101 is applied to the failure analysis memory 102, first, the I / O data specified from the failure analysis memory 102 is selected by the selection unit 103, and the selected data is selected by the fail counter 104. All addresses of the I / O data specified by the unit 103 are equally divided into several address parts, and the number of failed addresses in each divided part is counted.
[0006]
After that, the information counted by the fail counter 104 is stored in the buffer 105, and the stored information is verified to analyze the failure in the failure analysis memory 102.
[0007]
There is also a method of simulating the above-described failure analysis by software instead of hardware.
[0008]
5A and 5B are diagrams for explaining a conventional failure analysis by software, in which FIG. 5A is a diagram illustrating a data configuration, and FIG. 5B is a diagram illustrating a processing procedure.
[0009]
As shown in FIG. 5, for example, in order to determine the number of bits "1" in one byte, the number of bits "1" is counted by adapting eight mask data.
[0010]
Therefore, in this method, the defect is analyzed by repeating the mask process eight times. When the number of data bits is 16 bits, double mask processing is required 16 times.
[0011]
[Problems to be solved by the invention]
The above-mentioned conventional one has the following problems.
(1) Since a pattern program for scanning a failure in the failure analysis memory is required, it must be replaced with a user's pattern program when used.
(2) Every time a pattern program is executed, previous data is lost.
(3) An online environment for generating a pattern program is required.
(4) When the failure analysis is simulated not by hardware but by software, mask processing for the number of bits is required, so that the time required for failure analysis becomes longer.
[0012]
In recent years, as the capacity of memory devices has increased, it has been desired to speed up failure analysis.
[0013]
The present invention has been made in view of the above-described problems of the conventional technology, and provides a failure analysis apparatus that can perform failure analysis at high speed even when the number of bits of a memory device is large. The purpose is to:
[0014]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides
A failure analysis method for extracting fail data of a memory device and detecting the number of fail of the fail data,
In advance, a value obtained by converting data of a predetermined number of bits into a decimal number is set as an address value,
When the address value is expressed in a binary number, the number of bits “1” is set as a fail number in association with the address value,
Reading the fail data from the memory device,
The method is characterized in that the fail data is converted into a decimal number, and the fail number corresponding to the matching address value is detected as the fail number of the fail data by comparing with the address value.
[0015]
Further, using display means for displaying the fail data,
The display means displays fail data at a plurality of addresses on one pixel.
[0016]
Further, the display of the fail data in one pixel of the display means is performed by performing color coding according to the number of failures in the data at the address displayed in the one pixel.
[0017]
Further, a failure analysis apparatus for extracting fail data of a memory device and detecting the number of fail of the fail data,
Reading means for reading the fail data from the memory device;
A value obtained by converting data of a predetermined number of bits into a decimal number is set in advance as an address value, and the number of bits “1” when the address value is expressed in a binary number is set as a fail number in correspondence with the address value. Control means for converting the fail data read out by the reading means into a decimal number, comparing with the address value, and detecting a fail number corresponding to the matching address value as a fail number of the fail data. It is characterized by having.
[0018]
Further, it is characterized by having display means for displaying fail data at a plurality of addresses in one pixel.
[0019]
Further, the display of the fail data in one pixel of the display means is performed by color-coding the data at the address displayed in the one pixel by the number of failures.
[0020]
Further, there is provided storage means for storing the fail data read by the reading means,
The control means reads the fail data from the storage means.
[0021]
(Action)
In the present invention configured as described above, in the control means, a value obtained by converting a predetermined number of bits of data into a decimal number is set in advance as an address value, and the bit "when the address value is represented by a binary number" The number of "1" is set as the number of failures corresponding to the address value, and the fail data read from the memory address is converted into a decimal number by the read means and compared with the address value, and the fail value corresponding to the matching address value is read. Since the number is detected as the number of failures of the fail data, the processing time does not increase even when the number of bits of the data read from the memory address is large.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0023]
FIG. 1 is a block diagram showing one embodiment of the failure analysis device of the present invention.
[0024]
In this embodiment, as shown in FIG. 1, a graphical user interface 20 for analyzing and displaying a defect of the defect analysis memory 2 in the device under test 30 is built in. The graphical user interface 20 has a defect. Reading means 24 for reading the fail data from the analysis memory 2; a file 21 which is a storage means for storing the fail data read by the reading means 24; and a display means 23 for displaying the fail data stored in the file 21 And a control unit 22 for reading out fail data from the file 21 and displaying it on the display unit 23 and detecting the number of failures of the fail data.
[0025]
Hereinafter, the operation of the failure analysis device configured as described above will be described.
[0026]
First, fail data is read from the failure analysis memory 2 by the reading means 24 and stored in the file 21.
[0027]
Next, the control unit 22 reads the fail data stored in the file 21 and counts the number of failures to be displayed on the display unit 23.
[0028]
Here, the counting operation of the number of failures in the control means 22 will be described in detail.
[0029]
FIG. 2 is a diagram for explaining a processing operation in the control means 22 shown in FIG.
[0030]
As shown in FIG. 2, for example, when counting the number of failures in one byte, there are 2 ⁸ = 256 (0 to 255) address values, each of which is represented by a binary number. A fail count table is used in which the number of bits "1" is set as the number of failures and corresponds to each address value.
[0031]
When 1-byte fail data is read from the file 21, the read fail data is converted into a decimal number, and the conversion result is compared with the address value of the fail count table.
[0032]
Then, the number of failures corresponding to the address value that matches the failure data converted into the decimal number is detected, and the number of failures becomes the number of failures of the fail data read from the file 21.
[0033]
When the method as described above is used, the number of failures can be counted only by obtaining the fail data and then finding the corresponding position in the fail count table. In comparison with the processing procedure in the assembler language according to the method described above, fail data can be processed 14 times faster when processing 1-byte data and about 30 times faster when processing 2-byte data. .
[0034]
Thereafter, the fail data is displayed on the display means 23 using the number of failures counted by the control means 22.
[0035]
Hereinafter, the display operation of the display unit 23 will be described in detail.
[0036]
FIG. 3 is a diagram for explaining a processing operation in the display unit 23 shown in FIG.
[0037]
When screen display is performed on the display means 23 having a limit of 512 × 512 pixels in the screen display area and data of 1 Mbit or more is displayed, fail data of several addresses per pixel is color-coded as fail information. Must be displayed (compression processing).
[0038]
For example, in the case where 1M-bit fail data (1024 × 1024 bits) is displayed on the screen, the number of failures corresponding to two addresses in both the X and Y directions is displayed together. The number of failed addresses is determined (in this case, the number of failures is any one of 0 to 4), and is displayed in one pixel on the screen by color-coding according to the number of failures.
[0039]
That is, the sum of the failed addresses at the X / Y addresses (0, 0), (0, 1), (1, 0), and (1, 1) is displayed at the position 1 on the display screen. The same applies to positions other than the display screen. In this case, the number of failed addresses in each of the four areas is any one of 0 to 4, and therefore, on the screen display, for example, green, red, brown, blue , Colored orange.
[0040]
In the above-described embodiment, the number of failures is detected by counting the number of bits "1" in one byte in the control means 22, but as another method, there is even one bit "1". A method of detecting fail data depending on whether or not the data is present is also conceivable.
[0041]
【The invention's effect】
The present invention is configured as described above, and has the following effects.
[0042]
According to the first and fourth aspects of the present invention, a data obtained by converting a predetermined number of bits of data into a decimal number is set as an address value, and the bit “1” when the address value is expressed in a binary number. The fail data read from the memory device is converted into a decimal number, compared with the address value, and the fail number corresponding to the matching address value is set as the fail data. Since the configuration is such that the number of failures is detected, even when the number of bits of data read from the memory address is large, the processing time does not increase and the failure analysis can be performed at high speed.
[0043]
According to the second, third, fifth, and sixth aspects, since fail data at a plurality of addresses is displayed in one pixel, the amount of data to be displayed is limited when the display area of the screen is limited. Can exceed the limit, fail data can be displayed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a failure analysis device according to the present invention.
FIG. 2 is a diagram for explaining a processing operation in a control unit shown in FIG. 1;
FIG. 3 is a diagram for explaining a processing operation in a display unit shown in FIG. 1;
FIG. 4 is a block diagram illustrating a configuration example of a conventional failure analysis device.
5A and 5B are diagrams for explaining conventional failure analysis by software, in which FIG. 5A is a diagram illustrating a data configuration, and FIG. 5B is a diagram illustrating a processing procedure.
[Explanation of symbols]
2 Failure analysis memory 10 Failure analysis device 20 Graphical user interface 21 File 22 Control means 23 Display means 24 Reading means 30 Device under test

Claims (7)

A failure analysis method for extracting fail data of a memory device and detecting the number of fail of the fail data,
In advance, a value obtained by converting data of a predetermined number of bits into a decimal number is set as an address value,
When the address value is expressed in a binary number, the number of bits “1” is set as a fail number in association with the address value,
Reading the fail data from the memory device,
A failure analysis method comprising: converting the fail data into a decimal number; comparing the address value with the address value; and detecting a fail number corresponding to a matching address value as a fail number of the fail data. The failure analysis method according to claim 1,
Using display means for displaying the fail data,
A failure analysis method characterized by displaying fail data at a plurality of addresses on one pixel of the display means. 3. The failure analysis method according to claim 2,
A failure analysis method characterized in that the display of the fail data in one pixel of the display means is performed by color-coding according to the number of failures in the data at the address displayed in the one pixel. A failure analyzer for extracting fail data of a memory device and detecting the number of fail of the fail data,
Reading means for reading the fail data from the memory device;
A value obtained by converting data of a predetermined number of bits into a decimal number is set in advance as an address value, and the number of bits “1” when the address value is expressed in a binary number is set as a fail number in correspondence with the address value. Control means for converting the fail data read out by the reading means into a decimal number, comparing with the address value, and detecting a fail number corresponding to the matching address value as a fail number of the fail data. A failure analysis device characterized by having. The failure analysis device according to claim 4,
A failure analysis device comprising display means for displaying fail data at a plurality of addresses in one pixel. The failure analysis device according to claim 5,
The failure analysis apparatus according to claim 1, wherein the display of the fail data in one pixel of the display means is performed by color-coding according to the number of failures in the data at the address displayed in the one pixel. The failure analysis device according to any one of claims 4 to 6,
Storage means for storing the fail data read by the reading means,
The failure analysis device, wherein the control unit reads the fail data from the storage unit.

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