JP3587369B2 - Path detection device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an improvement in a path detection device that detects a path from a received signal in a DS-CDMA (Direct Sequence-Code Division Multiple Access) receiver.
[0002]
[Prior art]
In the DS-CDMA receiver, detection of the correlation peak (path) is performed in order to obtain the demodulation timing using only the correlation peak of the output of a matched filter (hereinafter simply referred to as MF) for filtering the received baseband signal. Detection) is important. However, in general, the received baseband signal fluctuates drastically under the influence of multipath fading, so that the MF output also fluctuates and is buried in noise, making path detection extremely difficult.
[0003]
FIG. 5 is a block diagram showing a circuit configuration of a conventional path detection device.
In FIG. 5, in general, when the number of bits of a signal processed by the MF unit 102 is large, the circuit configuration of the MF unit 102 is large. Therefore, a small circuit configuration can be realized by reducing the number of processing bits. It is planned. Therefore, the received baseband signal is input to the bit number adjusting section 101 and cut out at the bit cutout position set by the control section 104, and the number of bits of the received baseband signal is adjusted.
[0004]
The received baseband signal whose bit number has been adjusted is input to MF section 102 and despread with a spreading code generated by spreading code generator 103. The MF unit 102 performs a correlation operation for one symbol time between the received baseband signal and the spreading code using a multiplier or an accumulator. If the phase of the spread code of the received baseband signal matches the phase of the spread code output from spread code generator 103, MF section 102 detects a sharp correlation peak unique to the spread code. Since these MF outputs have a phase rotation due to a propagation path and an information signal, the power conversion circuit 105 squares the MF outputs to remove phase fluctuations.
[0005]
The MF output from which the phase variation has been removed by the power conversion circuit 105 is cumulatively added by the adder 106 and the memory 107.
FIG. 6A shows an example of the cumulative addition output.
The cumulative addition output is input to the noise level measuring unit 108, and the noise level included in the cumulative addition output is measured. The noise level measuring unit 108 can be realized by, for example, an LPF (Low Pass Filter). FIG. 6A shows an example of the noise level measurement output together with an example of the cumulative addition output.
[0006]
That is, FIG. 6A shows both a signal example of the cumulative addition output and a signal example of the noise level measurement output viewed on the time axis.
In FIG. 6A, the noise level measurement output is an output obtained by time-averaging the cumulative addition output. As is clear from FIG. 6A, if the level of the noise level measurement output is changed and set as a threshold value, and only the path existing at the center exceeds the threshold value, it is determined as the reception path timing. It can be assumed that it will be possible.
[0007]
The noise level measurement output from the noise level measurement unit 108 is input to the first comparator 109 and is compared with the lower limit set by the control unit 104. The first comparator 109 compares the noise level measurement output with the lower limit, outputs the lower limit when the noise level measurement output is smaller than the lower limit, and outputs the lower limit when the noise level measurement output is larger than the lower limit. Output the output.
[0008]
An example of the noise level measurement output and an example of the lower limit comparison result are shown in FIG. In FIG. 6B, the lower limit comparison result always exceeds the lower limit. The lower limit comparison result is input to the threshold generation unit 110, and the threshold generation unit 110Lower limit comparison result to lower limit comparison resultThe threshold value is generated by adding half the maximum value of.
FIG. 6C shows an example of the lower limit value comparison result and the threshold value.
[0009]
The threshold value generated by threshold value generating section 110 is compared with the cumulative addition output by second comparator 111, and the cumulative addition output exceeding the threshold value is determined as the reception path timing. FIG. 6D shows an example of the threshold value and an example of the cumulative addition output. As is clear from FIG. 6D, only the cumulative addition output exceeding the threshold value is determined as the reception path timing. The determined reception path timing is output to control section 104.
[0010]
As described above, in the path detection device shown in FIG. 5, the control unit 104 accumulates two parameters, that is, the bit cutout position to the bit number adjustment unit 101 and the lower limit value to the first comparator 109. Before the addition, it is set only once to make it a fixed value, and the path detection control processing is performed.
[0011]
FIG. 7 is a flowchart illustrating a path detection control process performed by the control unit 104.
As shown in FIG. 7, the control unit 104 first clears the cumulative addition memory 107 to eliminate the influence of the past cumulative addition value (step 301). Next, the control unit 104 sets the bit extraction position in the bit number adjustment unit 101 (step 302), and sets a lower limit value in the first comparator 109 (step 303). Then, in order to suppress noise included in the MF output and absorb fading fluctuations of the MF output, a long time (for example, 40 ms) averaging is performed (step 304).
[0012]
After waiting for averaging, the control unit 104 receives the reception path timing from the second comparator 111 and determines whether a path has been detected (step 305). If the path is detected (if Yes), the path detection flag is set (step 306), and the path detection control processing ends. On the other hand, if the path is not detected in processing step 305 (if No), the path detection flag is cleared (step 307), and the path detection control processing ends.
[0013]
[Problems to be solved by the invention]
However, in the above-described conventional path detection device, the setting of the bit cutout position in the bit number adjustment unit 101 and the setting of the lower limit value in the first comparator 109 by the control unit 104 are fixed during the path detection control processing. In other words, when the level of the received baseband signal fluctuates due to fading fluctuation, for example, when the level fluctuates and becomes low because the set values are fixed values, the MF input with the adjusted number of bits Similarly, the level also becomes low, and it is difficult to obtain a correlation peak in the MF output. Further, although the threshold value slightly decreases due to the level decrease, the lower limit value is fixed at a high level, so that path detection becomes extremely difficult. Occurs.
[0014]
An operation flow when the reception baseband signal level fluctuates will be described with reference to FIG.
FIG. 8 shows the relationship between the cumulative addition output and the threshold value of the conventional path detection control method when the reception baseband signal level temporally decreases in bit units.
In FIG. 8A, it is assumed that the received baseband signal is composed of 10 bits including a sign bit, the MF input signal is composed of 4 bits including a sign bit, and the MSB bit is a sign bit and “0” is "1" indicates a positive sign and "1" indicates a negative sign. Here, for the sake of simplicity, all the signs are positive. In section T1, the eighth bit is "1" and the received baseband signal level is maximum, but in section T2, the eighth and seventh bits are "0" and the received baseband signal level is low.
[0015]
Assuming that the cutout position of the remaining 3 bits excluding the sign bit among the 4 bits of the MF input signal is the upper 3 bits (8th, 7th, 6th bits), as a result, 4 bits in the thick frame are input to the MF. . It is also assumed that as a result of setting the lower limit, the threshold value has reached a level as shown in FIGS. 8B and 8C in each section. FIG. 8B shows a relationship between the cumulative addition output and the threshold value in the section T1. On the other hand, FIG. 8C shows a relationship between the cumulative addition output and the threshold value in the section T2.
[0016]
In FIG. 8B, the reception baseband signal level is the maximum in the section T1, and the MF input level is also the maximum because the cut-out position of the input bit is set to the upper 3 bits. At this time, the cumulative addition output also becomes maximum, and only the path exceeding the threshold is set as the reception path timing. On the other hand, in the section T2, the reception baseband signal level is lowered, and the MF input level is extremely low because the cutout position of the MF input bit is set to the upper 3 bits. Therefore, as shown in FIG. 8C, the cumulative addition output also decreases, and since the lower limit value is fixed, the threshold value is fixed at the same level as that in the section T1, and there is no path exceeding this, and the reception is not performed. No path timing is detected.
[0017]
Conventionally, instability of path detection due to such level fluctuation has been avoided by averaging over a long section (for example, about 40 ms). However, since the section is a long section, it takes time and the level does not recover during averaging. In such a case, there is a problem that the path cannot be detected.
[0018]
The present invention has been made in view of the above-described problems of the conventional example.PowerIt is an object of the present invention to provide a path detection device that can optimize a level and a lower limit and improve a path detection rate.
[0019]
[Means for Solving the Problems]
In order to solve the above-described problem, a path detection device according to the present invention detects a reception signal level using a predetermined number of extracted bits, and detects the detection value.And set valueA path detecting unit that sets a threshold based on the threshold and detects a path of the received signal using the threshold; and a path detecting unit that detects whether a path is detected within a predetermined time. When no path is detected by the path detecting means,Change the cutting position and the set value for bit cuttingAnd a change setting unit.
Further, the path detecting device according to the present invention is characterized in that a predetermined number of bits are cut out from the received baseband signal and input, and correlation operation means for performing a correlation operation between the received baseband signal and the spread code, and an output of the correlation operation means A noise level measuring unit that measures a noise level by performing LPF processing on a signal based on a signal, a first comparator that inputs an output of the noise level measuring unit, a lower limit value, and outputs a larger one, A threshold value generating unit that generates a threshold value by adding a half of the maximum value of the output of the first comparator to the output of the comparator, and a threshold value output by the threshold value generating unit A second comparator for comparing a signal based on the output of the correlation operation means, and a path detection means for detecting whether or not a path is detected from the output of the second comparator within a predetermined time. No path detection by the path detecting means The case, is characterized in that a change setting means for changing the lower limit.
Further, in the path detecting device according to the present invention, in the path detecting device according to claim 2, the correlation calculating means is a matched filter, and the change setting means is optional when there is no path detection by the path detecting means. The cutting position at which the bit cutting is performed is changed every number of times or every period.
[0020]
In the above configuration, if a path is not detected by the path detecting means, first, the lower limit is lowered to determine whether or not a path is detected. If no path is detected, the bit cutout position is further changed to reduce the number of bits. It is preferable that the number is large, for example, the maximum number that can be input to the matched filter.
[0021]
According to the above configuration, even when the received baseband signal level is reduced, the MF input is periodically performed.PowerBy adjusting the level and changing the lower limit, it is possible to detect a path by averaging short sections without waiting for the level to recover.
[0022]
Note that the path detection device according to the embodiment of the present invention is configured to input a reception baseband signal, cut out at a set bit extraction position, and output a reception baseband signal in which the number of bits is adjusted, and a bit number adjustment unit. A matched filter for despreading the output from the bit number adjusting unit and outputting a correlation value for one symbol time, a power conversion circuit for converting the output of the matched filter into power, an adder, and an output of the adder And a memory for storing an output of the power conversion circuit and a value stored in the memory by an adder to obtain a cumulative addition value, which is included in an output of the cumulative addition means. The noise level measurement unit that measures the noise level is compared with the noise level measurement output and the set lower limit. If the lower limit is larger, the lower limit is output. If the lower limit is smaller, the noise level is output. A first comparator that outputs a measurement output, a threshold generator that outputs a signal obtained by adding a maximum value of the output of the first comparator and a half value of the maximum value, and a threshold generator that outputs the signal. A second comparator that compares the output of the second adder with the output of the cumulative adder, and outputs only the output of the cumulative adder that exceeds the output of the threshold generator as the reception path timing; A path detection device including a control unit that sets a bit cutout position to the bit number adjustment unit and a lower limit value to the first comparator based on the control unit, wherein the control unit includes a counter therein. After clearing the memory of the accumulating means, setting the bit cutout position in the bit number adjusting unit, setting the lower limit value in the first comparator, and initializing the counter, counting by the counter The value is preset If the count value of the counter is not within the maximum path detection time, the path detection flag is cleared and the path detection control process is terminated. If it is within the maximum time, wait for a predetermined time, receive the reception path timing from the second comparator, determine whether or not a path has been detected, and if a path has been detected, set a path detection flag and end the path detection control processing, If the path is not detected, the lower limit value to the first comparator is changed and set, and it is determined whether or not the count value of the counter has passed an arbitrarily set cycle time. If the time has elapsed, the cutout position to the bit number adjustment unit is changed and the lower limit value to the first comparator is reset, while if the counter has not elapsed for a predetermined time, the memory Is cleared, the counter is advanced, it is determined again whether or not the counter is within the maximum path detection time, and the processing is repeated until a series of path detection control processing is completed.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram illustrating a configuration of a path detection device according to an embodiment of the present invention.
1, the same parts as those of the conventional example shown in FIG. 5 are denoted by the same reference numerals, and the description thereof will be omitted. As a new code, reference numeral 204 denotes a control unit according to the present embodiment. This control unit 204 has a counter therein, clears the memory 107, and sets the bit cutout position in the bit number adjustment unit 101A. At the same time, a lower limit value is set in the first comparator 109A and the counter is initialized. Then, it is determined whether or not the count value of the counter is within a predetermined maximum path detection time which will be described later with reference to FIG. If the value is not within the maximum path detection time, the path detection flag is cleared and the path detection control process is terminated. If the count value is within the maximum path detection time, a predetermined time is waited. It is determined whether or not a path has been detected. If a path is detected, a path detection flag is set and the path detection control process is terminated. The value is changed and set, and it is determined whether or not the count value has passed an arbitrarily set cycle time. If the counter has passed the cycle time, the cutout position to the bit number adjusting unit 101A is changed. The lower limit value of the first comparator 109A is reset. On the other hand, if the counter has not passed the predetermined time, the memory 107 is cleared, the counter is advanced, and it is determined again whether the counter is within the maximum path detection time. The processing is repeated until a series of path detection control processing ends.
[0024]
That is, in this embodiment, when a path is detected from a received signal in a DS-CDMA receiver,weighted averageIf the path is not detected, it is determined that the reception level has dropped, and the lower limit is changed to lower the threshold so that the path can be detected. If the path cannot be detected more than once even if the lower limit is changed, bit extraction is performed. The position is changed and the input level to the MF unit 102 is set to the maximum, and the lower limit value is reset, thereby making it possible to cope with a change in the received signal level due to fading or the like.
[0025]
Next, the operation of the path detection device having the configuration shown in FIG. 1 will be described.
In FIG. 1, generally, when the number of bits of a signal processed by the MF unit 102 is large, the circuit configuration of the MF unit 102 is large. Therefore, a small-scale circuit configuration can be realized by reducing the number of processing bits. It is planned. Therefore, the received baseband signal is input to bit number adjusting section 101A, and cut out at the bit cutout position set by control section 204, and the number of bits of the received baseband signal is adjusted.
[0026]
The received baseband signal whose bit number has been adjusted is input to MF section 102 and despread with a spreading code generated by spreading code generator 103. The MF unit 102 performs a correlation operation for one symbol time between the received baseband signal and the spreading code using a multiplier or an accumulator. If the phase of the spread code of the received baseband signal matches the phase of the spread code output from spread code generator 103, MF section 102 detects a sharp correlation peak unique to the spread code. Since these MF outputs have a phase rotation due to the propagation path and the information signal, the power conversion circuit 105 squares the MF outputs to remove phase fluctuations.
[0027]
The MF output from which the phase change has been removed by the power conversion circuit 105 is cumulatively added by the adder 106 and the memory 107. An example of the accumulated addition output is shown in FIG.
The cumulative addition output is input to the noise level measuring unit 108, and the noise level included in the cumulative addition output is measured. The noise level measuring unit 108 can be realized by, for example, an LPF. An example of the noise level measurement output is shown in FIG.
[0028]
That is, FIG. 6A shows both the signal of the cumulative addition output and the signal example of the noise level measurement output viewed on the time axis, and the noise level measurement output is an output obtained by time-averaging the cumulative addition output. . As is clear from FIG. 6A, if the level of the noise level measurement output is changed and set as a threshold value, and only the path existing at the center exceeds the threshold value, it is determined as the reception path timing. It can be assumed that it will be possible.
[0029]
The noise level measurement output from the noise level measurement unit 108 is input to the first comparator 109A and compared with the lower limit set by the control unit 204. The first comparator 109A compares the noise level measurement output with the lower limit, outputs the lower limit when the noise level measurement output is smaller than the lower limit, and outputs the lower limit when the noise level measurement output is larger than the lower limit. Output the output.
[0030]
An example of the noise level measurement output and an example of the lower limit comparison result are shown in FIG.
In FIG. 6B, the lower limit comparison result always exceeds the lower limit. The lower limit comparison result is input to the threshold generation unit 110, and the threshold generation unit 110Lower limit comparison result to lower limit comparison resultThe threshold value is generated by adding half the maximum value of.
FIG. 6C shows an example of the lower limit value comparison result and the threshold value.
[0031]
The threshold value generated by threshold value generating section 110 is compared with the cumulative addition output by second comparator 111, and the cumulative addition output exceeding the threshold value is recognized as the reception path timing. FIG. 6D shows an example of the threshold value and an example of the cumulative addition output. As apparent from FIG. 6 (D), only the cumulative output exceeding the threshold value is determined as the reception path timing. The determined reception path timing is output to control section 204.
[0032]
FIG. 2 is a flowchart illustrating a path detection control process performed by the control unit 204 according to the present embodiment.
Here, the counter initialization step 504 initializes the counter. The counter end determination step 505 determines whether or not the count value of the counter has exceeded an arbitrary path detection maximum time (MAX) (symbol period × arbitrary number). The averaging waiting step 506 waits for a predetermined time to perform cumulative addition averaging of the MF output. The predetermined time is shorter than the prior art, for example, about 2 ms. The lower limit value changing step 510 changes and sets the currently set lower limit value. The counter cycle determination step 511 calculates the remainder between the counter value and an arbitrary cycle (PERIOD) (any number of times). If the remainder is 0, it is determined that an arbitrary cycle time has elapsed. It is determined that the cycle time has not elapsed. In the cutout position change step 512, the cutout position of the currently set bit is changed and set. A lower limit reset step 513 resets an arbitrary lower limit. The counter increment step 515 advances the counter.
[0033]
Hereinafter, the path detection control processing by the control unit 204 according to the flowchart shown in FIG. 2 will be described.
As shown in FIG. 2, first, the memory 107 for cumulative addition is cleared to eliminate the influence of past cumulative addition values (step 501). Next, a bit extraction position is set to the bit number adjustment unit 101A (step 502), and any three bits excluding the sign bit from the received baseband signal composed of 10 bits are input to the MF. Next, a lower limit value is set to the first comparator 109A (step 503), a counter is initialized (step 504), and the counter is checked whether an arbitrary path detection maximum time (MAX) has elapsed (step 505). If the counter is not within the maximum path detection time (if No), the path detection flag is cleared (step 507), and the path detection control processing ends.
[0034]
On the other hand, if it is within the maximum path detection time (Yes) in the step 505, a predetermined time is waited until the MF outputs are averaged (step 506), and it is checked whether a path is detected (step 508). . If a path is detected (if Yes), the path detection flag is set (step 509), and the path detection control processing ends.
[0035]
On the other hand, if no path is detected in step 508 (if No), the lower limit is changed (step 510), and the counter is checked for whether or not an arbitrary period time (PERIOD) has elapsed (step 511). If it has not elapsed (if No), the memory is cleared (step 514), the counter is advanced (step 515), and the counter is checked again to see if an arbitrary path detection maximum time (MAX) has elapsed (step 505). .
[0036]
In step 511, if an arbitrary period has elapsed (if Yes), the cutout position is changed to adjust the MF input bit (step 512), and the lower limit is reset (step 513). The memory is cleared (step 514), the power counter is advanced (step 515), and the counter is checked again to see if an arbitrary path detection maximum time (MAX) has elapsed (step 505). The processing from the counter end determination to the advance of the counter (step 505 → 515) is performed until the counter exceeds the maximum path detection time in processing step 505 (until it becomes No) or until the path is detected in step 508 ( It repeats until it becomes Yes.
[0037]
Here, the operation flow of the lower limit value change (step 510) will be described with reference to FIG.
FIG. 3 shows the relationship between the cumulative addition output and the threshold value when the lower limit of the path detection control method of the present invention is changed while the reception baseband signal level temporally decreases in bit units.
[0038]
In FIG. 3A, it is assumed that the received baseband signal is composed of 10 bits including a sign bit, the MF input signal is composed of 4 bits including a sign bit, and the MSB bit is a sign bit and “0” is "1" indicates a positive sign and "1" indicates a negative sign. Here, for the sake of simplicity, all the signs are positive. In section T1, the eighth bit is "1" and the reception baseband signal level is maximum, but in section T2, the eighth bit is "0" and the reception baseband signal level is slightly lower.
[0039]
When the extraction position of the remaining 3 bits excluding the sign bit among the 4 bits of the MF input signal is set to the upper 3 bits (8th, 7th, 6th bits) in the extraction position setting (step 502), 4 The bit is input to the MF section. It is also assumed that the threshold value has reached the level shown in FIG. 3B as a result of setting the lower limit value in the lower limit value setting (step 503). FIG. 3B shows the relationship between the cumulative addition output and the threshold value in the section T1.
[0040]
In FIG. 3 (B), the reception baseband signal level is the maximum in the section T1, and the MF input level is also the maximum because the cutout position of the MF input bit is the upper 3 bits. At this time, the cumulative addition output also becomes maximum, and only the path exceeding the threshold is set as the reception path timing. On the other hand, in the section T2, the reception baseband signal level is lowered by one bit, and the cutoff position of the MF input bit is set to the upper three bits, so that the MF input level is lower than the section T1.
[0041]
Therefore, the cumulative addition output also decreases as shown in FIG. FIG. 3C shows the relationship between the cumulative addition output and the threshold value in the section T2. In FIG. 3 (C), if the same lower limit is used in the section T2 as in the section T1, the threshold value is also at the same level as in the section T1, and there is no path exceeding this, and the reception path timing is not detected. When the reception path timing is not detected, the lower limit value is lowered in the lower limit value change (step 510) as in the section T2 in FIG. 3, so that the threshold value is also lowered, and only the path exceeding the threshold value is recognized as the reception path timing. Is done.
[0042]
Next, the flow of the operations of the cutout position change processing (step 512) and the resetting of the lower limit value (step 513) will be described with reference to FIG.
FIG. 4 shows the cumulative addition when the cutout position of the MF input bit of the path detection control method of the present invention is changed and the lower limit value is reset while the reception baseband signal level is temporally reduced in bit units. Shows the relationship between output and threshold.
[0043]
In FIG. 4A, it is assumed that the received baseband signal is composed of 10 bits including a sign bit, the MF input signal is composed of 4 bits including a sign bit, and the MSB bit is a sign bit and “0” is "1" indicates a positive sign and "1" indicates a negative sign. Here, in order to simplify the explanation, all the signs are positive. In the sections T1 and T2, the eighth and seventh bits are “0”, and the reception baseband signal level is low.
[0044]
In the cutout position setting (step 502), if the cutout positions of the remaining 3 bits excluding the sign bit out of the 4 bits of the MF input signal are set to the upper 3 bits (8th, 7th, 6th bits), as a result, a thick frame in the section T1 Are input to the MF. It is also assumed that the threshold value is set as shown in FIG. 4B as a result of setting the lower limit value in the lower limit value setting (step 503). FIG. 4B shows the relationship between the cumulative addition output and the threshold value in the section T1.
[0045]
In FIG. 4 (B), the path is not detected at the high lower limit because the received baseband signal level is low in the section T1, and if the lower limit is lowered by changing the lower limit (step 510), the accumulated addition output is low, so that an incorrect path is obtained. As the reception path timing. Therefore, if a path is not detected even after an arbitrary period of time elapses before the lower limit is excessively lowered, the cutout position of the bit is changed in the cutout position change processing (step 512) so that the MF input becomes the maximum level. Further, since it is necessary to once raise the lower limit value that has been lowered before the elapse of the cycle time, the lower limit value is reset (step 513).
[0046]
In FIG. 4A, the input signal to the MF is changed to the ninth, sixth, fifth, and fourth bits of the received baseband signal in the section T2, and the MF input level is maximized. Therefore, the cumulative addition output also becomes maximum as shown in FIG. FIG. 4C shows the relationship between the cumulative addition output and the threshold value in the section T2. In FIG. 4 (C), in section T2, the cumulative addition output also becomes maximum and path detection becomes easy, and only paths exceeding the threshold value are determined to be reception path timings.
[0047]
【The invention's effect】
As described above in detail, by implementing the present invention, even if the received baseband signal level is lowered, the MF input level is periodically adjusted and the lower limit value is changed to wait for the level recovery. There is an effect that a path can be detected with an average of short sections without any problem.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a path detection device according to an embodiment of the present invention.
FIG. 2 is a processing flowchart of a control unit 204 shown in FIG.
FIG. 3 is an explanatory diagram showing a relationship between a decrease in the level of a received baseband signal, a cumulative addition output when a lower limit value is changed in the path detection control method of the present invention, and a threshold value.
FIG. 4 is an explanatory diagram showing a relationship between a decrease in the level of a received baseband signal, a change in MF input bits of the path detection control method of the present invention, and a cumulative addition output when a lower limit value is reset and a threshold value.
FIG. 5 is a block diagram illustrating a configuration of a conventional path detection device.
6 is a diagram illustrating an output signal of the path detection device shown in FIG.
7 is a processing flowchart of a control unit 104 shown in FIG.
FIG. 8 is an explanatory diagram showing a relationship between a decrease in the level of a received baseband signal, a cumulative addition output, and a threshold value in a conventional example.
[Explanation of symbols]
101A Bit number adjustment unit, 102 Matched filter (MF) unit, 103 spreading code generator, 204 control unit, 105 power circuit, 106 adder, 107 memory, 108 noise level measurement unit, 109A first comparator, 110 Threshold generator, 111 second comparator.

Claims (3)

The reception signal level is detected using the extracted predetermined number of bits, a threshold value is set based on the detection value and the set value, and the path of the reception signal is detected using the threshold value. In the path detection device,
Path detection means for detecting whether a path is detected within a predetermined time,
When there is no path detection by the path detection unit, a change setting unit that changes the cutout position and the set value for performing the bit cutout,
A path detection device comprising: Correlation calculation means for cutting out and inputting a predetermined number of bits from the reception baseband signal and performing a correlation calculation between the reception baseband signal and the spreading code,
A noise level measurement unit that measures a noise level by performing LPF processing on a signal based on an output of the correlation operation unit;
A first comparator which inputs the output of the noise level measuring unit and the lower limit value and outputs the larger one, and outputs to the output of the first comparator half the maximum value of the output of the first comparator A threshold generation unit that generates a threshold by adding the values of
A second comparator that compares a threshold value output by the threshold value generation unit with a signal based on an output of the correlation operation unit;
Path detection means for detecting whether a path is detected from the output of the second comparator within a predetermined time,
When there is no path detection by the path detection means, change setting means for changing the lower limit,
A path detection device comprising: The path detection device according to claim 2,
The correlation calculation means is a matched filter, and the change setting means changes the cutout position at which the bit cutout is performed at an arbitrary number of times or every cycle when no path is detected by the path detection means. Path detection device.

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