JP3593123B2 - Set associative memory device - Google Patents

Description

  The present invention relates to a set associative memory device, and more particularly, to a set associative memory device in which power consumption is reduced and a time lag in reading data is reduced.

  A conventional set associative memory is described in "Parallel Computer Architecture" (written by Shinji Tomita, Shokodo, 2.3.2 Storage Controller, (1) Storage Hierarchy, and (2) Cache Memory). I have.

  FIG. 17 is a block diagram showing a schematic configuration of a conventional set associative type memory described in the above-mentioned known document, in which a two-set associative address translation buffer (hereinafter, referred to as TLB) 691 and a two-set associative memory are shown. This is a TLB / cache device composed of a cache 692.

  The address 600 is a logical address, is converted into a physical address by the TLB 691, and is input to the cache 692.

  The address 600 is composed of a logical page number 604 and an offset 601 within a page.

  The logical page number 604 is converted into a physical page number 625 by the TLB 691 and input to the cache 692.

  The intra-page offset 601 is directly input to the cache 692 without being converted.

  The physical address is composed of a physical page number 625 and an offset 601 in the page.

  Hereinafter, the operation of the TLB / cache device shown in FIG. 17 will be described.

  The lower bit 602 of the logical page number 604 is input to the TLB tag storage unit (610, 611), and the TLB tag (612, 613) is output.

  These TLB tags are input to the TLB way determiner 614.

  Here, reference numeral 610 is a memory for storing a tag of the TLB way 0, and 611 is a memory for storing the tag of the TLB way 1 respectively.

  Next, the TLB way determination unit 614 compares the upper bit 603 of the logical page number 604 with the TLB tag of each way, and outputs a TLB way determination signal 615 indicating which TLB tag matches the TLB tag.

  On the other hand, the lower bit 602 of the logical page number 604 is input to the TLB data storage unit (620, 621) of the TLB, and the physical page number (622, 623) is output.

  These physical page numbers are input to the physical page number selector 624.

  Here, 620 is a memory for storing the physical page number of way 0, and 621 is a memory for storing the physical page number of way 1 respectively.

  The physical page number selector 624 selects either the physical page number 622 of way 0 or the physical page number 623 of way 1 based on the TLB way determination signal 615, and outputs the physical page number 625.

  The offset 601 in the page is input to the cache tag storage unit (630, 631), and the cache tag (632, 633) is output.

  These cache tags (632, 633) are input to the cache way determiner 634.

  Here, 630 is a memory for storing the tag of way 0 of the cache, and 631 is a memory for storing the tag of way 1 of the cache.

  Next, the cache way determination unit 634 compares the physical page number 625 with the cache tag (632, 633) of each way, and outputs a cache way determination signal 635 indicating which way the cache tag matches.

  On the other hand, the offset 601 in the page is input to the cache data storage unit (640, 641), and the data (642, 643) is output.

  These data (642, 643) are input to the data selector 644.

  Here, 640 is a memory for storing data of way 0, and 641 is a memory for storing data of way 1 respectively.

  The data selector 644 selects the data 642 or the data 643 based on the cache way determination signal 635 and outputs the data 645.

  At this time, if the physical page number 625 and the cache tag 632 of the way 0 match, the value of the data 642 of the way 0, and if the physical page number 625 and the cache tag 633 of the way 1 match, the value of the data 643 of the way 1 Is the value of the data 645.

  The value of the data 645 is temporarily stored in the latch 646 and then output as data 647 in the next cycle.

  In this TLB / cache device, eight TLB tag storage units (610, 611), TLB data storage units (620, 621), cache tag storage units (630, 631), and cache data storage units (640, 641) are provided. The memories can operate in parallel at the same time.

  That is, when the logical address 600 is input, these eight memories can start operating.

  On the other hand, the TLB tag storage units (610, 611), the TLB way decision unit 614, the physical page number selector 624, and the cache way decision unit 634 cannot be executed simultaneously, and must be executed in this order. No.

  Therefore, it takes time to generate the value of the cache way determination signal 635 output from the cache way determination unit 634.

  For this reason, in the conventional two-set associative cache, before the value of the cache way determination signal 635 is determined, both the way 0 portion 640 and the way 1 portion 641 of the cache data storage unit are operated in advance. Then, data 642 of way 0 and data 643 of way 1 are output, and the method is selected by the cache way determination signal 635.

  In this method, there is a problem that the power for operating the cache increases because both the portion 640 of the way 0 and the portion 641 of the way 1 of the cache data storage unit (640, 641) operate simultaneously. .

  The TLB tag storage units (610, 611), the TLB way decision unit 614, the physical page number selector 624, the cache way decision unit 634, and the data selector 644 must be executed in order, and the TLB / cache There is a problem that a time lag (delay time) from when the logical address 600 is input to the device until when the data 645 is output increases.

  To solve the above problem, in a set associative cache memory, activation of a sense amplifier at the time of data reading is performed by a hit signal from a tag, and when a hit occurs, the sense amplifier is activated to read data. The reduction of power consumption at the time is described in Japanese Patent Application Laid-Open No. 4-328656.

  Also, in order to solve the above problem, in a set associative cache memory, a hit signal is not output from an address comparing unit that compares an externally input address with a tag read from a tag unit. In the storage unit, flag information indicating the data unit accessed immediately before is stored in the storage unit, and by using the flag information, the data from the data unit of the cache memory is output before the hit signal is output from the address comparator. Is described in Japanese Patent Application Laid-Open No. 4-252343.

  In the set associative cache memory described in Japanese Patent Application Laid-Open No. 4-328656, it is possible to reduce the power consumption at the time of reading data, but it is not considered to reduce the time lag of reading data. There was a problem.

  In the set associative cache memory described in Japanese Patent Laid-Open No. 4-252343, it is possible to reduce the time lag of data reading. However, when a plurality of continuous areas are alternately accessed, a way is set. There is a problem in that the system does not have a mechanism for correctly predicting and does not consider a time lag in reading data from a set associative cache memory having an address translation buffer.

  SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object of the present invention is to reduce power consumption and reduce a time lag in data reading in a set associative memory device. It is an object of the present invention to provide a technology that can be used.

  Another object of the present invention is to provide a technique capable of reducing power consumption and reducing a time lag at the time of reading data in a set associative memory device including an address translation buffer. It is in.

Another object of the present invention is to provide a set associative memory device having an address translation buffer, which can reduce the time lag of data reading when several continuous areas are alternately accessed. To provide technology.
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

(1) A tag storage unit for storing a tag, a data storage unit for storing data, and a part of an access address and a tag stored in the tag storage unit are compared to determine which way has been hit. In a set associative memory device including a way determiner that outputs a signal, and a data selector that selects data of a data storage unit of the selected way based on a way selection signal, a predicted value of the way determination signal is calculated. Means for activating only a data storage unit of a way predicted based on a predicted value from the way predicting unit to be generated, a means for inputting the predicted value as a way selection signal to a data selector, A way prediction determination unit that compares a way determination signal from a determiner with the predicted value and outputs a way prediction determination signal when the two do not match, Characterized by comprising a means for changing the way the determination signal indicating the hit way prediction value of the way prediction unit based on a way prediction determination signal from tough.

(2) The means of (1), further comprising means for activating only the tag storage unit of the way predicted based on the predicted value from the way prediction unit.

(3) In the means of the above (1) or (2), the way prediction section has a plurality of prediction way latches for storing way number values, and when accessing a plurality of continuous areas, And outputting the way number value stored in the predicted way latch as the predicted value of the way determination signal.

(4) In the above-mentioned means (1) to (3), the memory device further includes a set associative type address translation buffer, and the way determinator of the memory device is configured to store the TLB data from the address translation buffer and the tag. The address translation buffer compares the tag stored in the storage unit and outputs a way determination signal indicating which way has been hit, and the address translation buffer includes a TLB tag storage unit for storing a TLB tag, and a TLB for storing TLB data. A data storage unit, a TLB way determination unit that compares a part of the access address with a TLB tag stored in the TLB tag storage unit and outputs a TLB way determination signal indicating which way has been hit, and a TLB way determination A TLB way predictor for generating a predicted value of a signal, and a predicted value based on a predicted value from the TLB way predictor. Means for activating only the TLB data storage section of the selected TLB way, and TLB data which receives a prediction value from the TLB way prediction section as a way selection signal and selects TLB data in the TLB data storage section of the predicted way. A selector, a TLB way determination signal from the TLB way determination unit, which compares the TLB way determination signal from the TLB way determination unit with the predicted value, and outputs a TLB way prediction determination signal when the two values do not match. Means for changing the prediction value of the TLB way prediction unit to a TLB way determination signal indicating a hit way based on the prediction determination signal.

(5) The means according to (4), further comprising means for activating only the TLB tag storage unit of the way predicted based on the predicted value from the TLB way prediction unit.

(6) In the means of (4) or (5), when the TLB way prediction unit has a plurality of TLB prediction way latches for storing way number values and accesses a plurality of continuous areas, TLB way number values stored in a plurality of corresponding TLB prediction way latches are output as prediction values of a TLB way determination signal.

(7) A tag storage unit for storing a tag, a data storage unit for storing data, and a part of an access address and a tag stored in the tag storage unit are compared to determine which way has been hit. In a set associative memory device including a way determiner that outputs a signal and a data selector that selects data of a data storage unit of a way selected based on a way selection signal, a plurality of memories each storing a way number value A way prediction unit having a prediction way latch, and when accessing a plurality of continuous areas, a way prediction unit that outputs a number value of a way stored in a corresponding plurality of prediction way latches as a prediction value of a way determination signal; Means for inputting a predicted value as a way selection signal to the data selector, and comparing the way determination signal from the way determiner with the predicted value, A way prediction determination unit that outputs a way prediction determination signal in the case; and means for changing a prediction value of the way prediction unit to a way determination signal indicating a hit way based on the way prediction determination signal from the way prediction determination unit. It is characterized by the following.

(8) In the means of the above (7), the memory device further comprises a set associative address translation buffer, and the way determinator of the memory device stores the TLB data from the address translation buffer and the tag storage unit. The address conversion buffer compares the stored tag with the stored tag and outputs a way determination signal indicating which way is hit. The address translation buffer stores a TLB tag and a TLB data storage that stores TLB data. And a TLB way discriminator that compares a part of the access address with the TLB tag stored in the TLB tag storage unit and outputs a TLB way decision signal indicating which way has been hit, and stores the way number value. A plurality of TLB prediction way latches, and a plurality of TLB prediction way latches are provided. A TLB way prediction unit that outputs the number value of the TLB way stored in the B prediction way latch as a prediction value of the TLB way determination signal, and a prediction value from the TLB way prediction unit is input as a selection signal, and the predicted way A TLB data selector for selecting TLB data in a TLB data storage unit, a TLB way determination signal from a TLB way determiner, and the predicted value, and a TLB way prediction determination for outputting a TLB way prediction determination signal when they do not match. And a means for changing the prediction value of the TLB way prediction unit to a TLB way determination signal indicating a hit way based on the TLB way prediction determination signal from the TLB way prediction determination unit.

  According to the means described in the above item (1) or (2), in the memory device of the set associative system, which way is hit by the way prediction unit, and the data storage unit of the predicted way, or Since only the predicted tag storage unit and data storage unit are operated, it is possible to reduce the power consumption for operating the memory device and reduce the time lag of data reading.

  According to the means described in the above item (3), which way is hit by the way prediction unit, the data storage unit of the predicted way, or the predicted tag storage unit and the data storage unit In the memory device of the set associative system in which only the section is operated, when accessing a plurality of continuous areas, the number value of the way stored in the plurality of predicted way latches of the way predicting section is used to predict the way determination signal. Since it is used as a value, it is possible to reduce the power consumption for operating the memory device and reduce the time lag of data reading when alternately accessing some continuous areas.

  According to the means described in (4) or (5), in a set associative memory device having an address translation buffer, which way of the address translation buffer is determined by the TLB way prediction unit of the address translation buffer. A hit is predicted, and the TLB data storage unit of the predicted way or only the predicted TLB tag storage unit and the TLB data storage unit is operated, and the way prediction unit of the memory device performs the operation of the memory device. Since a way to be hit is predicted and only the predicted way data storage unit or the predicted tag storage unit and the predicted data storage unit are operated, the memory device including the address translation buffer is operated. Power consumption for data read and data read time. It is possible to reduce the grayed.

  According to the means described in the above item (6), the TLB way prediction unit of the address translation buffer predicts which way of the address translation buffer will hit, and the TLB data storage unit of the predicted way, or Only the predicted TLB tag storage unit and the TLB data storage unit are operated, and the way prediction unit of the memory device predicts which way of the memory device is to be hit. Alternatively, in a set associative memory device having an address translation buffer, which operates only the predicted tag storage and data storage, when accessing a plurality of continuous areas, Plurality of predictions by TLB way predictor and way predictor of memory device Since the way number value stored in the way latch is used as the predicted value of the TLB way determination signal of the address translation buffer and the predicted value of the way determination signal of the memory device, when several consecutive areas are alternately accessed, Power consumption for operating the memory device can be reduced, and a time lag of data reading can be reduced.

  According to the means described in the above item (7), in a set associative memory device, a plurality of continuous areas are accessed by a way prediction unit having a plurality of prediction way latches for storing way number values. In this case, which way is hit is predicted, so that when several consecutive areas are alternately accessed, the time lag of data reading can be reduced.

  According to the means described in the above item (8), in a set associative memory device having an address translation buffer, when accessing a plurality of continuous areas, a plurality of ways for storing way number values are stored. A TLB way prediction unit having a TLB prediction way latch predicts which way in the address translation buffer will be hit, and a way prediction unit having a plurality of prediction way latches for storing the number value of the way, Since the way is predicted to be hit, the time lag of data reading can be reduced.

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
(1) In a memory device of the set associative system, a way prediction unit predicts which way will be hit, and only the data storage unit of the predicted way or only the predicted tag storage unit and the data storage unit are operated. As a result, power consumption for operating the memory device can be reduced, and a time lag of data reading can be reduced.

(2) In a set associative memory device in which a way prediction unit predicts which way will be hit, when accessing a plurality of continuous areas, the memory is stored in a plurality of prediction way latches of the way prediction unit. Since the way number value thus used is used as the predicted value of the way determination signal, it is possible to reduce the data read time lag when several consecutive areas are alternately accessed.

(3) In a set associative memory device having an address translation buffer, a TLB way prediction unit of the address translation buffer predicts which way of the address translation buffer will be hit, and a TLB data storage unit of the predicted way; Alternatively, while only the predicted TLB tag storage unit and TLB data storage unit are operated, which way of the memory device is hit by the way prediction unit of the memory device, the data storage of the predicted way is performed. , Or only the predicted tag storage and data storage are operated, so that the power consumption for operating the memory device having the address translation buffer is reduced, and the time lag of data reading is reduced. It is possible to do.

(4) The TLB way prediction unit of the address translation buffer predicts which way in the address translation buffer will hit, and the TLB data storage unit of the predicted way, or the predicted TLB tag storage unit and TLB data storage unit Of the memory device is predicted by the way prediction unit of the memory device, and the data storage unit of the predicted way, or the predicted tag storage unit and the data storage unit In a set associative memory device having an address translation buffer, which operates only a plurality of regions, when a plurality of continuous areas are accessed, a plurality of TLB way prediction units of the address translation buffer and a plurality of way prediction units of the memory device are used. Number of way stored in predicted way latch Is used as a predicted value of the TLB way determination signal of the address translation buffer and the way determination signal of the memory device. Therefore, when several continuous areas are alternately accessed, the power consumption for operating the memory device is reduced. It is possible to reduce the time lag of data reading.

(5) In a memory device of the set associative system, a way prediction unit having a plurality of prediction way latches for storing way number values predicts which way will hit when accessing a plurality of continuous areas. Thus, when several consecutive areas are alternately accessed, it is possible to reduce the data read time lag.

(6) In a set-associative memory device having an address translation buffer, when accessing a plurality of continuous areas, an address is obtained by a TLB way prediction unit having a plurality of TLB prediction way latches for storing way number values. Since a way prediction unit having a plurality of prediction way latches for storing way number values is predicted by predicting which way in the conversion buffer will be hit, The time lag of data reading can be reduced.

(7) By using the memory device according to the present invention as a cache memory of a processor, the power consumption of the cache memory can be reduced, and the operation of the cache memory can be performed at high speed. Can be realized.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and a repeated description thereof will be omitted.
FIG. 1 is a block diagram showing a schematic configuration of a cache which is an embodiment (Embodiment 1) of the memory device of the present invention, and is a diagram showing an example in which the cache of Embodiment 1 is applied to a processor.

  In FIG. 1, the processor includes a processor main body 182, an address translation buffer (hereinafter, referred to as TLB) 191, a cache 192, a cache way prediction unit 193, and a cache way prediction determination unit 194.

  The processor main body 182 includes an address generation unit 190 and a data processing unit 195.

  The TLB 191 is a two-set associative memory, and the cache 192 is a two-set associative memory for predicting ways.

  FIG. 2 is an enlarged block diagram showing a more detailed configuration of the cache 192, the cache way prediction unit 193, and the cache way prediction determination unit 194 shown in FIG. 1. FIG. 3 is a block diagram showing the TLB 191 shown in FIG. FIG. 2 is an enlarged block diagram showing a more detailed configuration of FIG.

  FIG. 4 is a diagram showing a time chart of the processor shown in FIG.

  FIG. 4 is a diagram showing a time chart when the way 0 of the cache is predicted and the prediction hits.

  First, the outline of the operation of the processor shown in FIG. 1 will be described with reference to FIGS.

  The processor shown in FIG. 1 is processed by pipeline control.

  In FIG. 4, a numeral 401 indicates an instruction number, and an area in which 1 is written indicates that instruction 1 is being processed.

  Hereinafter, the processing of the instruction 1 will be described.

  As shown in FIG. 1, a portion including the TLB 191, the cache 192, the cache way prediction unit 193, and the cache way prediction determination unit 194 is divided into a memory unit 180 and a way determination unit 181 according to a difference in operation timing. .

  At time 1, the address generation unit 190 generates an address, and outputs the address as the address 100 at the next time.

  At time 2, the memory unit 180 outputs the data 147 to the data processing unit 195 one cycle after inputting the address 100.

  At this time, the cache prediction way signal 151 which is an output signal of the cache way prediction unit 193 indicates the way 0, and the cache data storage units 140 and 141 of the memory unit 180 indicate the predicted way, that is, the way 0 of the way 0. Only the cache data storage unit 140 operates.

  Then, the data read from the cache data storage unit 140 is output as data 147.

  At time 3, the data processing unit 195 inputs and processes the data 147.

  At time 3, the way determination unit 181 determines whether the data 147 read from the memory unit 180 is data of a correct way.

  The memory unit 180 and the way determination unit 181 can perform processing by a pipeline method.

  That is, when instruction 1 is being processed by way determination unit 181 at time 3, instruction 2 is processed by memory unit 180.

  If the way determination unit 181 determines that the data of all the instructions is the correct way data (that is, if the way prediction hits), the time chart and data as shown in FIG. 4 are processed.

  Next, the operation of the processor shown in FIG. 1 will be described in detail with reference to FIGS.

  First, the operation of the memory unit 180 at time 2 will be described.

  First, the logical page number upper bits 103 are stored in the latch 105.

  The logical page number lower bits 102 are input to the TLB tag storage units (110, 111) and the TLB TLB data storage units (120, 121), respectively.

  Then, the TLB tag storage units (110, 111) and the TLB data storage units (120, 121) operate, and their outputs are stored in the latches 116, 117, 126, and 127, respectively.

  On the other hand, the address offset 101 within the page is input to the cache tag storage units (130, 131) and the cache data storage units (140, 141).

  Then, the cache tag storage units (130, 131) operate to output tag values to the cache tags (132, 133), respectively, and the values are stored in the latches (136, 137), respectively.

  Further, a cache prediction way signal 151 is output from the cache way prediction unit 193.

  The value of the signal 151 indicates the predicted way, ie, way 0.

  The signal 151 is decoded by the way decoder 160 and input to the cache data storage (140, 141).

  At this time, since the value of signal 151 indicates way 0, way decoder 160 outputs signal 161 for operating data storage unit 140 of way 0.

  The signal 161 causes the data storage unit 140 to operate, and outputs data 142. In this case, the data storage unit 141 does not operate.

  The data selector 144 receives the predicted way data 142 and the cache predicted way signal 151.

  In the data selector 144, the way indicated by the cache prediction way signal 151, that is, the data 142 of the way 0 is selected and output as the data 145.

  The cache prediction way signal 151 is stored in the latch 152.

  The above processing is performed in one cycle.

  FIG. 7 is a diagram showing a configuration of the way decoder 160.

  The cache prediction way signal 151 is a 2-bit signal, and includes a signal indicating that the way 0 has been predicted and a signal indicating that the way 1 has been predicted.

  The way decoder 160 decomposes the 2-bit signal into 1-bit units and sets a signal indicating that the way 0 is predicted as the cache way 0 enable signal 161 and a signal indicating that the way 1 is predicted as the cache way 1 Each is output as an enable signal 162.

  Next, the operation of the way determination unit at time 3 will be described.

  Based on the logical page number upper bit stored in the latch 105, the TLB tag stored in the latch (116, 117), and the physical page number stored in the latch (126, 127), the TLB way determination unit 114 The value of the physical page number 125 is generated by the physical page number selector 124.

  Further, based on the cache tag stored in the latch (136, 137) and the physical page number 125, a value is output to the cache way determination signal 135 by the cache way determination unit 134.

  The cache way determination signal 135 is a 2-bit signal. The 1-bit signal indicating whether the physical page number 125 and the cache tag 138 of the way 0 match, and whether the physical page number 125 and the cache tag 139 of the way 1 match. Is constituted by a 1-bit signal indicating

  The cache way prediction determining unit 154 determines whether the way prediction of the cache 192 has missed based on the value of the cache predicted way signal 151 stored in the latch 152 and the cache way determination signal 135.

  FIG. 6 is a block diagram showing a more detailed configuration of the cache way prediction determining unit 194 including the cache way prediction determining unit 154 shown in FIG.

  The signal 153 indicating the predicted way of the cache 192 is a 2-bit signal, and includes a signal 710 indicating that the way 0 has been predicted and a signal 711 indicating that the way 1 has been predicted.

  The cache way determination signal 135 is a 2-bit signal, and includes a signal 712 indicating that the way 0 has hit and a signal 713 indicating that the way 1 has hit.

  AND operator 700 outputs 1 when way 0 is predicted and way 0 hits.

  The AND operator 701 outputs 1 when way 1 is predicted and way 1 is hit.

  The cache way prediction determination prohibition signal 704 is a signal that outputs 1 when the cache way prediction determination is not performed, and outputs 0 at time 3.

  The OR operator 705 outputs 1 when way 0 is predicted and way 0 is hit, or when way 1 is predicted and way 1 is hit.

  That is, the OR operator 705 outputs 1 when the cache way prediction hits.

  The NOT operator 707 outputs a value of 1 to the cache way prediction determination signal 155 when the way prediction of the cache is missed.

  At time 3, the process related to the instruction 1 is performed by the cache way prediction determining unit 154, and the value of the output signal 702 of the AND operator 700 becomes 1 because the way 0 is predicted and the way 0 is hit.

  Then, the value of the cache way prediction determination signal 155 becomes 0, indicating that the cache way prediction signal 155 way prediction has hit.

  If the way prediction hits, instructions 1 and 2 can be executed in a pipeline as shown in FIG.

  Next, a case where the way 1 of the cache 192 hits even though the way 0 is predicted by the cache way prediction unit 193 will be described.

  In this case, the way prediction has been missed.

  When the way 1 of the cache 192 hits, the value of the cache way determination signal 135 indicates the way 1, and the value of the signal 712 and the value of the signal 713 shown in FIG.

  On the other hand, since the way 0 is predicted, the value of the signal 710 is 1 and the value of the signal 711 is 0, so that the outputs of the AND operators 700 and 701 are both 0, the value of the signal 706 is 0, and The value of the way prediction determination signal 155 becomes 1.

  That is, the cache way prediction determination signal 155 indicates a way prediction miss.

  When the value of the cache way prediction determination signal 155 becomes 1, exceptional processing is executed.

  FIG. 5 is a diagram showing a time chart in the case described above.

  FIG. 5 is a time chart when the way 0 is predicted by the instruction 1 and the way prediction is missed, and the way 1 is predicted after the instruction 2 and the way prediction is hit.

  At time 3, if the cache way prediction determination signal 155 of the instruction 1 indicates a way prediction miss, a pipeline control signal 156 is output, and the processor main body 182, TLB 191, and cache 192 to be performed at time 3 are output. Suppress the operation.

  In the TLB 191, the processing of the next instruction, that is, the instruction 2 is started, but is suppressed in the middle.

  At time 3, the cache way determination signal 135 is stored in the latch 150 by the cache way prediction determination signal 155.

  As a result, the value of the cache prediction way signal 151 is replaced.

  That is, from time 4, the value of the cache prediction way signal 151 indicates the way 1 which is the way in which the cache hit at time 3.

  At time 4, a cache prediction way signal 151 having a new value is output, and the cache data storage unit 141 of way 1 is operated.

  Way 1 data 143 output from the cache data storage unit 141 is selected by the data selector 144 based on the cache prediction way signal 151 and stored in the latch 146.

  At time 5, the data of way 1 stored in the latch 146 is output from the cache 192 and processed by the data processing unit 195.

  In the first embodiment, not only the data storage unit (140, 141) of the predicted way but also the tag storage of the predicted way is generated by the cache predicted way signal 151 which is an output signal from the cache way prediction unit 193. It is also possible to activate only the units (130, 131).

  FIG. 8 is a block diagram illustrating a schematic configuration of an address translation buffer (TLB) and a cache according to another embodiment (embodiment 2) of the memory device according to the present invention. FIG. 9 illustrates an example in which a cache 992 and a cache 992 are applied to a processor.

  The processor shown in FIG. 8 is different from the processor shown in FIG. 1 in that a TLB way prediction unit 996 and a TLB way prediction determination unit 997 are added, and the way of TLB is also predicted.

  The configurations of the TLB way prediction unit 996 and the TLB way prediction determination unit 997 of the second embodiment are the same as those of the cache way prediction unit 193 and the cache way prediction determination unit 194 of the first embodiment.

  The processor body 982, cache 992, cache way prediction unit 993, and cache way prediction determination unit 994 shown in FIG. 8 are respectively the processor body 182, cache 192, cache way prediction unit 193, and cache way prediction determination unit 194 shown in FIG. It corresponds to.

  FIG. 9 is a diagram showing a time chart of the processor shown in FIG.

  FIG. 9 is a diagram showing a time chart when the TLB way 0 is predicted for all the instructions 1 to 4 and the prediction hits.

  The outline of the operation of the processor shown in FIG. 8 will be described with reference to FIGS.

  The processor shown in FIG. 8 is processed by pipeline control.

  In FIG. 9, a numeral 1001 indicates an instruction number, and an area in which 1 is written indicates that instruction 1 is being processed.

  Hereinafter, the processing of the instruction 1 will be described.

  As illustrated in FIG. 9, a part including the TLB 991, the cache 992, the TLB way prediction unit 996, the TLB way prediction determination unit 997, the cache way prediction unit 993, and the cache way prediction determination unit 994 operates. It is divided into a memory unit 980 and a way determination unit 981 according to the difference in timing.

  At time 1, the address generator 990 generates an address, and outputs the address 900 at the next time.

  At time 2, the memory unit 980 outputs the data 947 to the data processing unit 995 one cycle after inputting the address 900.

  As for the TLB data storage units (920, 921), only the TLB data storage unit 920 of the way predicted by the TLB way prediction unit 996 operates.

  Here, since the TLB way prediction unit 996 predicts the way 0, the TLB prediction way signal 961 output from the TLB way prediction unit 996 indicates the way 0.

  Then, the TLB prediction way signal 961 is input to the TLB 991, and the TLB data storage unit 920 operates.

  As for the cache data storage units (940, 941), only the cache data storage unit 940 of the way predicted by the cache way prediction unit 993 operates, and the data read from the cache data storage unit 940 is used as data 947. Is output.

  At time 2, the TLB tag storage units (910, 911) and the cache tag storage units (930, 931) operate.

  Then, at time 3, the data processing unit 995 receives and processes the data 947.

  Further, the TLB 991 compares the upper bit of the logical page number 904 with the TLB tag read from the TLB tag storage unit (910, 911) at the previous time, and outputs a TLB way determination signal 960.

  Further, the way predicted by the TLB way prediction unit 996 at the previous time from the TLB 991, that is, the physical page number 925 read from the TLB data storage unit 920 of the way 0 is output and sent to the cache 992.

  The cache 992 compares the physical page number 925 with the cache tag read from the cache tag storage unit (930, 931) at the previous time, and outputs a cache way determination signal 935.

  At time 3, the TLB way prediction determining unit 997 determines whether or not the TLB way prediction has missed based on the value of the TLB way determination signal 960 and the value of the TLB prediction way signal 961 output at the previous time. I do.

  Further, at time 3, the cache way prediction determining unit 994 determines whether the cache way prediction at time 2 has missed.

  If the TLB way prediction and the cache way prediction are both hits, a time chart as shown in FIG. 10 is obtained.

  Next, a case will be described in which way 1 of the TLB is hit despite prediction of way 0 of the TLB.

  In this case, the value of the TLB way determination signal 960 indicates way 1, and the TLB way prediction determination unit 997 determines that the TLB way prediction has failed.

  FIG. 10 is a diagram showing a time chart in the case described above.

  In this case, the value 1 is output to the TLB way prediction determination signal 962, and the value 1 indicates a TLB way prediction error.

  Then, the value of the TLB way determination signal 960 is stored in the TLB way prediction unit 996 by the TLB way prediction determination signal 962.

  By this storage, the value of the TLB way determination signal 960 at time 3, that is, the value indicating the way 1 is output to the TLB prediction way signal 961 from time 4.

  At time 3, the pipeline control signal 963 is output, and the operations of the processor main body 982, TLB 991, and cache 992 to be performed at time 3 are suppressed.

  In the TLB 991 and the cache 992, the processing of the next instruction, that is, the instruction 2, has been started, but is suppressed in the middle.

  At time 4, a new value is output as the TLB prediction way signal 961.

  The value of the TLB prediction way signal 961 indicates the way 1, and the TLB data storage unit 921 of the way 1 is operated.

  On the other hand, at time 4, the cache 992 does not operate and holds the internal state.

  At time 5, the output of the TLB data storage unit 921 is output to the physical page number 925.

  Then, the cache way determination signal 935 is output from the cache 992 and sent to the cache way prediction determination unit 994, and the cache way prediction determination unit 994 determines whether or not the cache way prediction has missed.

  In the second embodiment, not only the TLB data storage unit (920, 921) of the predicted way but also the TLB of the predicted way is determined by the TLB prediction way signal 961 which is an output signal from the TLB way prediction unit 996. It is also possible to activate only the tag storage units (910, 911).

  FIG. 11 is a block diagram showing a schematic configuration of a cache which is another embodiment (Embodiment 3) of the memory device of the present invention, and shows an example in which the cache of Embodiment 3 is applied to a processor.

  FIG. 11 is obtained by changing the address generation unit 190 of the processor shown in FIG. 1 to an address generation unit 1290, changing the cache way prediction unit 193 to a cache way prediction unit 1293, and further adding an address control unit 1296.

  The processor main body 1282, TLB 1291, cache 1292, cache way prediction unit 1293, and cache way prediction determination unit 1294 shown in FIG. It corresponds to the prediction determination unit 194.

  The address generation unit 1290 has four address latches 1220 to 1223.

  The third embodiment is characterized in that the cache way prediction unit 1293 has cache prediction way latches 1230 to 1233 corresponding to the address latches 1220 to 1223, respectively.

  The address generation unit 1290 has four address latches 1220 to 1223, selects one of the outputs of the latches by an address selector 1224, and passes the address 1200 after one cycle via an address adder 1226 and a latch 1228. Output to

  On the other hand, the cache way prediction unit 1293 has four cache prediction way latches 1230 to 1233 corresponding to the address latches 1220 to 1223, and the output of the cache prediction way latch corresponding to the selected address latch in the address selector 1224. Is selected by the cache prediction way selector 1234 and output as the cache prediction way signal 1212.

  At this time, the address selector 1224 receives the address latch read selection signal 1205 output from the address control unit 1296, and the cache prediction way selector 1234 receives the address latch read selection signal 1205 as a signal delayed by one cycle from the address latch read signal 1205. A certain cache prediction way latch read selection signal 1208 is input.

  When the output of the address latch 1220 is selected by the address selector 1224, the output of the cache prediction way latch 1230 is selected by the cache prediction way selector 1234.

  Similarly, when the outputs of the address latches 1221, 1222, and 1223 are selected by the address selector 1224, the outputs of the cache prediction way latches 1231, 1232, and 1233 are selected by the cache prediction way selector 1234, respectively.

  The address adder 1226 is used to add a certain value to the value of the address latch when successive address areas are successively accessed using the same address latch.

  When the way prediction fails, the value of the cache way determination signal 1211 is written to the cache prediction way latch used to output the value to the cache prediction way signal 1212.

  A mechanism for performing this writing is a latch 1240 and a decoder 1242.

  Latch 1240 stores and stores the value of cache prediction way latch read selection signal 1208 input to cache prediction way selector 1234.

  When the way prediction misses, the value of the cache way prediction determination signal becomes 1.

  When the value of the cache way prediction determination signal 1214 input to the decoder 1242 becomes 1, the decoder 1242 decodes the value stored in the latch 1240 to set any one of the latch set signals 1243 to 1246 to 1. .

  FIG. 12 is a diagram showing a circuit configuration of the decoder 1242 shown in FIG.

  11 corresponds to the decode input signal 1400, the signals 1243 to 1246 correspond to the decode output signals 1430 to 1433, and the signal 1214 illustrated in FIG. 11 corresponds to the decode enable signal 1410.

  The decode input signal 1400 is composed of a 2-bit binary number, and can be decomposed into a 0-bit signal 1402 and a 1-bit signal 1403.

  The decoder sets one of the decode output signals 1430 to 1433 to 1 according to the value of the 2-bit signal.

  However, when the value of the decode enable signal 1410 is 0, the values of the decode output signals 1430 to 1433 are all 0.

  When the latch set signals 1243 to 1246 are 1, the value of the cache way determination signal 1211 is written to the cache prediction way latches 1230 to 1233, respectively.

  FIG. 13 is a diagram illustrating an example of data stored in the data storage unit of the cache 1292.

  In FIG. 13, reference numeral 1700 denotes a way 0 cache data storage unit, and 1701 denotes a way 1 cache data storage unit.

  Reference numeral 1710 denotes a line of the cache 1292. In this example, four data are stored in one line.

  Reference numeral 1711 denotes data stored in the cache 1292.

  Reference numeral 1712 denotes an auxiliary address of the data 1711.

  Generally, in the cache 1292, data is managed for each line, and data of the same line is stored in the same way.

  In the example shown in FIG. 13, addresses 200 to 203 correspond to the same line, and data B [0] to data B [3] are stored in the same way.

  Similarly, data A [0] to data A [3] are stored in the same way.

  Data A is character string data, data A [0] is the first character data, data A [1] is the second character data, data A [2] is the third character data, and data A [2] is the data A [3] means the fourth character data.

  Data B is similar character string data.

  Here, an example of a process of sequentially reading character data from the cache 1292 in order to compare the character string data A and the character string data B will be described.

  In the comparison of character strings, character data A [0] is character data B [0], character data A [1] is character data B [1], and similarly, character data A [3] is character data B [1]. Each is compared with [3].

  Therefore, the order of character data A [0], character data B [0], character data A [1], character data B [1], and so on in the same manner, character data A [3], character data B [3] , Character data is read from the cache 1292.

  Hereinafter, the operation of the processor shown in FIG. 11 will be described with reference to the time chart of FIG.

  In FIG. 14, reference numeral 1601 denotes a value of a signal output from a latch or a cache or a value of a signal.

  At time 0, it is assumed that the head address 100 of the character string data A is stored in the address latch 1220 and the head address 200 of the character string data B is stored in the address latch 1221.

  In the processor shown in FIG. 11, the address latch 1220 is used to read each character data of the character string data A. When reading the character data A [0], the address adder 1226 sets the value 0 to the character data A [1]. Is read by the address adder 1226, and similarly, when the character data A [3] is read, the value 3 is added by the address adder 1226 to the value of the address latch 1220.

  Similarly, the address latch 1221 is used to read out each character data of the character string data B.

  At time 0, the values of both the cache prediction way latches 1230 and 1231 are 0.

  That is, the prediction ways corresponding to the address latch 1220 and the address latch 1221 are both 0.

  In this time chart, the reading process is started from time 1.

  At time 1, in order to read the character data A [0] at the address 100, the value of the address latch selection signal 1205 becomes 0, the value 100 of the address latch 1220 is selected, and is output as the address latch selection output signal 1225.

  Then, it is output to the address 1227 via the address adder 1226.

  Nothing is added by the address adder 1226, and the value of the address 1227 remains at 100.

  At time 2, the value of the cache prediction way latch 1230 corresponding to the address latch 1220 is changed to the value 0 of the cache prediction way latch 1230 by the value 0 of the cache prediction way latch read selection signal 1208 which is a signal delayed by one cycle from the value of the address latch selection signal 1205. The signal 1212 is read.

  As a result, the cache data storage unit way 0 (1700) operates.

  At time 3, the cache way determination signal 1211 is output. However, as shown in FIG. 13, the value of the cache way determination signal 1211 is 1 because the data A [0] at the address 100 exists in the way 1 of the cache.

  The cache way prediction determining unit 1294 compares the value 1 of the cache way determination signal 1211 with the value 0 of the cache predicted way signal 1212 output at time 2, but because they do not match, a way prediction miss occurs.

  Therefore, the pipeline control signal 1213 is issued, and the value of the cache way prediction determination signal 1214 is set to 1.

  The decoder input signal 1241 which is a signal delayed by one cycle from the cache prediction way latch read selection signal 1208 is input to the decoder 1242, and the latch set signal 1243 is input to the cache prediction way latch 1230 which has read at time 2. .

  As a result, the value 1 of the cache way determination signal 1211 is written to the cache prediction way latch 1230.

  That is, at time 3, the prediction way corresponding to the address latch 1220 is changed to 1.

  At time 4, the value of the cache prediction way latch 1230 becomes 1, the correct way prediction value 1 is output to the cache prediction way signal 1212, and character data A [0] is output from the cache data storage way 1 (1701). Is read.

  At time 5, A [0] is output to the output data signal 1215 of the cache.

  On the other hand, at time 2, in order to read the character data B [0] at the address 200, the value of the address latch selection signal 1205 becomes 1 and the value 200 of the address latch 1221 is selected and output to the address latch selection output signal 1225. You.

  Then, it is output to the address 1227 via the address adder 1226.

  In the address adder 1226, nothing is added and the value of the address 1227 remains at 200.

  At time 3, this value 200 is output from the address 1200 from the latch 1228.

  Further, the value 1 of the address latch selection signal 1205 is output from the latch 1209 to the cache prediction way latch read selection signal 1208.

  At time 4, due to cache prediction miss processing, the value of the address latch selection signal 1205 and the value of the cache prediction way latch read selection signal 1208 are temporarily changed to read the character data A [0]. At time 5, the same value as at time 3 is restored again.

  Here, the latches 1209 and 1228 are latches with a value recovery function, and the circuit configuration is shown in FIG.

  In FIG. 15, a latch 1800 with a recovery function corresponds to the latch 1209 or 1228, an input signal 1801 corresponds to the signal 1205 or 1227, and an output signal 1802 corresponds to the signal 1208 or 1200.

  The latch with value recovery function 1800 normally functions as a simple latch that outputs the input signal 1801 to the output signal 1802 using the latch 1810, but stores the value one cycle before in the latch 1811.

  At time 3 when it is determined that a cache way prediction miss for reading the character data A [0] has been determined, the address of the next character data B [0] or the cache prediction way latch read selection signal (hereinafter, character data B [0 ] (Referred to as a read parameter) is output from the latch 1800 with the recovery function. The character data A [0] read parameter is stored in the latch 1811.

  At time 4, based on the pipeline control signal 1213 issued at this time, the character data A [0] read parameter stored in the latch 1811 is read, and the character data A [0] having the way prediction error is read. The process is executed again, and at time 5, the character data B [0] read parameter is read from the latch 1810 and the process returns to the normal process.

  At time 5, the cache prediction way latch is selected by the value 1 of the cache prediction way latch read selection signal 1208, and the value 0 is output to the cache prediction way signal 1212.

  As a result, the cache data storage unit way 0 (1700) operates to read out the character data B [0].

  Since the character data B [0] is stored in the way 0 as shown in FIG. 13, the way prediction becomes a hit.

  At time 6, the value of character data B [0] is output to cache output data signal 1215.

  After the reading of the above two character data, the value of the cache prediction way latch 1230 corresponding to the address latch 1220 becomes 1 and the value of the cache prediction way latch 1231 corresponding to the address latch 1221 becomes 0.

  Therefore, when character data A [1], B [1], A [2], B [2], A [3], and B [3] are subsequently read, the address latches 1220, 1221, and 1220 respectively. , 1221, 1220, 1221, the values of the cache prediction ways are all correct, and the way prediction hits.

  As described above, in the present embodiment, the possibility of hitting the way prediction increases even when several consecutive areas are alternately accessed.

  FIG. 16 is a block diagram illustrating a schematic configuration of a cache according to another embodiment (fourth embodiment) of the present invention, and is a diagram illustrating an example in which the cache according to the fourth embodiment is applied to a processor.

  Note that FIG. 16 shows only an address generation unit, a cache way prediction unit, and an address control unit used in the processor.

  FIG. 16 shows a processor constructed by replacing the address generation unit 1290, the cache way prediction unit 1293 and the address control unit 1296 shown in FIG. 11 with an address generation unit 1390, a cache way prediction unit 1393 and an address control unit 1396. is there.

  The address generation unit 1390 shown in FIG. 16 is capable of transferring an address from an address latch to an address latch, and outputs an output value of an address latch among the address latches 1320 to 1323 to an address selector 1324 and an address adder. Data can be written to any of the address latches 1320 to 1323 via the 1326.

  The latch set signals 1351 to 1354 are signals for setting the value of the address 1300 in the address latches 1320 to 1323. When the value of the latch set signal 1351 to 1354 is 1, the address 1300 is applied to the address latches 1320 to 1323, respectively. The value is set.

  The values of the latch set signals 1351 to 1354 are generated by the decoder 1350 based on the address latch write enable signal 1307 and the address latch write selection signal 1306.

  The address latch write enable signal 1307 is a signal that becomes 1 when an address is transferred to the address latches 1320 to 1323.

  When this signal is 1, the address latch write selection signal 1306 is decoded by the decoder 1350, and the latch set signals 1351 to 1354 are output.

  The circuit configuration of the decoder 1350 is the same as that of FIG. 12, and a signal 1306 shown in FIG. 16 is used as a decode input signal 1400, signals 1351 to 1354 shown in FIG. 16 are used as decode output signals 1430 to 1433, and a signal 1307 shown in FIG. Corresponds to the decode enable signal 1410.

  The cache way prediction unit 1393 has cache prediction way latches 1330 to 1333, and can write the cache way determination signal 1311 to the cache prediction way latches 1330 to 1333.

  The cache way prediction unit 1393 can further transfer the value of the cache prediction way latch from the cache prediction way latch to the cache prediction way latch, and output the output of a certain cache prediction way latch among the cache prediction way latches 1330 to 1333. Can be written to any of the cache prediction way latches 1330 to 1333 via the cache prediction way selector 1334.

  The transfer of the cache prediction way is performed when the transfer of the address is performed.

  When the value of the address latch write enable signal 1307 becomes 1 when the address is transferred, the cache predictive way latch write select signal selector 1360 changes the value of the address latch write select signal 1306 to the cache predictive way latch write. The cache prediction way latch write data selector 1362 outputs the value of the cache prediction way signal 1312 to the cache prediction way latch write data 1363, and the cache prediction way latch write enable signal selector 1364 outputs the address of the address. The value of the latch write enable signal 1307, that is, the value 1, is output to the cache prediction way latch write enable signal 1365.

  The decoder 1342 decodes the value of the cache prediction way latch write select signal 1361 and outputs latch set signals 1343 to 1346.

  The circuit configuration of the decoder 1342 is also the same as that of FIG. 12. The signal 1361 shown in FIG. 16 is used as the decode input signal 1400, the signals 1343 to 1346 shown in FIG. 16 are used as the decode output signals 1430 to 1433, and the signal 1365 shown in FIG. Corresponds to the decode enable signal 1410.

  Latch set signals 1343 to 1346 are signals for setting the values of cache prediction way latch write data 1363 in cache prediction way latches 1330 to 1333. When the values of latch set signals 1343 to 1346 are 1, respectively, The value of cache prediction way latch write data 1363 is set in way latches 1330 to 1333.

  The operation of the cache way prediction unit 1393 when the value of the address latch write enable signal 1307 is 0 is the same as the operation of the cache way prediction unit 1293 shown in FIG.

  In the third and fourth embodiments, it is possible to predict the way in the address translation buffer (TLB). At this time, as shown in the cache way prediction unit (1293, 1393), the TLB way is predicted. It is also possible to provide a plurality of prediction way latches of the prediction unit.

In addition, the third and fourth embodiments can be applied to a conventional cache that does not activate the data storage unit of the way predicted based on the predicted value or the TLB data storage unit of the TLB. Not even.
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist of the invention. Of course.

FIG. 2 is a block diagram illustrating a schematic configuration of a cache which is an embodiment (Embodiment 1) of the memory device of the present invention, and is a diagram illustrating an example in which the cache of Embodiment 1 is applied to a processor. FIG. 2 is an enlarged block diagram showing a more detailed configuration of a cache, a cache way prediction unit, and a cache way prediction determination unit shown in FIG. 1. FIG. 2 is an enlarged block diagram showing a more detailed configuration of an address translation buffer (TLB) shown in FIG. 1. FIG. 2 is a diagram showing a time chart when a cache way prediction hits in the processor shown in FIG. 1. FIG. 2 is a diagram showing a time chart when a cache way prediction misses in the processor shown in FIG. 1. FIG. 2 is a block diagram illustrating a more detailed configuration of a cache way prediction determination unit illustrated in FIG. 1. FIG. 3 is a diagram showing a configuration of a way decoder shown in FIG. 2. FIG. 13 is a block diagram illustrating a schematic configuration of an address translation buffer (TLB) and a cache according to another embodiment (embodiment 2) of the memory device according to the present invention. FIG. 11 is a diagram illustrating an example in which is applied to a processor. FIG. 9 is a diagram showing a time chart when a way prediction of an address translation buffer (TLB) hits in the processor shown in FIG. 8. FIG. 9 is a diagram showing a time chart when a hit occurs when a way prediction of an address translation buffer (TLB) is missed in the processor shown in FIG. 8. FIG. 16 is a block diagram illustrating a schematic configuration of a cache as another embodiment (third embodiment) of the memory device according to the present invention, and is a diagram illustrating an example in which the cache according to the third embodiment is applied to a processor. FIG. 12 is a diagram illustrating a circuit configuration of the decoder illustrated in FIG. 11. FIG. 12 is a diagram illustrating an example of data stored in a data storage unit of the cache illustrated in FIG. 11. FIG. 12 is a diagram showing a time chart of the processor shown in FIG. 11. FIG. 12 is a diagram illustrating a circuit configuration of a latch with a value recovery function illustrated in FIG. 11. FIG. 16 is a block diagram illustrating a schematic configuration of a cache as another embodiment (fourth embodiment) of the memory device according to the present invention, and is a diagram illustrating an example in which the cache according to the fourth embodiment is applied to a processor. FIG. 11 is a block diagram showing a schematic configuration of a conventional set associative memory.

Explanation of reference numerals

100, 600, 900, 1200, 1227, 1300 Address 101, 601, 901, 1201 In-page offset 102, 602 Logical page number lower bit 103, 603 Logical page number upper bit 104, 604, 904, 1204 Logical page number 110, 111,610,611,910,911 TLB tag storage unit 112,113,612,613 TLB tag 114,614 TLB way determiner 105,116,117,126,127,136,137,146,152,646,1240 , 1340, 1810, 1811 Latches 120, 121, 620, 621, 920, 921 TLB data storage 122, 123, 622, 623, 625, 925, 1210 Physical page numbers 124, 624 Physical page numbers Selectors 130, 131, 630, 631, 930, 931 Cache tag storage units 132, 133, 632, 633 Cache tags 134, 634 Cache way determiners 140, 141, 640, 641, 940, 941, 1700, 1701 Cache data Storage section 144,644 Data selector 150,1230,1231,1232,1233,1330,1331,1332,1333 Cache prediction way latch 154 Cache way prediction decision unit 160 way decoder 180,980 Memory section 181,981 Way decision section 182 , 982, 1282 Processor 190, 990, 1290, 1390 Address generator 191, 691, 991, 1291 TLB
192, 692, 992, 1292 Cache 193, 993, 1293, 1393 Cache way prediction unit 194, 994, 1294 Cache way prediction determination unit 195, 999, 1295 Data processing unit 401, 1001 Instruction numbers 700, 701, 1420 to 1423 AND operator 705 OR operator 707, 1404, 1405 NOT operator 790 Cache way prediction determination control logic 996 TLB way prediction unit 997 TLB way prediction determination unit 1209, 1228, 1800 Latch with value recovery function 1220, 1221, 1222, 1223 , 1320, 1321, 1322, 1323 Address latch 1224, 1324 Address selector 1226, 1326 Address adder 1234, 1334 Cache prediction way selection Decoders 1242, 1342, 1350, 1490 Decoders 1296, 1396 Address control unit 1360 Write selection signal selector 1362 Write data selector 1364 Write enable signal selector 1710 Cache line 1711 Data 1712 Data address.

Claims (3)

A tag storage unit for storing tags,
A data storage unit for storing data,
A way determiner that compares a part of the access address with the tag stored in the tag storage unit and outputs a way determination signal indicating which way has been hit;
A data selector for selecting data in a data storage unit of the selected way based on a way selection signal, the set associative memory device comprising:
A plurality of predicted way latches for storing way number values;
When accessing a plurality of continuous areas, a way prediction unit that outputs a number value of a way stored in a corresponding plurality of prediction way latches as a prediction value of a way determination signal,
Means for inputting the predicted value to a data selector as a way selection signal,
A way prediction signal comparing the way determination signal from the way determiner and the prediction value, and outputting a way prediction determination signal in the case of a mismatch,
Means for changing a prediction value of the way prediction unit to a way determination signal indicating a hit way based on a way prediction determination signal from the way prediction determination unit. The memory device further includes a set associative type address translation buffer,
The way determination unit of the memory device compares the TLB data from the address translation buffer with the tag stored in the tag storage unit, and outputs a way determination signal indicating which way has been hit,
The address translation buffer includes a TLB tag storage unit that stores a TLB tag;
A TLB data storage unit for storing TLB data;
A TLB way determiner that compares a part of the access address with a TLB tag stored in the TLB tag storage unit and outputs a TLB way determination signal indicating which way has been hit;
A plurality of TLB prediction way latches for storing way number values;
A TLB way prediction unit that outputs a TLB way number value stored in a corresponding plurality of TLB prediction way latches as a prediction value of a TLB way determination signal when accessing a plurality of continuous areas;
A TLB data selector to which a prediction value from the TLB way prediction unit is input as a selection signal and selects TLB data in a TLB data storage unit of the predicted way;
A TLB way prediction determination unit that compares a TLB way determination signal from the TLB way determination unit with the prediction value, and outputs a TLB way prediction determination signal when they do not match,
And means for changing a prediction value of the TLB way prediction unit to a TLB way determination signal indicating a hit way based on a TLB way prediction determination signal from the TLB way prediction determination unit. A set associative memory device as described in the above.   3. The set associative method according to claim 2, wherein the TLB way prediction unit further includes means for transferring a number value stored in an arbitrary TLB prediction way latch to another TLB prediction way latch. Memory device.

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