JPH0795309B2 - Set associative cache memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a set associative system capable of easily testing an address tag memory and an LRU (Least Recent-ly Used) bit memory included in a cache system. The method relates to a cache memory.

[Conventional technology]

FIG. 3 is an address configuration diagram and a block diagram of a 4-way set associative cache memory for explaining a conventional method of diagnosing a set associative cache memory. This 4-way set associative cache memory is described on page 205 of the September 1987 issue of "Interface" by CQ Publisher.

In FIG. 3, 1 is an address to access the cache memory, 2 is an address tag which is a part of the address 1, 3 is a set select which is a part of the address 1, and 4 is a part of the address 1. Is a word select, 5 is an address tag memory that holds an address tag in the cache memory, 6 is a valid bit memory that indicates whether the data held in the data block memory 7 described later is valid or invalid, 7 Is a data block memory for holding the data in the cache memory, and 8 is an LR as a replacement priority data storage means for the data of each way.
The LRU bit memory 8 is a U bit memory, and the LRU bit memory 8 is a status register whose data replacement is controlled by an LRU (Least Recently Used) algorithm. Further, 9 is an address tag comparator which compares the data of the addresses held in the address tag 2 and the address tag memory 5 to check whether or not they match, 10 is the word select 4 of the address 1 The first selector selected,
11 is the second selected by the address tag comparator 9
, And a is output data output from the second selector 11.

Next, the operation will be described.

When address 1 is given from the outside, set select 3
The contents of the address tag memory 5 of each way selected in step 1 are sent to the address tag comparator 9, and the contents of the data block memory 7 are also sent to the first selector 10, so that the word data selected by the word select 4 is sent to the second. To selector 11. Then, it is checked whether the content of the address tag memory 5 selected by the address tag comparator 9 and the address tag 2 match, and if there is a matching way, the second selector 11 selects the corresponding way. Way data is output data a
Output as. However, if the address tag comparator 9 does not match, the main memory (not shown) outside the cache memory is read, the data is sent to the MPU, and the data is stored in the data block memory 7 in the cache memory. To do. At this time, the LRU algorithm decides which way to store the data, and that information is the LRU algorithm.
It is stored in the bit memory 8.

Next, a method of diagnosing the address tag memory 5 of this cache memory system will be described.

The basic method is to first access the cache system with an arbitrary address, write an address tag that is a part of the previous address to the tag memory of the entry accessed by the set select 3, and then , When the cache system is accessed with the same cache entry as before, whether or not the cache hit determination and the cache mishit determination are correctly performed is checked. That is, when an address having the same bit pattern sequence as the address tag 2 previously written in the address tag memory 5 is accessed, it is determined to be a cache hit, the content of the data memory is output, and the written address tag 2 It is determined that an address having a bit pattern sequence group different from that is determined as a cache miss and that an external memory access cycle occurs in order to fetch data into the data block memory 7.

At this time, it should be noted that the way in which the address tag 2 is written follows the priority level indicated by the LRU bit of each entry at that time. Therefore, it is necessary to take this point into consideration when creating the test pattern, and to know the state of the LRU bit at the time of giving each test vector.

Next, a method of diagnosing the LRU bit memory 8 of this cache memory will be described.

In this conventional example, since data cannot be directly written to the LRU bit memory 8 from the outside, in order to set the LRU bit memory 8 to a value to be diagnosed, the operation of writing the data of the main memory to the cache memory multiple times is performed. is necessary. In addition, in order to confirm that the LRU bit memory 8 is set to the desired value, it is necessary to perform multiple read operations from the cache memory and multiple write operations of the main memory data to the cache memory. Is. In this case as well, for the same reason as above, it is necessary to grasp the LRU state at each point in time when creating the test pattern.

[Problems to be Solved by the Invention]

Since the test of the address tag memory 5 and the LRU bit memory 8 in the conventional set associative cache memory is performed by the above-described method, the test pattern to write to the address tag memory 5, that is, to which way the tag address is written. It cannot be controlled easily from the outside. Therefore, in creating the test pattern, it is necessary to know the state of the LRU bit, that is, the access history of the way to each entry, which causes the problem of making the test pattern difficult. Further, as is apparent from FIG. 3, since the LRU bit memory 8 itself cannot be directly accessed from the outside,
When creating the test pattern, there are the same problems as described above.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a set associative cache memory that can easily test a tag memory and an LRU.

[Means for Solving the Problems]

A set associative cache memory according to claim 1 of the present invention is a decode circuit for receiving a way selection signal from the outside for designating a specific way and generating a way hit signal, and a decode circuit for receiving a diagnostic mode signal. And a third selector for selecting and outputting one of the way hit signal from the priority order storing means and the way hit signal from the priority storing means.

A set associative cache memory according to claim (2) of the present invention includes a decoding circuit for receiving a way selection signal from the outside for designating a specific way and generating a way hit signal, and a decoding circuit for receiving a diagnostic mode signal. From the decoder circuit and the third selector which selects and outputs one of the way hit signal from the priority order storing means and the way hit signal from the priority storing means, and when the way hit signal from the decoding circuit is selected by the diagnostic mode signal. And a control circuit for updating the contents of the priority storage means according to the hit signal.

[Action]

In the set associative cache memory according to the first aspect, if the diagnostic mode is set to the diagnostic mode, the way is selected by the way selection signal input from the outside.

In the set associative cache memory according to claim (2), if the diagnostic mode is set to the diagnostic mode, the way is selected by the way selection signal input from the outside, and the contents of the priority storage means are selected according to the selection result. Will be updated.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a set associative cache memory which is most suitable for testing the address tag memory 5. In this figure, the same symbols as those in FIG. 3 indicate the same elements, 12 is a diagnostic mode signal, 13 is a way selection signal, 14 is a decoding circuit, and 15 is a decoding circuit.
Is a selector circuit as a third selector, 16 is a way hit signal obtained by decoding the way selection signal 13 by the decoding circuit 14, and 17 is a way generated by the LRU bit memory 8 as priority storage means. It is a hit signal.

Next, the operation will be described.

The normal operation of the 4-way set associative cache memory shown in FIG. 1 is exactly the same as the operation of the conventional cache memory shown in FIG. 3, except for the operation in the diagnostic mode. The procedure for testing the address tag memory in the diagnostic mode is described below.

First, the diagnostic mode signal 12 is set to "1" and the way selection signal 13 is set to a level corresponding to the way to be selected. The way selection signal 13 has the number of bits corresponding to the number of ways provided in the cache system. Next, the contents of the address tag memory 5 of each way are cleared and the cache system is accessed with an arbitrary address. In the accessed entry, there is no address tag 2 that should hit in any way. Therefore, an external bus cycle occurs to fetch data to the external memory, and part of the previous address is the address tag. Is stored in the address tag memory 5. At this time, when the diagnostic mode signal 12 is at "1" level, the selector circuit 15 selects the way hit signal 16, so the way in which the address tag 2 is written is determined by the way selection signal 13. By repeating this operation for all ways of all entries, desired test patterns can be written in all bits of the address tag memory 5.

At this time, it should be noted that when writing a test pattern to the address tag memory 5 of each entry, the way to which the pattern is written does not depend on the contents of the LRU bit memory 8 and the way selection signal 13 The point is to follow the level only. Therefore, without knowing the contents of the LRU bit memory 8, the test pattern can be written in one cycle without exception in any way of any entry.

Therefore, all entries of this cache system are sequentially accessed by an appropriate address pattern group, that is, an address pattern group which should be hit by the cache and an address pattern group which should be hit by the cache, and the cache is correctly judged as a hit or a mishit. By checking whether or not the address tag memory 5 can be tested.

Further, FIG. 2 is a block diagram showing an embodiment of the set associative cache memory according to claim (2) which is most suitable for the test of the LRU bit memory 8. In this figure, the same reference numerals as those in FIG. 1 indicate the same parts, and 18 is a control circuit, and in the diagnostic mode, the way designated by the way hit signal 16 obtained by decoding the way selection signal 13 is
It has a function of updating the LRU bit memory 8 as if accessed.

Therefore, according to this embodiment, when the test of the address tag memory 5 is carried out by the previous procedure, the LR at each time point is
The bit contents of the U bit memory 8 can be grasped from a very simple logic. Whether or not the LRU bit memory 8 is set to a desired value needs to be indirectly known by several subsequent read operations, but the setting operation can be easily performed as described above.

〔The invention's effect〕

As described above, the set associative cache memory according to claim (1) of the present invention includes a decoding circuit for receiving a way selection signal from the outside for designating a specific way and generating a way hit signal, and a diagnostic mode. Since the third selector which receives the signal and selects and outputs one of the way hit signal from the decoding circuit and the way hit signal from the priority order storing means is provided, the way can be selected directly from the outside. This makes it possible to significantly simplify the algorithm for creating a test pattern for diagnosing the address tag memory.

A set associative cache memory according to a second aspect of the present invention includes a decoding circuit that receives a way selection signal from the outside for designating a specific way and generates a way hit signal, and a decoding circuit that receives a diagnostic mode signal. Of the way hit signal and the way hit signal from the priority storing means, and a third selector for selecting and outputting one of the way hit signals and the way hit signal from the decoding circuit by the diagnostic mode signal. Since the control circuit for updating the contents of the priority storage means according to the signal is provided, the way can be selected directly from the outside, and the contents of the priority storage means can be updated according to the selection result. This has the effect that the algorithm for creating a test pattern for diagnosing the storage means is also greatly simplified. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a set associative cache memory according to claim (1), and FIG. 2 is a block diagram showing an embodiment of a set associative cache memory according to claim (2). FIG. 3 is a block diagram of a conventional 4-way set associative cache memory. In the figure, 1 is an address, 2 is an address tag, 3 is a set select, 4 is a word select, 5 is an address tag memory, 6 is a valid bit memory, 7 is a data block memory, 8 is an LRU bit memory, and 9 is an address tag. Comparators, 10 and 11 are first and second selectors, 12 is a diagnostic mode signal, 13 is a way selection signal, 14 is a decode circuit, 15 is a selector circuit, 16 and 17 are way hit signals, and 18 is a control circuit. is there. The same reference numerals in each drawing indicate the same or corresponding parts.

Claims (2)

[Claims] 1. A data block memory which holds an address consisting of an address tag, a set select and a word select, and stores data in a cache memory, and the address tag is stored in association with the contents of the data block memory. An address tag memory, a valid bit memory indicating whether the memory in the data block is valid or invalid, a priority storage unit for storing the replacement priority of the data of each way, the address tag and the address An address tag comparator for comparing the data in the tag memory, a first selector for selecting the word data by the word select, and a word data from the first selector for selecting the output of the address tag comparator. Set associative with output second selector In a cache memory, a decoding circuit for receiving a way selection signal from the outside for designating a specific way and generating a way hit signal, and a way hit signal from the decoding circuit for receiving a diagnostic mode signal and the priority storing means And a third selector that selects and outputs one of the way hit signals from the set associative type cache memory. 2. A data block memory for holding data in a cache memory, and an address tag corresponding to the contents of the data block memory. An address tag memory, a valid bit memory indicating whether the memory in the data block is valid or invalid, a priority storage unit for storing the replacement priority of the data of each way, the address tag and the address An address tag comparator for comparing the data in the tag memory, a first selector for selecting the word data by the word select, and a word data from the first selector for selecting the output of the address tag comparator. Set associative with output second selector In a cache memory, a decoding circuit for receiving a way selection signal from the outside for designating a specific way and generating a way hit signal, and a way hit signal from the decoding circuit for receiving a diagnostic mode signal and the priority storing means A third selector that selects and outputs one of the way hit signals from the decoder circuit and the priority storage means according to the way hit signal when the way hit signal from the decoding circuit is selected by the diagnostic mode signal. And a control circuit for updating the contents of the set associative cache memory.