JP3597117B2 - Alarm temporary hold circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technology for collecting alarm information generated in a transmission device or the like, and in particular, is provided between an alarm detection unit and a processing unit that processes collected alarms, and a phase difference between alarm detection and collection timing. And a temporary alarm storage circuit for temporarily storing alarm information.
[0002]
[Prior art]
Conventionally, in this type of system, an alarm detection unit for detecting an alarm generated in a transmission device or the like, an alarm temporary holding circuit for temporarily temporarily holding the detected alarm information, and a recovery for the collected alarm And an alarm processing unit that performs an operation. The alarm temporary holding circuit temporarily holds the alarm information and, after sending the alarm information in response to the read request from the alarm processing unit, clears the alarm information because the alarm information is unnecessary. Is generally adopted.
[0003]
FIG. 4 shows the alarm temporary holding circuit, and is an example of a circuit configuration in a case where alarm information detected by an alarm detection unit is multiplexed.
[0004]
The address information S1 paired with the multiplexed alarm information S3 from the alarm detection unit is input to the temporary holding circuit, and D flip-flops 12-0 to i (hereinafter, referred to as DFF) corresponding to the address S1 are input. ), The alarm information is temporarily stored. When the readout of the alarm information is performed, when there is a read signal S4 from the alarm processing unit, the corresponding DFF output is selected by the selection circuit 11 according to the address information S2 from the alarm processing unit, and is output to the alarm processing unit. The temporary holding function is realized by clearing the information of the corresponding DFF 12 at the end edge of the read signal S4.
[0005]
Next, the circuit operation shown in FIG. 4 will be described with reference to FIG. First, the temporary holding operation of the alarm will be described. When the value “A” is input as the alarm information S3 when the temporary holding address S1 is “1”, “A” is temporarily held in the FF 12-1 corresponding to the address information S1, and read out from the alarm processing unit. Retained until requested. However, at this time, if the value “B” has already been temporarily stored in the FF 12-1, the “A” of the alarm information S3 and the “B” already stored in the FF 12-1 are stored in the FF 12-1. The logical sum is temporarily stored. This is because the input timing of the alarm information to the alarm temporary holding circuit and the reading operation of the alarm processing unit are performed asynchronously, so that the alarm holding information for which the reading of the alarm is not completed cannot be cleared, and the following alarm and the subsequent alarm cannot be cleared. This is because it is necessary to perform an alarm process on the alarm information obtained by the logical sum.
[0006]
Next, a read operation from the alarm processing unit will be described. When "2" is input as the alarm read address S2 from the alarm processing unit, the value "C" of the FF 12-2 corresponding to the read address is selected and output as the alarm read signal S4, and the end point of the read signal S4 ( In this circuit example, the temporary holding information is cleared by setting the temporary holding information of the FF 12-2 to "0" at the point of change from the high level to the low level).
[0007]
In addition to the above circuit configuration, Japanese Patent Application Laid-Open No. 2-233035 is known. This alarm temporary holding circuit prepares two memories each having a capacity corresponding to the alarm information, and includes a memory for performing write control from the alarm detection unit, and a memory for performing read control from the alarm processing unit and temporary storage clear control. The temporary holding function is realized by switching with a control signal from the alarm processing unit.
[0008]
Here, comparing the holding circuit of FIG. 4 with the holding circuit described in the gazette, the technology described in the gazette uses two memory circuits for the temporary holding, so that the alarm information temporarily held It can be said that the advantage of the circuit configuration is greater than that of the holding circuit in FIG.
[0009]
[Problems to be solved by the invention]
However, the holding circuit disclosed in Japanese Patent Application Laid-Open No. 2-233035 is suitable for relatively high integration because it holds alarm information in a memory, but requires two memories for the amount of alarm information. It can be said that there is still enough room for improvement in integration.
[0010]
Therefore, an object of the present invention is to provide a novel alarm temporary holding circuit for solving the problems inherent in the above-mentioned existing technology, and a small-scale configuration suitable for high integration even in a system having a large number of alarm information. Is provided.
[0011]
[Means for Solving the Problems]
According to the present invention, the alarm information temporarily received from the alarm detection unit is temporarily stored, the alarm information specified by the alarm processing unit read address is transferred from the alarm processing unit, and the alarm information after the transfer is cleared. In the temporary holding circuit, a memory circuit that reads data by inputting an input address and a read enable signal and writes data by inputting an input address and a write enable signal, and outputs a clock obtained by multiplying the temporary holding address by four. A timing signal generating circuit that generates four timing signals by dividing the frequency and sequentially outputs these as first to fourth timing signals, and when the timing signals indicate first and second timing signals, An alarm processing unit when the tentative holding address is used as an address input of the memory circuit and the third and fourth timing signals are indicated; A selection circuit for selecting and outputting an output address as an address input of the memory circuit, and when the timing signal generation circuit outputs a first timing signal to the memory circuit and alarm information is received. A first read enable signal, a second write enable signal is subsequently output when a second timing signal is generated, and a third read signal is output when the timing signal generation circuit outputs a third timing signal. And outputting a second read enable signal when a read signal of alarm information is received from the alarm processing unit, and subsequently outputting a second write enable signal when generating a fourth timing signal. A timing adjustment circuit, and an alarm received from an alarm detection unit when the first write enable signal is generated for the memory circuit. And the alarm information read by the output of the first read enable signal, and outputs alarm information obtained by ORing the alarm information. When the second write enable signal is generated, data indicating no alarm information is output. And a data output circuit for outputting the data.
[0012]
Further, the first to fourth timing signals may be generated in the third, fourth, first, and second order. In the configuration of the timing signal generation circuit, for example, the clock is input. It can be configured by a quaternary counter and a decoder that outputs the four types of timing signals by decoding the count value of the quaternary counter.
[0013]
Further, a wait signal indicating that the reading of the alarm information is not completed is received between the time when the read request from the alarm processing unit is received and the time when no alarm information is stored in the read address specified by the request. With the provision of the wait signal generation circuit for outputting to the processing unit, even if the alarm processing speed in the alarm processing unit is faster than the reading operation, the read signal can be collected accurately.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an alarm temporary holding circuit according to an embodiment of the present invention will be described with reference to the drawings.
[0015]
In the temporary alarm holding circuit shown in FIG. 1, the temporary holding address transmitted from the alarm detecting circuit (not shown), the alarm information in phase with the temporary holding address, the read address and the read signal transmitted from the alarm processing unit (not shown) are stored. On the basis of the above, history reading of alarm information (hereinafter referred to as phase 0) / writing of alarm information (hereinafter referred to as phase 1) / reading of alarm information (hereinafter referred to as phase 2) / clearing of alarm information (hereinafter referred to as phase 2). By executing a process consisting of four phases (called phase 3), temporary storage and reading of alarm information are performed.
[0016]
In order to execute these four phases, the illustrated alarm temporary holding circuit includes a memory circuit 2 that stores alarm information to temporarily temporarily hold alarm information received from the alarm detection unit, and a memory circuit 2 that sequentially stores the alarm information. A timing signal generation circuit 1 for generating a timing signal serving as a reference for a phase operation, a write / read control circuit 3 for controlling writing and reading to and from the memory based on the timing signal, and a readout from the memory circuit 2 D flip-flops 4 and 5 (hereinafter, referred to as D-FF) for temporarily holding alarm information. The timing signal generation circuit 1 generates a timing signal corresponding to each phase by synchronizing with the phase of the temporary holding address input via S1 and dividing one symbol of the temporary holding address by four.
[0017]
The write / read control circuit 3 outputs a selection circuit 32 for selecting a temporary holding address and an alarm processing unit read address according to the phase, and a read enable signal and a write enable signal required in each phase. A timing adjustment circuit 31, an OR circuit 33 for ORing the alarm information received from the alarm detection unit and the alarm information read from the memory, an output of the ORed alarm information, and an output of the alarm information read from the memory And an output control circuit 34 for controlling the
[0018]
Next, regarding the four phases in the above-described temporary alarm holding circuit, the operation of the phase 0 will be described first. Phase 0 is an operation of reading out the memory storage information indicated by the temporary holding address received in the same phase when the alarm information is received from the alarm detection unit. In the relationship between the reception of the alarm information and the operation of reading the alarm information, since each operation is performed asynchronously, it is necessary to store the history of the alarm information. That is, in the state where the uncollected alarm information is stored in the memory circuit 2, if the storage address matches the temporary holding address of the received alarm information, it is necessary to reflect the currently received alarm information to the past alarm information. And the reading in phase 0 is for that purpose.
[0019]
In the phase 0, the operation starts when the timing adjustment circuit 31 detects the alarm information in the write / read control circuit 3, and the selection circuit 32 receives the timing of the phase 0 output from the timing signal generation circuit 1 and temporarily holds the timing. The address is selected and output, and a read enable signal is output from the timing adjustment circuit to the memory circuit 2, whereby the alarm information indicated by the temporary holding address is read. The read alarm information is latched by the D-FF 4 to complete the operation.
[0020]
Next, phase 1 will be described. The OR circuit performs an OR operation on the past alarm information output from the D-FF 4 and the alarm information received via the input S3, and outputs the result to the output control circuit. On the other hand, the timing adjustment circuit 31 outputs the write enable signal to the memory circuit 2 and the output control circuit 34 at the timing of the phase 1 output from the timing signal generation circuit 1, and the writing of the alarm information is completed.
[0021]
Phase 2 is an operation performed when a request for reading alarm information is issued from the alarm processing unit. Upon receiving a read request from the alarm processing unit, the timing adjustment circuit 31 outputs a read enable signal to the memory circuit 2 at the timing of phase 2 output by the timing signal generation circuit 1. The phase 2 timing signal switches the output of the selection circuit 32 from the temporary holding address to the alarm processing unit read address, and the memory circuit 2 outputs alarm information that has received a read request. The read alarm information is output to the output control circuit 34 and output to the alarm processing unit via the D-FFs 5 and S6.
[0022]
Phase 3 is an operation of clearing the address position after the reading of the alarm information is completed in response to the reading request from the alarm processing unit. Therefore, phase 3 is an operation performed in conjunction with the operation of phase 2. The timing adjustment circuit 31 outputs the write enable signal to the memory circuit 2 at the input of the alarm processing unit read signal and at the timing of phase 3 output by the timing signal generation unit 1. Then, the clear operation is completed by storing “0” output from the output control circuit 34 in the alarm processing unit read address in the memory circuit 2.
[0023]
Next, an embodiment of the alarm temporary holding circuit is shown in FIG. In the present embodiment, a temporary holding address consisting of m-bit parallel data and alarm information are given as input from the alarm detection unit via the input terminals of S1 and S3, and an m-bit parallel address is input as an input from the alarm processing unit. An alarm processing unit read address and an alarm processing unit read signal composed of data are provided through input terminals S2 and S4, and the temporarily held alarm information is output to the alarm processing unit through an output terminal S6. It is assumed that the temporary holding address input from S1 is always input regardless of the presence or absence of alarm information.
[0024]
The timing signal generation circuit 1 is constituted by a divide-by-4 counter circuit, outputs a count value of 0 to 3 to a decoder based on a clock input, and outputs a timing signal. Each of the decoded outputs corresponds to phases 0 to 3.
[0025]
The write / read control circuit 3 includes a plurality of gate circuits as shown. First, the configuration of the timing adjustment circuit 31 will be described. The logical sum 311 detects the input of the alarm information by logically ORing the parallel data of the alarm information input via S3. The NOR 312 receives the output of the logical sum 311 and the decode value output from the first port of the timing signal generation circuit 1 and outputs an address selection signal to the selection circuit 32. The AND 313 receives the output of the OR 311 and the decode value output from the 0th port of the timing signal generation circuit 1 as inputs, and outputs a logical product of them. The output of the AND 313 is output to the subsequent D-FF 315 and OR 317. The AND 314 receives the read signal of the alarm processing unit and the decode value output from the second port of the timing adjustment circuit 31, outputs the signal to the enable terminal of the D-FF 5, and outputs the result to the logical sum 317 with the D-FF 316. The D-FF 315 generates a signal obtained by delaying the output of the AND 313 by one clock, and generates a write enable signal in phase 1 via the OR 318 and the AND 319. The D-FF 316 generates a signal obtained by delaying the output of the AND 314 by one clock, and generates a write enable signal in phase 3 via the OR 318 and the AND 319. The OR 317 generates a read enable signal in phase 0 and phase 2.
[0026]
The selection circuit 32 is constituted by a selector, and selectively outputs one of the temporary holding address and the alarm processing unit read address using the output of the NOR 312 as a selection signal. The logical sum 33 can be constituted by, for example, an OR gate. The output control circuit 34 can be composed of an AND 341 for controlling the output of the OR 33 to the memory circuit 2 and a buffer with a control terminal.
[0027]
Next, the circuit operation of this embodiment will be described with reference to a time chart shown in FIG. In this time chart, when the temporary holding address S1 is “WA3”, the value “A” is input as the alarm information S3, and the alarm information “A” is received in the alarm information S3 overlapping this input period. It shows the operation in the case.
[0028]
First, the operation of the phase 0 for reading the history of the alarm information from the detection of the alarm information will be described. The alarm information "A" input via the input terminal S3 is input to the write / read control circuit 31 and the logical sum 33, and the write / read control circuit 31 converts the alarm information "A" by the logical sum 311. The reception of the alarm information “A” is detected by the logical sum.
[0029]
The read enable signal S14 necessary for reading the temporary holding address “WA3” is generated by the following route. In phase 0, the timing signal generation circuit 1 outputs a timing signal synchronized with the temporary holding address input as needed from the 0th port of the decoder. The logical product 313 receives the output of the logical sum 311 and the high level signal from the port 0, outputs a high active signal, and outputs the read enable signal S14 via the logical sum 317.
[0030]
On the other hand, the selection circuit 32 for selecting an address selects the temporary holding address as the read address of the memory circuit 2 by outputting the NOR 312 which receives the detection signal of the alarm information “A” as an input. Assuming that the memory area value corresponding to the value “WA3” of the temporary holding address S1 is “B”, “B” is read as the information S13 and “B” is held as the holding value S18 of the D-FF4. .
[0031]
When the operation of phase 0 is completed, the operation automatically shifts to the operation of phase 1. That is, the high-level output of the logical sum 313 shown above is input to the D-FF 315, generates a signal delayed by one clock with respect to the read enable signal, and generates the logical sum 318 and the logical product 319. Then, the write enable signal S15 is output via the CPU. The output of the D-FF 315 is output to the AND 341 of the output control circuit 34, and the logical sum 33 output of the alarm information S18 “B” and the alarm information “A” read in phase 0 is indicated by the temporary holding address “WA3”. Is written in the area.
[0032]
Next, the operation of phase 2 will be described. The timing signal generating circuit 1 outputs a high-level timing signal from the second port of the decoder. The logical product 314 calculates a logical product of the read signal from the alarm processing unit, and outputs the read enable signal S14 via the logical sum 317. At the same time, the enable S11 necessary for holding the alarm information of the D-FF 5 is output. At this time, the selection circuit 32 selects the read address of the alarm information processing unit, and if the memory area value corresponding to the value “RA” of the read address S2 is “C”, “C” is held in the D-FF5. Then, "C" is output as the alarm processing unit read signal S6.
[0033]
Next, phase 3 will be described. The high-level output of the logical product 314 described above is input to the D-FF 316, generates a signal delayed by one clock with respect to the read enable signal, and performs write enable via the logical sum 318 and the logical product 319. The signal S15 is output. At this time, in the output control circuit 34, the parallel data of all “0” is output from the logical product 341. Therefore, the area of the alarm processing unit read address “RA” output by the selection circuit 32 is cleared. .
[0034]
The above-described operation is an example in which the temporary storage of the alarm information and the reading from the alarm processing unit are performed at the same time. However, when these are input at different timings, the continuous operation of the phase 0 and the phase 1 is performed. An operation, a continuous operation of phase 2 and phase 3, respectively, will occur.
[0035]
Next, a second embodiment of the present invention will be described with reference to the drawings. The present embodiment is intended to apply weight control to the alarm processing unit when the operation of the alarm processing unit is faster than one cycle from phases 0 to 3 in the first embodiment described above. is there.
[0036]
Supplementing the relationship between the alarm processing unit and the alarm detection unit using a general-purpose CPU, these are usually operated by an asynchronous clock signal in many cases, and the operation of the temporary holding circuit according to the present invention is It is operated by the clock S5 on the unit side. When the processing speed is required in the alarm processing unit such as the CPU and the operation speed is higher than the speed of the alarm information, the read signal S4 becomes inactive before the value “C” of the alarm read data S6 is read from the circuit. It may change. In such a case, the alarm processing unit such as the CPU accurately reads the value of the read signal S6 in order to capture the read data S6 at the end of the alarm read signal S4 (in the present embodiment, at the transition point from the high level to the low level). Cannot read.
[0037]
In order to avoid such a case, in the case of a general-purpose CPU, the read cycle can be extended by WAIT control. As an operation of the CPU or the like, when the WAIT signal S7 is active (high level in the present embodiment), the read cycle is extended, and after changing to inactive, the read signal S4 is inactive (low level in the present embodiment). To read the exact value. The WAIT signal S7 is output to an alarm processing unit such as a CPU for performing this control.
[0038]
Note that the operation of FIG. 3 and the operation of FIG. 1 are the same except for the WAIT signal S7, and thus the timing of the WAIT signal is shown together in the timing chart of FIG.
Therefore, the alarm temporary holding circuit shown in FIG. 3 is different in that a weight signal generating circuit 6 is provided in the circuit of FIG. The wait signal generation circuit 6 outputs the wait signal S7 after the read control signal from the alarm processing unit becomes active, and releases the wait signal S7 when the memory contents are cleared.
[0039]
As described above, in the above-described two embodiments, an example has been described in which a clock obtained by multiplying the tentative holding address by 4 is divided by 4 to generate 4 phases. Needless to say, the timing signal may be generated in the order of the first phase, the fourth phase, the first phase, and the second phase.
[0040]
【The invention's effect】
As described above, according to the present invention, the timing of the temporary holding and reading is managed by the timing signal which is synchronized with the temporary holding address value output from the alarm detection unit and is divided by four, so that the temporary holding circuit And a circuit suitable for high integration can be provided.
[Brief description of the drawings]
FIG. 1 is a block diagram of a temporary alarm holding circuit according to a first embodiment of the present invention;
FIG. 2 is a circuit configuration diagram of a temporary alarm holding circuit according to an embodiment of the present invention;
FIG. 3 is a time chart showing the operation of the temporary alarm holding circuit shown in the embodiment.
FIG. 4 is a block diagram of a temporary alarm holding circuit according to a second embodiment of the present invention;
FIG. 5 is a block diagram of a conventional temporary holding circuit.
FIG. 6 is a timing chart illustrating an operation of a conventional temporary holding circuit.
[Explanation of symbols]
1 timing signal generation circuit 2 memory circuit (RAM)
3 read / write control circuit 31 timing adjustment circuit 31A 4 clock width circuit 311 logical sum 312 NOR
313 logical product 314 logical product 315 D flip-flop 316 D flip-flop 317 logical sum 318 logical sum 319 logical product 32 selection circuit 33 logical sum 34 output control circuit 341 logical product 4 D flip-flop 5 D flip-flop 6 weight signal generation circuit S1 Address signal S2 corresponding to the alarm information Address signal S3 input from the alarm processing unit S3 Multiplexed alarm signal S4 Alarm processing unit read signal S5 Quadrupled clock S6 synchronized with the multiplexed alarm signal S6 Alarm processing unit read data S7 Weight signal S8 History Read timing signal S9 Warning read timing signal S10 History hold signal S11 Read hold signal S12 Memory address signal S13 Memory data signal S14 Memory read signal S15 Memory write signal S16 4 clock width S17 of alarm processing unit read signal S17 4 minutes Week counter value S18 History read information

Claims (4)

In an alarm temporary holding circuit for temporarily holding the alarm information received from the alarm detection unit, transferring the alarm information specified by the alarm processing unit read address from the alarm processing unit, and clearing the transferred alarm information,
A memory circuit for reading data by inputting an input address and a read enable signal, and writing data by inputting an input address and a write enable signal;
A timing signal generation circuit that generates four timing signals by dividing a clock obtained by multiplying the tentative holding address by four, and sequentially outputs these as first to fourth timing signals;
When the timing signal indicates the first and second timing signals, the tentative holding address is used as the address input of the memory circuit, and when the timing signal indicates the third and fourth timing signals, the alarm processor read address is used as the address of the memory circuit. A selection circuit for selecting and outputting as an address input;
A first read enable signal is output to the memory circuit when the timing signal generation circuit outputs a first timing signal and alarm information is received, and then a second read enable signal is output to the memory circuit. The first write enable signal is output when the timing signal is generated, and the readout signal of the alarm information is received from the alarm processing unit when the timing signal generation circuit outputs the third timing signal. A timing adjustment circuit that outputs a second read enable signal in such a case, and subsequently outputs a second write enable signal when a fourth timing signal is generated;
The memory circuit is obtained by logically ORing the alarm information received from the alarm detection unit when the first write enable signal is generated and the alarm information read by the output of the first read enable signal. And a data output circuit for outputting data indicating that there is no alarm information when the second write enable signal is generated. In an alarm temporary holding circuit for temporarily holding the alarm information received from the alarm detection unit, transferring the alarm information specified by the alarm processing unit read address from the alarm processing unit, and clearing the transferred alarm information,
A memory circuit that reads data according to an input address and a read enable signal and writes data according to the input address and a write enable signal;
A timing signal generation circuit that generates four timing signals by dividing a clock obtained by multiplying the tentative holding address by four, and sequentially outputs these as first to fourth timing signals;
When the timing signal indicates the first and second timing signals, the alarm processor read address is used as the address input of the memory circuit. When the timing signal indicates the third and fourth timing signals, the temporary holding address is used for the memory circuit. A selection circuit for selecting and outputting as an address input;
Outputting a first read enable signal to the memory circuit when the timing signal generation circuit outputs a first timing signal and when a read signal of alarm information is received from the alarm processing unit; Subsequently, when the second timing signal is generated, the first write enable signal is output, and when the timing signal generation circuit outputs the third timing signal, the alarm information is received. A timing adjustment circuit that outputs a second read enable signal in such a case, and subsequently outputs a second write enable signal when a fourth timing signal is generated;
When the first write enable signal is generated, data indicating no alarm information is output to the memory circuit, and when the second write enable signal is generated, the alarm information received from the alarm detector and the second write enable signal are output to the memory circuit. A data output circuit for outputting alarm information obtained by logically ORing the alarm information read by the output of the read enable signal. 2. The timing signal generating circuit according to claim 1, wherein the timing signal generating circuit includes a quaternary counter that receives the clock and a decode that outputs the four types of timing signals by decoding a count value of the quaternary counter. 3. The alarm temporary holding circuit according to claim 1. A wait signal indicating that the reading of the alarm information has not been completed is received between the time when the read request from the alarm processing unit is received and the time when no alarm information is stored in the read address specified by the request, and the alarm processing unit. 4. The temporary alarm hold circuit according to claim 1, further comprising a wait signal generation circuit for outputting the alarm signal to the alarm hold circuit.

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