JP3597886B2 - Semiconductor device - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a semiconductor device technology, and more particularly to a technology that is effective when applied to a semiconductor integrated circuit device in which a distance between metal wirings is small.
[0002]
[Prior art]
For example, FIG. 7 shows a state of a conventional metal wiring. The semiconductor substrate 21 is made of single-crystal silicon, the surface of which is provided with an insulating layer 22 of silicon oxide, and the lower metal wiring 20 is pattern-formed on the surface thereof. A semiconductor integrated circuit having silicon oxide films 28 and 31 functioning as an interlayer insulating film between the lower metal wiring and the upper metal wiring 29 and an SOG film 30 contributing to planarization of the insulating film is known as a prior art. Conceivable. For example, a publication related to multilayer wiring is disclosed in JP-A-5-218028.
[0003]
[Problems to be solved by the invention]
In many of such multilayer wiring structures, the relative permittivity of the silicon oxide film 28 is about 4, and therefore, in recent semiconductor devices in which the distance between the lower metal wirings 20 is 1 micron or less due to high integration, the distance between the wirings is reduced. Due to the increase in capacity, the electrical characteristics of the semiconductor integrated circuit device have been adversely affected, such as delaying the propagation speed of electric signals.
[0004]
Therefore, in the above-mentioned conventional technology, when determining the thickness and material of the interlayer insulating film, alpha rays and flatness are taken into consideration, but measures for reducing the wiring capacitance between adjacent metal wirings are taken into consideration. Inadequate measures were not taken.
[0005]
That is, the wiring capacitance is represented by the dielectric constant between adjacent wirings × (the area opposed to adjacent wirings 配線 the distance between adjacent wirings), and the entire opposing surface of the adjacent wirings is filled with an ordinary insulating material having a relative dielectric constant of 4, The wiring capacity is increased in order to reduce the distance.
[0006]
Further, in order to avoid a delay in the propagation speed of an electric signal, the allowable interval between predetermined wirings, the allowable range of the threshold voltage of a MOS transistor, and the like become narrow, so that the manufacturing process of a semiconductor integrated circuit has a certain limit. .
[0007]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a technique capable of effectively reducing a wiring capacitance between wirings made of a metal or a polycrystalline silicon strip.
[0008]
Another object of the present invention is to provide a technique capable of improving the operation speed of a semiconductor integrated circuit device.
[0009]
Another object of the present invention is to provide a technique capable of relaxing the restrictions on the manufacturing process of a semiconductor integrated circuit device.
[0010]
The novel structure and effect of the present invention will become apparent from the description of the specification and the accompanying drawings.
[0011]
[Means for Solving the Problems]
In the semiconductor device of the present invention, by forming an insulating film having a small relative dielectric constant between metal wires to be reduced, the capacitance between the metal wires is reduced and the characteristics of the circuit are improved. . Specifically, in a wiring step of a semiconductor device, fine metal wirings are formed, and a low dielectric constant insulator material containing an organic substance such as a polymer is formed between the metal wirings by a spin coating method or the like. The dielectric constant of this insulator material has been developed to about one half that of a silicon oxide film, and the capacitance between wirings can be significantly reduced.
[0012]
However, in a low-dielectric-constant insulator material containing an organic substance such as a polymer, when forming this film, the polymer molecules are formed so as to be perpendicular to the substrate surface, and the dielectric constant in a direction perpendicular to the substrate is reduced. It tends to be higher than the dielectric constant in the horizontal direction. Therefore, when an insulating film containing these organic substances is used as the interlayer insulating film of the semiconductor wiring, the capacitance between the horizontal wirings can be significantly reduced, but the effect of the reduction in the vertical wiring capacitance is not so large. It was not remarkable.
[0013]
[Action]
According to the present invention, the capacitance between the wirings can be minimized by controlling the direction of the polymer molecule. As a low dielectric constant insulator material containing an organic substance such as a polymer, it is more effective to include spin-on glass (SOG), polyimide, Teflon (registered trademark), or the like having a lower relative dielectric constant than silicon oxide as a constituent element. It is a target.
[0014]
As a result, the time when the electric signal charges or discharges the metal wiring can be shortened as compared with the related art, so that the propagation speed of the electric signal can be increased.
[0015]
【Example】
1 to 5 are sectional views in the order of manufacturing steps of a semiconductor device according to a first embodiment of the present invention. FIG. 1 is a cross section in which a metal wiring 3 is formed on a Si substrate 1 covered with an insulating film (SiO ₂ ) 2. FIG. 2 shows that a CVD-SiO ₂ film 4 is formed so as to cover the metal wiring 3, and a spin-on glass (SOG) precursor containing an organic polymer is used at a rotation speed of 1000 to 5000 rpm using a spinner. Coat. Thereafter, in order to evaporate the solvent, the section was baked at 100 to 200 ° C. (depending on the boiling point of the solvent), and was finally cured at 350 to 450 ° C. Usually, at this time, many organic polymer molecules are aligned in a direction perpendicular to the substrate surface. In this state, the relative permittivity of the polymer molecules in the horizontal direction is effective between the upper and lower metal wirings, so that the capacitance between the wirings becomes relatively large. Therefore, in this embodiment, a portion that affects the capacitance between the upper and lower wirings is removed by a chemical mechanical polishing (abbreviated as CMP) method. FIG. 3 shows the structure after using the CMP method. Thereafter, when applying the second layer of SOG, an electric field is applied so that the polymer molecules are oriented in the horizontal direction before baking, and bake-cure is performed in a state where the polymer molecules are oriented in the horizontal direction. . As a result, the capacitance between the upper and lower wirings can be reduced. Thereafter, the second metal wiring 5 is formed, and the semiconductor device may be manufactured in a normal semiconductor manufacturing process.
[0016]
In the present embodiment, the technical problem that the capacitance between the upper and lower wirings is relatively large because the polymer molecules tend to be oriented perpendicular to the substrate affects the upper and lower wirings by using the CMP method. After the film is removed, a layer in which polymer molecules are oriented in the horizontal direction is newly formed, and the capacitance between the upper and lower wirings is reduced, thereby minimizing the wiring capacitance of the entire semiconductor device.
[0017]
In the above embodiment, the organic polymer is removed by using the CMP method. However, a portion which affects the capacitance between the upper and lower wirings can be removed by the etch-back method.
[0018]
FIG. 6 is a process sectional view of a semiconductor device according to a second embodiment of the present invention. That is, after applying the SOG of the second layer, the organic SOG is rolled by a roller in order to change the direction of the polymer molecules in the organic SOG, and then final cured at 350 to 450 ° C. in nitrogen gas. is there. Further, also in the present embodiment, an etch-back method can be employed instead of the CPM method for removing the polymer portion which affects the wiring capacitance.
[0019]
In the above embodiments, the concept of the present invention has been described using an example of a manufacturing process using an organic SOG having a small relative dielectric constant. However, similar effects can be obtained by using a polyimide, Teflon (“registered trademark”), or the like. Is also good. Further, if an electric field is intentionally applied before the organic film applied after the CVD SiO ₂ film 4 is baked and cured so that the polymer molecules are oriented in a direction perpendicular to the substrate, the polymer molecules between the wirings become more vertical. Orientation, and the capacitance between wirings can be further reduced.
[0020]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
In the present invention, when forming an isolation insulating film whose relative dielectric constant has orientation dependency between the fine wiring in which the capacitance is a problem, the isolation insulating film is formed so that the relative dielectric constant between the wirings becomes low. By the orientation, the capacitance between the wirings can be reduced three-dimensionally, and the electrical operation speed of the integrated circuit can be increased.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a wiring formed on a Si substrate according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view in which an organic polymer layer is formed on a wiring layer according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of an embodiment of the present invention in which an upper portion of an organic polymer layer is removed.
FIG. 4 is a cross-sectional view of a main part in which a second isolation insulating film according to an embodiment of the present invention is overcoated.
FIG. 5 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention.
FIG. 6 is a cross-sectional view of a main part in which a second isolation insulating film according to another embodiment of the present invention is applied repeatedly.
FIG. 7 is a cross-sectional view of a conventional multilayer wiring.
[Explanation of symbols]
1, 21 Si substrate 2 SiO ₂ film 3, 20 First metal wiring (lower metal wiring)
4 CVD-SiO ₂ film 5, 29 Second metal wiring (upper metal wiring)
6 Organic polymer molecular layer (first isolation insulating film)
7 Interlayer insulating film layer (second isolation insulating film)
28, 31 silicon oxide 30 SOG film

Claims (1)

A substrate,
A first metal wiring composed of a plurality of wirings, each of which is separately arranged on the substrate;
A first isolation insulating material, which is made of an insulating material containing an organic substance having an orientation characteristic, is disposed between each of the first metal wirings, and has a relative dielectric constant in a direction perpendicular to the substrate larger than that in a horizontal direction. A membrane,
An insulating material containing an organic substance having an orientation characteristic is disposed on the first metal wiring and the first isolation insulating film, and a relative dielectric constant in a direction perpendicular to the substrate is lower than a relative dielectric constant in a horizontal direction. A second isolation insulating film;
A second metal wiring disposed on the second isolation insulating film;
Semiconductor device including: