JP3601883B2 - Semiconductor device - Google Patents

Description

従って、（１）式より（ｘ，ｙ）＝（２，３）または（３，２）のときだけ、容量Ｃ_ＦＩＧ５が容量Ｃ_ＦＩＧ２より大きくなる。言い替えると、ｘ，ｙがそれぞれ３以上になれば、データ転送回路３２の負荷容量Ｃ_ＦＩＧ５の方が小さくなる。しかも、ｘ，ｙが大きくなればなるほどＫの値は大きくなるため、データ転送回路３２の負荷容量はデータ転送回路３０に比べて小さくなることが分かる。
【００５６】
また、本実施例のデータ転送回路３２では、図２のデータ転送回路３０においてｑ本のデータ線を１ブロックとする構成を、ｘ本からなるｙ個の小ブロックに分けた構成とするので、データ転送回路３０では制御回路８０からのスイッチを制御する信号線の数がｘ×ｙ（＝ｑ）本であるのに対して、データ転送回路３２では制御回路８２からの信号線はｙ＋２ｘ本である。このため、本実施例のデータ転送回路３２の構成を用いることにより、データ線の数が増加した場合に信号線の数の増加を抑えることができるのでチップ面積の縮小に役立つほか、１本のライトパス、リードパスに接続できるデータ線数の選択の幅が広がるので設計の自由度が向上する。なお、各スイッチＳ_１１〜Ｓ_ｘｙ，Ｓ_１１〜Ｓ_ｐｑをそれぞれＭＯＳトランジスタ２個で構成した場合には、各ゲートに信号線が入力される必要があるので、上述した制御回路８０，８２からの各信号線ＳＳ１〜ＳＳｙ，ＳＳ１〜ＳＳｑの数は２倍の数となる。
【００５７】
前記実施例１と同様に本実施例の半導体装置も、通常のメモリとして用いることも可能であり、普段は画像処理専用として用い、必要が生じたときには通常のメモリとしてシステムの主記憶に用いる等といった時分割で用途を変える使い方も可能である。また、メモリセルアレイの領域を通常のメモリとして用いる部分と演算回路で専用に用いる部分と分けて使用することもできる等、実施例１と同様の効果を有することは言うまでもない。
【００５８】
また、図５に示したデータ転送回路３２で使用する各スイッチＳ_１１〜Ｓ_ｘｙのＭＯＳトランジスタによる具体的な構成は、実施例１と同様に、図６〜図８に示したいずれかの構成を必要に応じて使用すれば良い。
【００５９】
以上、本発明の好適な実施例について説明したが、本発明は前記実施例に限定されることなく、本発明の精神を逸脱しない範囲内において種々の設計変更をなし得ることは勿論である。
【００６０】
【発明の効果】
前述した実施例から明らかなように、本発明の半導体装置によれば、メモリセルアレイと演算回路との間に設けたデータ転送回路に、メモリセルからのデータ読み出し、メモリへセルへの書き込みのパスをそれぞれ独立して設けて、読み出し／書き込み動作を同時に行なえるように構成したことにより、データ処理にかかる時間ｍ×（ｔｒ＋ｔｃ＋ｔｗ）を、（ｍ×ｔｒ＋ｔｃ＋ｔｗ）、又は（ｔｒ＋ｍ×ｔｃ＋ｔｗ）、又は（ｔｒ＋ｔｃ＋ｍ×ｔｗ）等に短縮でき、大幅な高速化が可能となると共に一旦立ち上げたワード線上にあるメモリセル内のデータ処理を順次行うことによってワード線の立ち上げ回数を減らして消費電力の低減を図ることができる。
【図面の簡単な説明】
【図１】本発明に係る半導体装置の一実施例を示す基本構成のブロック図である。
【図２】図１の半導体装置に使用するデータ転送回路の一例を示す詳細な回路構成図である。
【図３】本発明に係る半導体装置の動作および従来の動作を比較説明する図であり、図３Ａおよび図３Ｂは図１の半導体装置の動作例、図３Ｃは従来の動作例を示すタイミング図である。
【図４】本発明に係る半導体装置の別の実施例を示す基本構成のブロック図である。
【図５】図４の半導体装置に使用するデータ転送回路の一例を示す詳細な回路構成図である。
【図６】本発明に係る半導体装置のデータ転送回路で使用するスイッチＳ_１１の具体的構成例の一例を示す回路構成図である。
【図７】本発明に係る半導体装置のデータ転送回路で使用するスイッチＳ_１１の具体的構成例の別の例を示す回路構成図である。
【図８】本発明に係る半導体装置のデータ転送回路で使用するスイッチＳ_１１の具体的構成例のまた別の例を示す回路構成図である。
【符号の説明】
１０…メモリセルアレイ、
２０…センスアンプ、
３０…データ転送回路、
３２…データ転送回路、
４０…演算回路、
５０…シリアルアクセスメモリ、
５１…Ｉ／Ｏポート、
６０…シリアルアクセスメモリ、
６１…Ｉ／Ｏポート、
７０…デコーダ、
７１…入力ポート、
８０…制御回路、
８１…Ｉ／Ｏポート、
８２…制御回路、
９０…シリコンチップ、
Ｃ_ｉｊ（ｉ＝１〜ｎ，ｊ＝０〜ｍ）…メモリセル、
ＤＬｊ，ＤＬｊ’（ｊ＝１〜ｍ）…データ線、
ＤＬ１Ｂ，ＤＬ１Ｔ…データ線、
ＷＬｉ（ｉ＝１〜ｎ）…ワード線、
Ｓ_ｊｋ（ｊ＝１〜ｐ，ｋ＝１〜ｑ）…スイッチ、
ＳＲ１〜ＳＲｘ…スイッチ、
ＳＷ１〜ＳＷｙ…スイッチ、
ＳＳｊ（ｊ＝１〜ｑ），ＳＳ１Ｒ，ＳＳ１Ｗ…信号線、
ＳＳＲ１〜ＳＳＲｙ…信号線、
ＳＳＷ１〜ＳＳＷｘ…信号線、
ＴｒＲ，ＴｒＲＢ，ＴｒＲＴ…トランジスタ、
ＴｒＷ，ＴｒＷＢ，ＴｒＷＴ…トランジスタ、
Ｒｊ（ｊ＝１〜ｐ），Ｒ１Ｂ，Ｒ１Ｔ…リードパス、
Ｗｊ（ｊ＝１〜ｐ），Ｗ１Ｂ，Ｗ１Ｔ…ライトパス。[0001]
[Industrial applications]
The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for data processing in which a highly integrated memory and a plurality of arithmetic circuits are implemented on one chip.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there has been known a semiconductor device in which a processor and a memory are mounted on one board for processing a large amount of data such as image processing, and are used as a dedicated processing system to perform high-speed processing. In this conventional example, since a memory and a processor are connected via a bus, bus arbitration is necessary, and when read / calculation / write is repeated for a large amount of data, as shown in FIG. Switching took a lot of time and did not increase the efficiency of data processing.
[0003]
Further, as a further advanced conventional example, a plurality of arithmetic circuits and a memory cell array are mounted on the same chip, and data of memory cells on one word line in the memory cell array are read in parallel, and the read data is read out. 2. Description of the Related Art There are known semiconductor devices that execute arithmetic processing of data in parallel. Examples of this type of semiconductor device include those described in, for example, "Aimoto et al.," Memory unit circuit method of memory integrated processor IMAP LSI ", Proceedings of the 1994 IEICE Spring Conference 5-261 C-693". There is.
[0004]
In the above-described conventional example, a 2 Mb SRAM and 64 parallel operation circuits are integrated, and the operation circuits are operated in parallel by a SIMD (Single Instruction Stream Multiple Data Stream) method. In such a semiconductor device, various image data processing can be performed by operating a plurality of arithmetic circuits mounted on the same chip as the memory cell array in parallel with one instruction and repeatedly executing the instructions. . When performing this image data processing, the calculation itself required for the data processing is not so difficult, but the amount of data to be processed is enormous, so the same calculation needs to be repeated many times.
[0005]
When processing image data using a conventional semiconductor device equipped with a plurality of arithmetic circuits and a memory cell array, first, data written in a memory cell is read out, and then the necessary data is read using a SIMD type arithmetic circuit. The operation is performed, and finally, the operation of writing the operation result to the memory cell is repeatedly performed. Here, the time required for reading is tr, the time required for calculation is tc, and the time required for writing is tw. In the above-described conventional semiconductor device, if a series of operations of reading, calculating, and writing are sequentially performed, the required time is (tr + tc + tw) in total, and the time required when this operation is repeated m times is m × (tr + tc + tw). It becomes.
In the future, with the progress of semiconductor manufacturing technology, miniaturization is advanced and high-speed operation of the arithmetic circuit can be expected. Therefore, if the arithmetic content is the same, the time tc required for the arithmetic can be reduced.
[0006]
[Problems to be solved by the invention]
However, according to a conventional semiconductor device in which a plurality of arithmetic circuits and a memory cell array described above are integrated on the same chip, even if the miniaturization progresses due to the development of semiconductor manufacturing technology, the memory cell array is different from the case of the arithmetic circuit. Conversely, as the size becomes smaller, it becomes more difficult to increase the amount of signals from the memory cells, so that the times tr and tw required for reading and writing cannot be reduced much. For this reason, in the case of image data processing in which an operation is added to data read from a memory cell and an operation of writing back to the same memory cell is repeated, the data processing operation is limited by the read time tr and the write time tw. There is a problem.
[0007]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device capable of shortening the data processing time when repeatedly performing the same operation as in image data processing and reducing power consumption.
[0008]
Further, another object of the present invention is that it can be used not only for image data processing but also as a main memory as a main memory, or can be used for versatile use in which an image data processing part and a normal memory part can be divided and used. To provide a simple semiconductor device.
[0009]
[Means for Solving the Problems]
In order to solve the above-described problem, a semiconductor device according to the present invention includes a memory cell array having a plurality of memory cells disposed at intersections of a plurality of data lines and a plurality of word lines, and a plurality of different memory cells in the memory cell array. A decoder for selecting at least one of the word lines to read information stored in the memory cell to a plurality of different data lines intersecting the word line; at least one arithmetic circuit; And a control circuit for controlling a data transfer circuit, a decoder, and an arithmetic circuit on a single chip, wherein the data transfer circuit is a word line selected by the decoder. Write to some data lines and read from some other data lines among multiple data lines that intersect As can be performed in at least a portion same in one hour, it is characterized in that it has been independently the read path and the write path.
[0010]
In the semiconductor device, the data transfer circuit selects a required number of data lines out of the plurality of data lines, and reads out each data read out on the data lines to an arithmetic circuit; Can independently have a function of selecting a required number of data lines from the plurality of data lines and writing the data from an arithmetic circuit to a memory cell via the data lines.
[0011]
Further, the function of reading each data read on the data line to the arithmetic circuit includes a switch controlled by a signal from the control circuit provided between the read path and each data line. The function of writing the operation result from the operation circuit to the memory cell via the data path can be constituted by a switch controlled by a signal from the control circuit provided between the write path and each data line.
[0012]
Further, the data transfer circuit includes a plurality of blocks formed by dividing a plurality of data lines into a required number, and one or one pair of read paths and one or one pair of write paths provided for each block. The connection to the read path, the connection to the write path, the connection to the write path, or the open state, which is provided between each data line in each block and the read path and write path of each block, is controlled by the control circuit. It is preferable to configure the switch with a switch.
[0013]
Still further, the data transfer circuit may be configured such that each of the blocks is divided into small blocks each having a smaller number of data lines, each data line in each small block, a read path side of each small block, and a write path. A switch controlled by the control circuit in one of a connection state to a read path connection line, a connection to a write path connection line, and an open state provided on the path side, and the read path connection line and the read path for each small block. And a switch that is turned on / off by the control circuit provided between the light path connection lines of each small block and a light path that is turned on / off by the control circuit provided between the light path connection line of each small block. May be.
[0014]
In addition, any of the semiconductor devices may be configured to have a function of directly accessing data stored in the memory cell array from outside.
[0015]
Further, the semiconductor device according to the present invention is provided at a word line, first and second data lines intersecting the word line, and at intersections of the word line and the first and second data lines. A first and a second memory cell, an arithmetic circuit, a read path connected to an input terminal of the arithmetic circuit, a write path connected to an output terminal of the arithmetic circuit, the first data line and the read path A first switch for connecting to the write path; and a second switch for connecting the second data line to the read or write path, wherein the word line is activated. While the first switch means connects the first data line to the read path, and the second switch means connects the second data line to the write path. Features A.
[0016]
[Action]
According to the semiconductor device of the present invention, between the memory cell array that holds data and the arithmetic circuit that receives data and performs an arithmetic operation, the data transfer circuit uses a read path that sends data of the memory cell to the arithmetic circuit and the arithmetic circuit. Providing separate write paths for sending data to the memory cells makes it possible to transfer the output of the memory cell array to the arithmetic circuit and simultaneously transfer the output of the arithmetic circuit to the memory cell array. In other words, since the read path and the write path are independent, different data lines can be selected between the memory cell array and the arithmetic circuit, and the read operation and the write operation can be partially overlapped and executed within the same time. . Therefore, in the case where data is read from the memory cell, the operation is performed, and the result is written back to the memory cell, the read path and the write path are separately provided, so that the data can be read and written at the same time. . Therefore, the processing time m × (tr + tc + tw) conventionally required when a series of processing is repeated m times can be apparently reduced to tr + m × tc + tw by performing reading and writing within the calculation time tc, for example. It becomes.
[0017]
Further, a switch controlled by a signal from the control circuit provided between the read path and each data line connects the read path and the data line, thereby selecting a selected one of the plurality of data lines. The data read out on the number of data lines can be read out to the arithmetic circuit, and a switch controlled by a signal from the control circuit provided between the write path and each data line is a switch which is connected to the plurality of data lines. The operation result can be written from the operation circuit to the memory cell through the required number of data lines selected among the lines.
[0018]
Further, the data transfer circuit includes a plurality of blocks formed by dividing a plurality of data lines into a required number, and one or one pair of read paths and one or one pair of write paths provided for each block. And a control circuit provided between each data line in each block and the read path and write path of each block to control the connection state to one of the connection to the read path, the connection to the write path, and the open state. By using a switch, a data line from one block can be connected to a read path and data can be read from a memory cell. At the same time, a data line in the same block is connected to a write path and the operation of the arithmetic circuit can be performed. The result can be written to the memory cell.
[0019]
Still further, the data transfer circuit may be configured such that each of the blocks is divided into small blocks each having a smaller number of data lines, each data line in each small block, a read path side of each small block, and a write path. A switch controlled by the control circuit in one of a connection state to a read path connection line, a connection to a write path connection line, and an open state provided on the path side, and the read path connection line and the read path for each small block. And a switch that is turned on / off by the control circuit provided between the light path connection lines of each small block and a light path that is turned on / off by the control circuit provided between the light path connection line of each small block. The read path and the write path are hierarchized, and the number of signal lines for controlling the switches is reduced. It can be.
[0020]
Further, by providing a function of directly accessing the data stored in the memory cell array from the outside, the semiconductor device according to the present invention can be used exclusively for image processing, and can be used as a normal memory if necessary, Of these, only one memory cell required for image processing is used exclusively for the arithmetic circuit, and the remaining part can be used for a general memory with a single chip.
[0021]
【Example】
Next, embodiments of a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings.
[0022]
<Example 1>
FIG. 1 is a block diagram of a basic circuit configuration showing one embodiment of a semiconductor device according to the present invention. In FIG. 1, reference numeral 10 denotes a memory cell array. The memory cell array 10 is arranged at each intersection of n word lines WLi (i = 1 to n) and m data lines DLj (j = 1 to m). Memory cell C in row i and column j _ij And each word line WLi is connected to an active memory cell C in the memory cell array 10. _ij Is connected to a decoder 70 for selecting An input port 71 is connected to the decoder 70 so that an address can be externally specified. Each data line DLj is connected via a I / O port 61 to a serial access memory 60 that transfers data to the outside, and a plurality of data lines DLj via a sense amplifier 20 that amplifies and holds a signal read from the memory cell array 10. And is connected to a plurality of data transfer circuits 30 corresponding to each block. Each data transfer circuit 30 is connected to the corresponding arithmetic circuit 40 and transfers data read from the memory cell array 10 to each arithmetic circuit 40. Each arithmetic circuit 40 is connected via an I / O port 51 to a serial access memory 50 for transferring data with the outside. Further, a control circuit 80 for controlling the whole is connected to the outside via an I / O port 81 and connected to each of the circuits 20, 30, 40, 50, 60, 70. The circuits, I / O ports, and the like are integrated on one silicon chip 90.
[0023]
The operation of the semiconductor device according to the present invention thus configured will be described below.
This semiconductor device uses the arithmetic circuit 40 to perform data processing on data input from outside the chip 90 via the I / O port 51 and the serial access memory 50 and data in the memory cell array 10. Can be. The control circuit 80 which has received a command and a clock from outside through the I / O port 81 controls the operations of the decoder 70, the sense amplifier 20, the data transfer circuit 30, the arithmetic circuit 40, the serial access memory 50, and the serial access memory 60 according to the clock. I do. The decoder 70 receiving the instruction from the control circuit 80 activates the word line WLi selected according to the input port 71 or the address specified by the control circuit 80, and activates the i-th memory cell column C in the memory cell array 10. _i1 , C _i2 , C _i3 , ... C _im Activate The contents of the activated memory cells are taken out through the respective data lines DL1 to DLm connected to the respective memory cells, amplified by the sense amplifier 20, and held. Each data transfer circuit 30 is connected to the i-th memory cell column C according to the signal lines SS1, SS2, SS3,... SSq selected by the control circuit 80. _i1 , C _i2 , C _i3 , ... C _im Is sent to the arithmetic circuit 40.
[0024]
Here, a detailed configuration of the data transfer circuit 30 is shown in FIG. Note that only one of the plurality of data transfer circuits 30 in FIG. 1 is shown. The data transfer circuit 30 is composed of p blocks as a whole, with one read path and one write path each, and q data lines as one block. Each block can be connected to a read path and a write path, respectively, from q data lines in the block.
[0025]
When one word line WLi is activated, the memory cell column C in the i-th row is activated. _i1 ~ C _im Is taken out by the data lines DL1 to DLm and amplified and held by the sense amplifier 20, data is transferred onto each of the data lines DL1 to DLm connected to each data transfer circuit 30 via the sense amplifier 20. appear. Since p × q data lines DL1 to DLpq are connected to the data transfer circuit 30 shown in FIG. 2, data appears on the data lines DL1 to DLpq.
[0026]
For example, according to the signal of the signal line SS1 output from the control circuit 80, each switch S in the first to p-th blocks ₁ 1, S ₂ 1, S ₃ 1, ... S _p 1 are connected to the read paths R1, R2, R3,. Thereby, the data on the data lines DL1, DLq + 1, DL2q + 1,... DL (p−1) q + 1 is transferred to the arithmetic circuit 40 through the read paths R1, R2, R3,. The arithmetic circuit 40 performs a required arithmetic operation using the data transmitted from the data transfer circuit 30 and the data input from outside the chip 90 to the serial access memory 50 via the I / O port 51. The result is output to each of the light paths W1, W2, W3,..., Wp.
[0027]
When the data of the operation result is to be written back to each memory cell from which the data has been read, when a predetermined operation time for the operation has elapsed, the control circuit 80 sends a signal to the signal line SS1 and Each switch S ₁ 1, S ₂ 1, S ₃ 1, ... S _p 1 are connected to the light paths W1, W2, W3,. As a result, the arithmetic circuit 40 transmits each memory cell C through the data transfer circuit 30. _i1 , C _{i (q + 1)} , C _{i (2q + 1)} , ... C _{i ((p-1) q + 1)} Write the calculation result to
[0028]
Each switch S ₁ 1, S ₂ 1, S ₃ 1, ... S _p Reference numeral 1 denotes a switch that takes one of a connection state of a read path side, a write path side, and an open state in response to a signal from the control circuit 80, and is normally in an open state. Also, instead of the control circuit 80 sending a signal to the signal lines SS1 to SSq when a predetermined arithmetic time has elapsed, the arithmetic circuit 40 may be configured to send a signal indicating that the arithmetic has been completed to the control circuit 80. Good. In this case, the control of the signal lines SS1 to SSq by the control circuit 80 is facilitated by the operation end signal, so that the design of the control circuit 80 can be simplified. In other words, even if the arithmetic circuit 40 is changed to perform a complicated operation, it is not necessary to estimate the time required for the complicated operation and redesign it in advance, and the control circuit 80 can be used without being changed. it can.
[0029]
Here, the case where data is written back to the memory cell from which data is read has been described, but it is easy to write data to another memory cell. In that case, a switch connected to a required data line may be selected by the signal lines SS1, SS2,..., SSq. Further, when writing the same data to a plurality of memory cells, a plurality of switches may be connected to one write path by a plurality of signal lines SS1, SS2,.
[0030]
As described above, according to the semiconductor device of the present embodiment, while the arithmetic circuit is writing to the memory cell via the write path, necessary data is read from another memory cell using the read path. be able to. For example, each data transfer circuit 30 transmits the memory cells C through the respective write paths W1, W2, W3,. _i1 , C _{i (q + 1)} , C _{i (2q + 1)} , ... C _{i ((p-1) q + 1)} The path through which data is written to the switch S1 is controlled by the signal on the signal line SS1 from the control circuit 80. ₁ 1, S ₂ 1, S ₃ 1, ... S _p 1 is connected to each light path side, and at the same time, each switch S ₁ 2, S ₂ 2, S ₃ 2, ... S _p 2 are connected to respective read paths, and data lines DL2, DLq + 2, DL2q + 2,... DL (p-1) q + 2 are connected to read paths R1, R2, R3,. Thereby, the memory cell C _i2 , C _{i (q + 2)} , C _{i (2q + 2)} , ... C _{i ((p-1) q + 2)} Can be transferred to the read operation circuit 40. If necessary, such a write and read operation is sequentially repeated, and the memory cell column C of the i-th row which is activated by the word line WLi selected by the decoder 70. _i1 , C _i2 , C _i3 , ... C _im May be processed. Further, all the data in the memory cell array 10 can be processed by raising another word line and performing the same processing on the memory cell columns in other rows.
[0031]
FIG. 3A schematically shows an example of a state in which data in each memory cell activated by raising one word line is sequentially processed as described above. In the figure, the horizontal axis represents the passage of time, the upper row shows the names of the data lines connected to the read path R1 and the time required for reading, the middle row shows the data processing time by the arithmetic circuit 40, and the lower row shows the write path W1. The names of the connected data lines and the time required for writing are shown.
[0032]
The flow of data is indicated by a dashed arrow. For example, data read from the memory cell over the time tr from the data line DL1 connected to the read path R1 is processed by the arithmetic circuit 40 during the time tc. It takes tw time through the write path W1 and the data line DL1 to be written to the memory cell again. Looking at FIG. 3A in the data flow in the vertical direction, for example, when the data line DL3 is connected to the read path R1, the arithmetic circuit 40 processes the data transferred from the data line DL2, and the write path W1 In FIG. 2, data transferred from the data line DL1 and processed by the arithmetic circuit 40 is transferred to the data line DL1. That is, a series of operations of reading from a memory cell, calculating data, and writing to a memory cell are performed at once, and apparently the time required for data processing is reduced.
[0033]
Assuming that the data operation time tc is the longest of the read time tr from the memory cell, the data operation time tc, and the write time tw to the memory cell, q data lines DL1, DL2,. ... The time required to process all q data appearing on DLq is (tr + q × tc + tw), and high-speed data processing is possible. Further, among the read time tr, the calculation time tc, and the write time tw, the processing time when the read time tr or the write time tw is the longest is (q × tr + tc + tw) and (tr + tc + q × tw), respectively. In the case of the above-described conventional semiconductor device, high-speed data processing is possible as compared with the processing time of q × (tr + tc + tw).
[0034]
FIG. 3B shows a timing chart when the above processing is performed. While one word line rises, reading / writing is partially performed simultaneously through a read pass / write pass. For example, at the same time that the data from the data line DL3 is transmitted to the read path R1 of the arithmetic circuit, the data of the operation result is transmitted to the data line DL1 from the write path W1 of the arithmetic circuit. This operation is performed in parallel with the operation of processing the data previously read from the data line DL2 by the arithmetic circuit.
[0035]
On the other hand, referring to FIG. 3C of the conventional example, the word line is raised to read data from the data line DL1 ', the word line is lowered, and after the processor performs data processing, the word line is raised and written again. Is performed, and the word line is lowered, and the word line is raised again to read data from the next data line DL2 '. Such an operation is performed by bus arbitration, and is inevitable when a normal memory chip and a processor chip are connected by a bus.
[0036]
Therefore, when the operation of the present invention is compared with the conventional example, the present invention has advantages such as no need for bus arbitration, no need for read / write switching time, and no need for restarting the word line. can give. Therefore, it is understood that the present invention can perform high-speed data processing.
[0037]
Furthermore, since the data transfer circuit 30 can perform the reading and the writing independently, it is easy to operate the data transfer circuit 30 at a timing other than that described here in accordance with the purpose. For example, it is possible to read data from the data lines DL1, DL2, and DL3 continuously, perform an operation using the three data, and then write the data to the data line DL1. Suitable for processing.
[0038]
Further, in the image memory, there is a request to write constant data into the memory cell at high speed in order to clear the screen, and the data transfer circuit 30 is effective to satisfy this request. In this case, data to be written may be output to the write path in advance, and a plurality of data lines may be connected to the write path at the same time. Thus, data can be simultaneously written to a plurality of memory cells at a time. If necessary, by simultaneously activating a plurality of word lines, it is possible to simultaneously write data to more memory cells at a time, so that the screen can be cleared faster.
[0039]
According to the data transfer circuit 30 of the present embodiment, the data in the memory cell column activated by the once activated word line can be sequentially processed while the word line is activated. The number of times of increase and the number of times of operation of the sense amplifier are reduced, which is effective for speeding up data processing and reducing power consumption. Further, for example, data is read from a memory cell group selected by a series of data lines DL1, DLq + 1, DL2q + 1,... DL (p-1) q + 1 connected by a signal line SS1, and another signal line SS2 Since it is possible to write data to the memory cell group selected by a series of connected data lines DL2, DLq + 2, DL2q + 2,..., DL (p−1) q + 2, the arithmetic circuit 40 performs reading / writing. There is no need to wait for time, and high-speed data processing can be performed.
[0040]
Further, when there is a large gap between the data line pitch of the memory cell array 10 and the width of one arithmetic circuit 40 on the layout of the chip 90, the pitch of the data lines is Although it is necessary to match the width of the arithmetic circuit 40, according to the semiconductor device of this embodiment, the data transfer circuit 30 can reduce the data line pitch to q: 2. Therefore, by setting this ratio in accordance with the pitch difference, the arithmetic circuit 40 and the memory cell array 10 can be laid out with high density.
[0041]
Further, the semiconductor device of this embodiment can be used as a normal memory. In that case, the control circuit 80 receives a control signal and a clock from the outside through the I / O port 81, and controls the sense amplifier 20, the decoder 70, and the serial access memories 50 and 60 according to the clock. An address is input from an input port 71, and data input / output is performed by the serial access memories 50 and 60 through I / O ports 51 and 61. Therefore, it is possible to use the semiconductor device of the present embodiment exclusively for image processing, and to change the application in a time-division manner, such as using it as a normal memory for the main memory of the system when necessary. A smaller system configuration is possible by using the device.
[0042]
Further, the area of the memory cell array 10 can be divided into a part used as a normal memory and a part exclusively used by the arithmetic circuit 40. For example, when applied to image processing, the system may want to change the memory size exclusively used by the arithmetic circuit 40 in order to cope with the nature of the image to be processed, the screen size, the display speed, and the like. In such a case, of the entire memory size, only the memory necessary for the image processing is used exclusively for the arithmetic circuit to perform the image processing, and the remaining part may be used as a normal memory for the main memory of the system.
[0043]
As described above, since one chip can cope with various uses, labor and time required for chip design can be saved. In addition, since unnecessary memory can be used for the main memory of the system, a smaller system configuration can be achieved. In addition, image processing can be performed in parallel by the semiconductor device of this embodiment and another processor, thereby achieving higher-speed processing. Is possible.
[0044]
When displaying an image on a display or sequentially processing image data stored in a memory, data processing is performed on the entire memory cell array 10. Normally, when a DRAM is used for a memory cell, refreshing is required. However, in the above case, if the time for accessing the entire memory cell array is shorter than the information holding time of the memory cell, the refreshing is not necessary. Therefore, in such a case, even if a DRAM is used as a memory cell, a refresh cycle is not necessary, so that a higher-speed operation can be expected. Further, a circuit for refreshing is not required. The size can also be reduced.
[0045]
Here, the switch S used in the data transfer circuit 30 shown in FIG. _j k (j = 1 to p, k = 1 to q) using MOS transistors, the switch S ₁ 1 is shown in FIG. 6 as an example. In FIG. 6, the switch S ₁ 1 includes two MOS transistors TrR and TrW. In this configuration example, the switch S ₁ 1 is required to be input to the gate of each MOS transistor, so that there are two signal lines SS1R for connecting the read path and the signal line SS1W for connecting the write path. When the MOS transistor TrR is turned on by the signal line SS1R, the data line DL1 is connected to the read path R1, and when the MOS transistor TrW is turned on by the signal line SS1W, the data line DL1 is connected to the write path W1.
[0046]
Further, in the semiconductor device of the present embodiment, a data line pair DL1T, DL1B, DL2T, DL2B, DL1T, DL1B, DL2T, DL2B,. ... There may be a case where it is desired to use DLqT and DLqB to transfer different signals. In such a case, the switch S used in the data transfer circuit 30 _j As k (j = 1 to p, k = 1 to q), the configuration shown in FIG. 7 can be adopted. FIG. 7 shows the switch S ₁ 1 is shown as an example. In this case switch S ₁ 1 is composed of four MOS transistors TrRT, TrWT, TrRB, TrWB. The read path R1 and the write path W1 also correspond to the data line pair DL1T and DL1B, respectively, that is, the read path pair R1T and R1B and the write path pair W1T and W1B. As in FIG. 6, the signal line SS1 includes two signal lines SS1R for connecting a read path and a signal line SS1W for connecting a write path. When the MOS transistors TrRT and TrRB are both turned on by the signal line SS1R, the data line pairs DL1T and DL1B are connected to the corresponding read path pairs R1T and R1B, respectively. To connect the data line pairs DL1T and DL1B to the corresponding write path pairs W1T and W1B, both the MOS transistors TrWT and TrWB may be turned on by the signal line SS1W.
[0047]
If both the read path and the write path do not need to be paired, the switch S ₁ 1 may have the configuration shown in FIG. The configuration of FIG. 8 is suitable when the pitch of the data line pair is narrow and it is difficult to arrange the transistors in the configuration example of FIG. Here, a case in which one read path is paired with one write path is shown, but it is needless to say that one read path and one write path may be paired as necessary.
[0048]
As described above, referring to FIG. 6 to FIG. _j Although the case where k (j = 1 to p, k = 1 to q) is shown as an example, it is needless to say that a pMOS transistor or a CMOS transistor may be used as necessary. .
[0049]
<Example 2>
FIG. 4 is a block diagram of a basic circuit configuration showing another embodiment of the semiconductor device according to the present invention. The same components as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals for convenience of description, and detailed description thereof will be omitted. That is, in the present embodiment, the read path and the write path are hierarchically formed by adding the p signal lines SSR1 to SSRp and the p signal lines SSW1 to SSWp to the configuration of the data transfer circuit and the control circuit for controlling the data transfer circuit. Is different.
[0050]
Here, a detailed configuration of the data transfer circuit 32 of the present embodiment is shown in FIG. Note that the transfer circuit 32 shown in FIG. 5 is only a part of one of the plurality of data transfer circuits 32 in FIG. 4, and the block 1 of the data transfer circuit 30 shown in FIG. (For example, the first block of FIG. 2 is shown). The data transfer circuit 32 further comprises q data lines as y small blocks each consisting of x small blocks, and y data lines in each small block are signal lines from the control circuit 82. In accordance with the signals of SSR1 to SSRx, each switch is connected to one read path R1 via one switch SR1 to SRx corresponding to each small block in the connection or open state, and is connected to one signal path SSW1 to SSWx. The switches are connected to one write path W1 via one switch SW1 to SWx each performing the same operation. Therefore, in each small block, a required data line is selected from xy (= q) data lines in each small block by the signals of the signal lines SS1 to SSy of the control circuit 82, and the corresponding switch S ₁ 1 to S _X The selected data line is connected to the read path side connection line or the write path side connection line of y, and the switch SR1 to SRx or the switch SW1 to SWx is closed by the signal of the signal line SSR1 to SSRx or the signal of SSW1 to SSWx, and corresponds. It can be connected to the read path R1 or the write path W1.
[0051]
By hierarchizing the read path and the write path in this way, the control circuit 82 of the present embodiment newly needs to control a total of 2x signal lines SSR1 to SSRx and SSW1 to SSWx. There are advantages.
That is, in the configuration of the data transfer circuit 30 shown in FIG. 2, the number of data lines connected to one read path or write path is q, but the data transfer circuit 32 of this embodiment shown in FIG. The number of data lines connected to one read path or write path can be reduced to less than q. If the number of the data lines is too large, the number of the signal lines SS1 to SSq also increases, and the capacity appearing on the read path and the write path increases, thereby lowering the operation speed. In such a case, the data transfer circuit 32 has a hierarchical structure. The control circuit 82 controls the signal lines SSR1 to SSRx and SSW1 to SSWx, which are required in accordance with the configuration, and opens one of the switches SR1 to SRx or the switches SW1 to SWx corresponding to the small blocks that do not need to be connected. Since more data lines can be connected to one read path and write path without increasing the load capacitance appearing on the write path, the read and write operations can be speeded up.
[0052]
The fact that the load capacity of the hierarchically structured data transfer circuit 32 is lighter than that of the data transfer circuit 30 of FIG. 2 will be briefly described. Here, each switch S ₁ 1 to S _x y, S ₁ 1 to S _p The case where q is constituted by two MOS transistors and each of the switches SR1 to SRx and SW1 to SWx is constituted by one MOS transistor will be described as an example.
[0053]
The approximate load capacitance when the data line DL1 is connected to the read path R1 is estimated for each of the data transfer circuits 30 and 32.
Assuming that the source / drain capacitance of the MOS transistor is Cd, the load capacitance viewed from the read path R1 is the switch S in the case of the data transfer circuit 30 of FIG. ₁ When 1 is off, Cd × q. Note that Cd also includes the parasitic capacitance with the gate. Switch S ₁ 1 is turned on, Cd is further added, so that the total capacitance C _FIG2 Is Cd × (q + 1). On the other hand, in the case of the data transfer circuit 32 in FIG. 5, the load capacitance viewed from the read path R1 is Cd × x when the switches SR1 to SRx are off. When the switch SR1 is turned on, Cd × (y + 1) is further added, and the switch S1 is turned on. ₁ 1 is turned on and Cd is further added, so that the total capacitance C _FIG5 Is Cd × (x + y + 2).
[0054]
Here, the capacity C _FIG2 And capacity C _FIG5 Take the ratio of C _FIG2 / C _FIG5 = K is smaller than 1, ie, the capacitance C _FIG5 Is the capacity C _FIG2 When considering the case where x and y are both larger, the following equation is obtained because both x and y are positive integers.
[0055]
(Equation 1)

Therefore, according to equation (1), only when (x, y) = (2, 3) or (3, 2), the capacitance C _FIG5 Is the capacity C _FIG2 Be larger. In other words, if x and y each become 3 or more, the load capacitance C of the data transfer circuit 32 _FIG5 Is smaller. In addition, since the value of K increases as x and y increase, the load capacity of the data transfer circuit 32 is smaller than that of the data transfer circuit 30.
[0056]
In addition, in the data transfer circuit 32 of the present embodiment, the configuration in which the q data lines in the data transfer circuit 30 in FIG. 2 are divided into one block is divided into y small blocks of x. In the data transfer circuit 30, the number of signal lines for controlling the switches from the control circuit 80 is x × y (= q), whereas in the data transfer circuit 32, the number of signal lines from the control circuit 82 is y + 2x. is there. For this reason, by using the configuration of the data transfer circuit 32 of this embodiment, when the number of data lines increases, the increase in the number of signal lines can be suppressed, which is useful for reducing the chip area and for reducing the number of signal lines. Since the range of selection of the number of data lines that can be connected to the write path and the read path is widened, design flexibility is improved. Each switch S ₁ 1 to S _x y, S ₁ 1 to S _p When q is composed of two MOS transistors, it is necessary to input a signal line to each gate. Therefore, the number of signal lines SS1 to SSy and SS1 to SSq from the control circuits 80 and 82 described above is The number is doubled.
[0057]
Similarly to the first embodiment, the semiconductor device of the present embodiment can also be used as a normal memory, and is usually used exclusively for image processing, and when necessary, used as a normal memory for a main memory of a system. It is also possible to change the application by time sharing. Further, it is needless to say that the same effect as that of the first embodiment can be obtained, for example, the area of the memory cell array can be used separately from a part used as a normal memory and a part exclusively used in an arithmetic circuit.
[0058]
Each switch S used in the data transfer circuit 32 shown in FIG. ₁ 1 to S _x As for the specific configuration using the MOS transistor y, any of the configurations shown in FIGS. 6 to 8 may be used as needed, as in the first embodiment.
[0059]
The preferred embodiment of the present invention has been described above. However, the present invention is not limited to the above-described embodiment, and it is needless to say that various design changes can be made without departing from the spirit of the present invention.
[0060]
【The invention's effect】
As is clear from the above-described embodiment, according to the semiconductor device of the present invention, the data transfer circuit provided between the memory cell array and the arithmetic circuit is used to read data from the memory cell and write data to the memory. Are provided independently so that the read / write operation can be performed at the same time, so that the time mx (tr + tc + tw) required for data processing is reduced to (mxtr + tc + tw), (tr + mxtc + tw), or ( tr + tc + m × tw), etc., enabling a significant increase in speed, and by sequentially performing data processing in memory cells on the word line once started, the number of times the word line starts up is reduced, thereby reducing power consumption. Can be achieved.
[Brief description of the drawings]
FIG. 1 is a block diagram of a basic configuration showing one embodiment of a semiconductor device according to the present invention.
FIG. 2 is a detailed circuit configuration diagram showing an example of a data transfer circuit used in the semiconductor device of FIG.
3A and 3B are diagrams for comparing and explaining an operation of the semiconductor device according to the present invention and a conventional operation. FIGS. 3A and 3B are operation examples of the semiconductor device of FIG. 1; It is.
FIG. 4 is a block diagram of a basic configuration showing another embodiment of the semiconductor device according to the present invention.
FIG. 5 is a detailed circuit configuration diagram showing one example of a data transfer circuit used in the semiconductor device of FIG. 4;
FIG. 6 shows a switch S used in the data transfer circuit of the semiconductor device according to the present invention. ₁ 1 is a circuit configuration diagram illustrating an example of a specific configuration example of FIG.
FIG. 7 shows a switch S used in a data transfer circuit of a semiconductor device according to the present invention. ₁ FIG. 9 is a circuit configuration diagram showing another example of the specific configuration example of FIG.
FIG. 8 shows a switch S used in the data transfer circuit of the semiconductor device according to the present invention. ₁ FIG. 9 is a circuit configuration diagram showing another example of the specific configuration example 1;
[Explanation of symbols]
10 ... memory cell array,
20: sense amplifier,
30 ... data transfer circuit,
32 ... data transfer circuit,
40 arithmetic circuit,
50 ... Serial access memory,
51 ... I / O port,
60 ... Serial access memory,
61 ... I / O port,
70 ... decoder,
71 input port,
80 ... control circuit,
81 ... I / O port,
82 control circuit,
90 ... silicon chip,
C _ij (I = 1 to n, j = 0 to m) ... memory cell,
DLj, DLj '(j = 1 to m) ... data line,
DL1B, DL1T data line,
WLi (i = 1 to n): word line,
S _j k (j = 1 to p, k = 1 to q) ... switch,
SR1 to SRx ... switches,
SW1 to SWy ... switches,
SSj (j = 1 to q), SS1R, SS1W ... signal line,
SSR1 to SSRy ... signal lines,
SSW1 to SSWx ... signal lines,
TrR, TrRB, TrRT ... transistor,
TrW, TrWB, TrWT ... transistor,
Rj (j = 1 to p), R1B, R1T... Lead path,
Wj (j = 1 to p), W1B, W1T... Light path.

Claims (17)

A memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells;
An arithmetic circuit;
A read path and a write path connected to the arithmetic circuit;
A switch circuit for connecting at least one of the plurality of bit lines to the read path, and connecting at least another one of the plurality of bit lines to the write path;
A semiconductor device comprising: a serial access memory connected to the memory cell array for inputting / outputting data via an I / O port;
The semiconductor device may further include a read operation for transferring data from the memory cell to the arithmetic circuit through the read path, an arithmetic operation for processing the data in the arithmetic circuit, and an output of the arithmetic operation from the arithmetic circuit through the write path. And a write operation of transferring data to the memory cell.
The read operation is performed by connecting a part of the plurality of bit lines to a read path via the switch circuit from a memory cell selected by one of the plurality of word lines. Is the operation of reading
In the write operation, another part of the plurality of bit lines is connected to the write path via the switch circuit to a memory cell selected by the one word line that is the same as the read operation. This is the operation of writing data,
The semiconductor device is for performing the read operation and the write operation in parallel within the period selected by the one word line,
The semiconductor device sequentially performs the read operation, the arithmetic operation, and the write operation in a pipeline,
The read data read from the memory cell by the read operation is processed by the arithmetic operation, and the memory cell to which the result of the arithmetic operation is written by the write operation stores the read data by the read operation. A semiconductor device comprising the same memory cell . In claim 1 ,
A semiconductor device, wherein the memory cell array and the arithmetic circuit are formed on the same semiconductor chip. In claim 1 or 2 ,
Wherein the plurality of Each of the memory cell, the semiconductor device comprising a memory cell der Turkey dynamic type. A memory for storing data,
An operation circuit for receiving the data from the memory, performing an operation, and outputting an operation result to the memory;
A serial access memory for inputting / outputting the data via an I / O port;
The arithmetic circuit has a first receiving operation for receiving first data, and a second receiving operation for subsequently receiving second data ,
A third receiving operation of receiving the third data after the second receiving operation, and a first output operation of outputting an operation result of the first data to the memory;
The operation of the first data is executed in parallel with the second receiving operation, and the operation of the second data is executed in parallel with the third receiving operation and the first output operation,
The first output operation is to output to a position in the memory where the first data is stored,
The first receiving operation and the first output operation are performed during the same word line selection period,
It said third receiving operation and the first output operation, and wherein a Rukoto conducted in parallel with different memory cells of the plurality of memory cells selected by the same word line. Oite to claim 4,
The semiconductor device according to claim 1, wherein the memory includes a plurality of dynamic memory cells. In a semiconductor device having a memory cell array including a plurality of word lines, first, second, and third bit lines, and a plurality of memory cells,
A first node connected to the first bit line, a second node connected to the second bit line, a third node connected to the third bit line, fourth and fifth nodes, A first switch circuit for connecting the first node to the fourth or fifth node; a second switch circuit for connecting the second node to the fourth or fifth node; A transfer circuit including a third switch circuit for connecting three nodes to the fourth node or the fifth node;
An arithmetic circuit including a sixth node connected to the fourth node and receiving data, and a seventh node connected to the fifth node and outputting data;
A serial access memory connected to the memory cell array and for inputting / outputting data via an I / O port;
In the semiconductor device, the arithmetic circuit may receive first data from the first bit line, receive second data from the second bit line, and receive third data from the third bit line via the sixth node. Outputting a calculation result of the first, second, and third data via the seventh node sequentially during a period in which one of the plurality of word lines is activated. ,
In the first operation, the transfer of the third data to the sixth node and the transfer of the operation result from the operation circuit to the first bit line are performed in parallel. In claim 6 ,
In the first operation, the first, second, and third data are transferred from the fourth node to the sixth node according to respective connection states of the first, second, and third switch circuits, and the operation is performed. The result is transferred to the first bit line by the first switch circuit,
The semiconductor device according to claim 1, wherein the first switch circuit, the second switch circuit, and the third switch circuit are controlled by two independent signal lines. In claim 6 or 7 ,
The semiconductor device according to claim 1, wherein the first operation is a filtering process of an image stored in the memory cell array. In any one of claims 6 to 8 ,
The semiconductor device, wherein the semiconductor device is formed on one semiconductor chip. In any one of claims 6 to 9 ,
The memory cell array forms a quadrilateral region;
The arithmetic circuit is arranged along one side of the quadrilateral,
The semiconductor device according to claim 1, wherein the transfer circuit is disposed between the memory cell array and the arithmetic circuit. In any one of claims 6 to 10 ,
In the first operation, when the third switch circuit connects the third node to the fourth node, the first switch circuit can connect the first node to the fifth node. A semiconductor device, comprising: In any one of claims 6 to 11 ,
The semiconductor device according to claim 1, wherein the first bit line and the second bit line are arranged adjacent to each other, and the second bit line and the third bit line are arranged adjacent to each other. In any one of claims 6 to 11 ,
The semiconductor device further has a second operation,
In the second operation, the first, second, and third nodes are commonly connected to the fifth node, and the same operation result is transferred from the operation circuit to the first, second, and third bit lines. A semiconductor device, comprising: In claim 13 ,
In the second operation, one or more of the plurality of word lines are activated. In claim 14 ,
The semiconductor device according to claim 2, wherein the second operation is an operation for clearing image data stored in the memory cell array. A plurality of word lines, a plurality of bit lines, a memory cell array including a plurality of memory cells,
An arithmetic circuit;
A plurality of read paths and a plurality of write paths connected to the arithmetic circuit;
A switch circuit for connecting at least one of the plurality of bit lines to one of the plurality of read paths and connecting at least another of the plurality of bit lines to one of the plurality of write paths And
The arithmetic circuit sequentially receives data from the plurality of read paths, performs an operation, and outputs an operation result to the plurality of write paths,
Outputting the calculation result calculated during the data receiving period to the light path is performed,
The semiconductor device sequentially performs the reception of the data and the output of the operation result in a pipeline within a period selected by one of the plurality of word lines,
The read data read by the receiving operation is processed by the arithmetic operation, and the memory cell to which the result of the arithmetic operation is written is the same memory cell in which the read data is stored by the receiving operation. Yes,
The semiconductor device according to claim 1, wherein the plurality of memory cells are dynamic memory cells. In claim 16 ,
The semiconductor device, wherein the memory cell array and the arithmetic circuit are formed on the same semiconductor chip.

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