JP4150703B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for data processing in which a highly integrated memory and a plurality of arithmetic circuits are realized on one chip.

  2. Description of the Related Art Conventionally, there has been known a semiconductor device in which a processor and a memory are mounted on one board for processing a large amount of data such as image processing and used as a dedicated processing system to perform processing at high speed. In this conventional example, since a memory and a processor are connected via a bus, bus arbitration is required. When a large amount of data is repeatedly read / calculated / written, as shown in FIG. Switching took a lot of time and the data processing efficiency did not increase.

  Further, as a further advanced example, a plurality of arithmetic circuits and a memory cell array are mounted on the same chip, and data of memory cells on one word line in the memory cell array are read in parallel and read out. 2. Description of the Related Art Semiconductor devices that execute parallel data processing are known. As this type of semiconductor device, for example, “Aimoto, et al.“ Memory Unit Circuit Method of Memory Integrated Processor IMAP LSI ”, 1994 IEICE Spring Conference Proceedings 5-261 C-693” (Non-patent Document 1) ).

  In the above conventional example, a 2 Mb SRAM and 64 parallel arithmetic circuits are integrated, and the arithmetic circuits are operated in parallel by the SIMD (Single Instruction Stream Multiple Data Stream) method. In such a semiconductor device, various image data processing can be performed by operating a plurality of arithmetic circuits mounted on the same chip as the memory cell array in parallel with one instruction and repeatedly executing them. . When performing this image data processing, the calculation itself necessary for the data processing is not so difficult, but since the amount of data to be processed is enormous, it is necessary to repeat the same calculation many times.

When processing image data using a conventional semiconductor device equipped with the plurality of arithmetic circuits and the memory cell array, first, the data written in the memory cell is read, and then the necessary data is used using the SIMD type arithmetic circuit. The operation of performing the operation and finally writing the operation result to the memory cell is repeatedly executed. Here, it is assumed that the time required for reading is tr, the time required for calculation is tc, and the time required for writing is tw. In the conventional semiconductor device, if a series of operations of reading, calculation, and writing are sequentially performed, the total time required is (tr + tc + tw), and the required time when this is repeated m times is m × (tr + tc + tw). It becomes.
In the future, as the semiconductor manufacturing technology advances, miniaturization advances and high-speed operation of the arithmetic circuit can be expected. Therefore, if the operation contents are the same, the time tc required for the operation can be shortened.

Aimoto, et al. “Memory Unit Circuit Method for Memory Integrated Processor IMAP LSI”, Proceedings of the 1994 IEICE Spring Conference, 5-261 C-693

  However, according to the conventional semiconductor device in which the plurality of arithmetic circuits and the memory cell array are integrated on the same chip, the memory cell array is the same as the case of the arithmetic circuit even if the miniaturization is advanced by the progress of the semiconductor manufacturing technology. On the other hand, as the size becomes smaller, it becomes more difficult to increase the signal amount from the memory cell, so that the time tr and tw required for reading and writing cannot be shortened much. For this reason, in the case of image data processing in which arithmetic processing is applied to data read from the memory cell and writing back to the same memory cell is repeated, the data processing operation is limited by the reading time tr and the writing time tw. There is a problem.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can increase the data processing time when the same calculation is repeatedly performed as in image data processing and can reduce power consumption.

  Another object of the present invention can be used not only for image data processing but also as a main memory as a normal memory, or can be used for various purposes in which an image data processing part and a normal memory part can be divided. And providing a simple semiconductor device.

  In order to solve the above-described problem, a semiconductor device according to the present invention includes a memory cell array having a plurality of memory cells arranged at intersections of a plurality of data lines and a plurality of word lines, and a plurality of different memory cells in the memory cell array. A decoder that selects at least one of the word lines to read information stored in the memory cell to a plurality of different data lines intersecting the word line; at least one arithmetic circuit; and the arithmetic circuit and the memory cell array. In a semiconductor device in which a data transfer circuit for transferring data between them and at least a data transfer circuit, a decoder, and a control circuit for controlling an arithmetic circuit are integrated on one chip, the data transfer circuit is connected to a word line selected by the decoder. Write to some data lines and read from some other data lines As can be performed in at least a portion same in one hour, it is characterized in that it has been independently the read path and the write path.

  In the semiconductor device, the data transfer circuit selects a required number of data lines from among the plurality of data lines, reads each data read on the data line to the arithmetic circuit, and the read function. Can independently have a function of selecting a required number of data lines out of the plurality of data lines and writing from the arithmetic circuit to the memory cell via the data lines.

  The function of reading each data read on the data line to the arithmetic circuit includes a switch controlled by a signal from the control circuit provided between the read path and each data line, and the data line The function of writing the operation result from the operation circuit to the memory cell via the switch can be constituted by a switch controlled by a signal from the control circuit provided between the write path and each data line.

  Further, the data transfer circuit includes a plurality of blocks formed by dividing a plurality of data lines into a required number, one or a pair of read paths and one or a pair of write paths provided for each block. In addition, the control circuit controls the connection state to any one of a connection to a read path, a connection to a write path, and an open state provided between each data line in each block and the read path and the write path of each block. It is suitable if it comprises a switch.

  Further, the data transfer circuit is divided into small blocks obtained by dividing each block into a smaller number of data lines, and each data line in each small block and the read path side and write of each small block are written. A switch controlled by the control circuit to any one of a connection state to a lead path connection line, a connection to a write path connection line, and an open state provided on the path side, and each lead path connection line and lead path of each small block And a switch that is turned on / off by the control circuit provided between each light path connection line and the light path of each small block. May be.

  In any of the semiconductor devices, a function of directly accessing data stored in the memory cell array from the outside can be provided.

Further, the semiconductor device according to the present invention is provided at each of the word line, the first and second data lines intersecting the word line, and the intersection of the word line and the first and second data lines. First and second memory cells, an arithmetic circuit, a read path connected to an input terminal of the arithmetic circuit, a write path connected to an output terminal of the arithmetic circuit, the first data line, and the read path Or a first switch means for connecting to the write path, and a second switch means for connecting the second data line to the read path or the write path, and the word line is activated. The first switch means connects the first data line and the read path, and the second switch means connects the second data line and the write path. Features A.
[Action]
According to the semiconductor device of the present invention, the data transfer circuit is connected between the memory cell array that holds data and the arithmetic circuit that receives the data and performs the arithmetic operation. By having separate write paths for sending data to the memory cells, it is possible to transfer the output of the memory cell array to the arithmetic circuit and simultaneously transfer the output of the arithmetic circuit to the memory cell array. That is, since the read path and the write path are independent, it is possible to select different data lines between the memory cell array and the arithmetic circuit and execute the read operation and the write operation partially overlapping each other in the same time. . Therefore, when the process of reading data from the memory cell, performing an operation, and writing back the result to the memory cell is repeatedly performed, since the read path and the write path are separately provided, the data can be read and written simultaneously. . For this reason, the processing time m × (tr + tc + tw) conventionally required when a series of processing is repeated m times can be apparently shortened to tr + m × tc + tw by performing, for example, reading and writing within the calculation time tc. It becomes.

  Further, the switch controlled by a signal from the control circuit provided between the lead path and each data line connects the lead path and the data line, thereby selecting the required requirements among the plurality of data lines. The data read on the number of data lines can be read out to the arithmetic circuit, and the switch controlled by the signal from the control circuit provided between the write path and each data line is the plurality of data The calculation result can be written from the arithmetic circuit to the memory cell through the selected required number of data lines among the lines.

  Further, the data transfer circuit includes a plurality of blocks formed by dividing a plurality of data lines into a required number, one or a pair of read paths and one or a pair of write paths provided for each block. And a control circuit provided between each data line in each block and the read path and write path of each block, the connection state to the read path, the connection to the write path, or the open state is controlled. By configuring the switch, the data line from one block can be connected to the read path to read data from the memory cell, and at the same time, the data line in the same block can be connected to the write path to perform the operation of the arithmetic circuit. The result can be written into the memory cell.

  Further, the data transfer circuit is divided into small blocks obtained by dividing each block into a smaller number of data lines, and each data line in each small block and the read path side and write of each small block are written. A switch controlled by the control circuit to any one of a connection state to a lead path connection line, a connection to a write path connection line, and an open state provided on the path side, and each lead path connection line and lead path of each small block And a switch that is turned on / off by the control circuit provided between each light path connection line and the light path of each small block. Thus, the read path and write path are hierarchized, and the number of signal lines for controlling the switch is reduced. It can be.

  Further, by providing a function for directly accessing the data stored in the memory cell array from the outside, the semiconductor device according to the present invention can be used exclusively for image processing, and can be used as a normal memory as needed, or the memory cell array Of these, only the number of memory cells required for image processing can be used exclusively for the arithmetic circuit, and the remaining portion can be used for a normal memory.

  As is apparent from the description of the embodiments, according to the semiconductor device of the present invention, the data transfer circuit provided between the memory cell array and the arithmetic circuit has a path for reading data from the memory cell and writing to the memory into the cell. Are provided independently so that read / write operations can be performed simultaneously, so that the time required for data processing m × (tr + tc + tw) is (m × tr + tc + tw), (tr + m × tc + tw), or ( tr + tc + m × tw), etc., and it is possible to significantly increase the speed and reduce the power consumption by reducing the number of word line start-ups by sequentially performing the data processing in the memory cells on the word lines once started up. Can be achieved.

  Next, embodiments of the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a basic circuit configuration showing an embodiment of a semiconductor device according to the present invention. In FIG. 1, reference numeral 10 denotes a memory cell array, and this memory cell array 10 is arranged at each intersection of n word lines WLi (i = 1 to n) and m data lines DLj (j = 1 to m). i-rows and j is a memory cell DRAM cell array composed of C _ij column, each word line WLi is connected to a decoder 70 for selecting a memory cell C _ij which becomes active in the memory cell array 10. An input port 71 is connected to the decoder 70 so that an address can be designated from the outside. Each data line DLj is connected to a serial access memory 60 that performs data transfer with the outside via an I / O port 61, and a plurality of data lines DLj are connected via a sense amplifier 20 that amplifies and holds a signal read from the memory cell array 10. And is connected to a plurality of data transfer circuits 30 corresponding to each block. Each data transfer circuit 30 is connected to each corresponding arithmetic circuit 40 and transfers data read from the memory cell array 10 to each arithmetic circuit 40. Each arithmetic circuit 40 is connected via an I / O port 51 to a serial access memory 50 that transfers data with the outside. Further, a control circuit 80 for controlling the whole is connected to the outside through the I / O port 81 and is connected to the circuits 20, 30, 40, 50, 60, 70. The above circuits, I / O ports, and the like are integrated on one silicon chip 90.

The operation of the semiconductor device according to the present invention configured as described above will be described below.
This semiconductor device performs data processing on data input from the outside of the chip 90 via the I / O port 51 and the serial access memory 50 and data in the memory cell array 10 using the arithmetic circuit 40. Can do. The control circuit 80 that receives a command and clock from the outside through the I / O port 81 controls the operations of the decoder 70, sense amplifier 20, data transfer circuit 30, arithmetic circuit 40, serial access memory 50, and serial access memory 60 according to the clock. To do. Upon receiving an instruction from the control circuit 80, the decoder 70 raises the word line WLi selected in accordance with the address specified by the input port 71 or the control circuit 80, and the i row of memory cell columns C _i1 , C _i2 , C _i3 ,... C _im is activated. The contents of the activated memory cell are taken out via the respective data lines DL1 to DLm connected to each memory cell, amplified by the sense amplifier 20, and held. Each data transfer circuit 30 calculates the contents of i rows of memory cell columns C _i1 , C _i2 , C _i3 ,... C _im in accordance with the signal lines SS 1, SS 2, SS 3,. Send to 40.

  A detailed configuration of the data transfer circuit 30 is shown in FIG. Only one of the plurality of data transfer circuits 30 in FIG. 1 is shown. The data transfer circuit 30 is composed of p blocks as a whole, with one read path and one write path and one block of q data lines. Each block can be connected to one read path and one write path from q data lines in the block.

When one word line WLi is activated and the contents of i rows of memory cell columns C _{i1 to} C _im are taken out by the data lines DL1 to DLm and amplified and held by the sense amplifier 20, the sense amplifier 20 The data appears on the respective data lines DL1 to DLm connected to the respective data transfer circuits 30 via. Since the data transfer circuit 30 shown in FIG. 2 is connected to p × q data lines DL1 to DLpq, data appears on the data lines DL1 to DLpq.

For example, the switches S ₁ 1, S ₂ 1, S ₃ 1,... S _p 1 in the first block to the p-th block are respectively connected to the lead paths R 1 and R ₂ according to the signal on the signal line SS 1 output from the control circuit 80. , R3,... Are connected to the Rp side. As a result, the data on the data lines DL1, DLq + 1, DL2q + 1,... DL (p-1) q + 1 are transferred to the arithmetic circuit 40 through the read paths R1, R2, R3,. The arithmetic circuit 40 performs a required operation using the data sent from the data transfer circuit 30 and the data input from the outside of the chip 90 to the serial access memory 50 via the I / O port 51, and calculates The result is output to each light path W1, W2, W3,... Wp.

When the data of the operation result is written back to each read memory cell, the control circuit 80 sends a signal to the signal line SS1 after a predetermined operation time determined in advance for the operation. Each switch S ₁ 1, S ₂ 1, S ₃ 1,... S _p 1 is connected to the light path W 1, W 2, W 3,. As a result, the arithmetic circuit 40 writes the arithmetic result to each of the memory cells C _i1 , C _{i (q + 1)} , C _{i (2q + 1)} ,... C _{i ((p−1) q + 1)} through the data transfer circuit 30.

Switch It should be noted that the switches _{S 1 1, S 2 1,} S 3 1, ...... S p 1 may take read path side in response to signals from the control circuit 80, the write path side, and one of the connection state of an open It is normally open. Further, the arithmetic circuit 40 may be configured to send a signal indicating the completion of the calculation to the control circuit 80 instead of the control circuit 80 transmitting a signal to the signal lines SS1 to SSq when a predetermined calculation time has elapsed. Good. In this case, since the control circuit 80 can easily control the signal lines SS1 to SSq by this calculation end signal, the design of the control circuit 80 can be simplified. That is, even when the arithmetic circuit 40 is changed so that it can perform a complicated operation, it is not necessary to estimate the time required for the complicated operation in advance and redesign, and the control circuit 80 can be used without being changed. it can.

  Although the case where data is written back to the memory cell from which reading has been described has been described here, writing to another memory cell is also easy. In that case, a switch connected to a required data line may be selected by the signal lines SS1, SS2,. Further, when writing the same data to a plurality of memory cells, a plurality of switches may be connected to one write path by a plurality of signal lines SS1, SS2,.

Thus, according to the semiconductor device of the present embodiment, necessary data is read from another memory cell using the read path while the arithmetic circuit is writing to the memory cell via the write path. be able to. For example, each data transfer circuit 30 has memory cells C _i1 , C _{i (q + 1)} , C _{i (2q + 1)} ,... C _{i ((p−1)} through the respective write paths W 1, W 2, W 3 _{,. q + 1)} , a path for writing data to each switch S ₁ 1, S ₂ 1, S ₃ 1,... S _p 1 is set to the respective write path side by a signal on the signal line SS 1 from the control circuit 80. and at the same time connected to the signal lines each switch _{S 1} 2 by a signal _{SS2, S 2 2, S 3} 2, connect ...... _{S p} 2 in each of the read path side, the data line DL2, DLq + 2, DL2q + 2 ,... DL (p-1) q + 2 is connected to the lead paths R1, R2, R3,. Thereby, the data of the memory cells C _i2 , C _{i (q + 2)} , C _{i (2q + 2)} ,... C _{i ((p−1) q + 2)} can be read and transferred to the arithmetic circuit 40. If necessary, such write and read operations are sequentially repeated, and i rows of memory cell columns C _i1 , C _i2 , C _i3 ,... C are activated by the word line WLi selected by the decoder 70. _What is necessary is just to process the data in _im . Further, by processing other word lines and performing the same processing on the memory cell columns in other rows, it is possible to perform processing on all the data in the memory cell array 10.

  FIG. 3A schematically shows an example of how data in each memory cell that has been activated by sequentially raising one word line is sequentially processed as described above. In the figure, the horizontal axis represents the passage of time, the upper line shows the name of the data line connected to the read path R1 and the time required for reading, the middle stage shows the data processing time by the arithmetic circuit 40, and the lower stage shows the write path W1. The name of the connected data line and the time required for writing are shown.

  The flow of data is indicated by dashed arrows. For example, data read from the memory cell over the time tr from the data line DL1 connected to the read path R1 is processed by the arithmetic circuit 40 during the time tc, Data is written to the memory cell again through the write path W1 and the data line DL1 over tw time. Looking at FIG. 3A in the data flow in the vertical direction, for example, when the data line DL3 is connected to the read path R1, the arithmetic circuit 40 processes the data transferred from the data line DL2, and the write path W1. Then, the data transferred from the data line DL1 and processed by the arithmetic circuit 40 is transferred to the data line DL1. That is, a series of operations of reading from the memory cell, calculating data, and writing to the memory cell are performed at one time, and apparently the time required for data processing is shortened.

  If the data calculation time tc is the longest among the read time tr from the memory cell, the data calculation time tc, and the write time tw to the memory cell, q data lines DL1, DL2,. ... The time required to process all q data appearing on DLq is (tr + q × tc + tw), and high-speed data processing is possible. Of the read time tr, calculation time tc, and write time tw, the processing times when the read time tr or the write time tw is the longest are (q × tr + tc + tw) and (tr + tc + q × tw), respectively. In the case of the semiconductor device of the conventional example described above, the processing time is higher than that of q × (tr + tc + tw).

  FIG. 3B shows a timing chart when the above processing is performed. While one word line is rising, a part of read / write is simultaneously performed through the read pass / write pass. For example, data from the data line DL3 is transmitted to the read path R1 of the arithmetic circuit, and at the same time, the data of the arithmetic result is transmitted from the write path W1 of the arithmetic circuit to the data line DL1. This operation is performed in parallel with the operation of processing the data previously read from the data line DL2 by the arithmetic circuit.

  On the other hand, referring to FIG. 3C of the conventional example, the word line is raised to read data from the data line DL1 ', the word line is lowered, the processor processes the data, and then the word line is raised again to write. The word line is lowered and the word line is raised to read data from the next data line DL2 ′. Such work is performed by bus arbitration, and cannot be avoided when a normal memory chip and a processor chip are connected by a bus.

  Therefore, when the operation of the present invention is compared with the conventional example, the present invention has advantages such as no need for bus arbitration, no read / write switching time, and no need to restart the word line. can give. Therefore, it can be seen that the present invention is capable of high-speed data processing.

  Furthermore, since the data transfer circuit 30 can perform reading and writing independently, it is easy to operate at timings other than those described here according to the purpose. For example, it is possible to operate at the timing of reading data continuously from the data lines DL1, DL2, and DL3 and writing to the data line DL1 after performing an operation using three data. Suitable for processing.

  In addition, the image memory has a request to write constant data to the memory cell at high speed in order to clear the screen. The data transfer circuit 30 is also effective in satisfying this request. In this case, data to be written in advance may be output to the write path, and a plurality of data lines may be simultaneously connected to the write path. As a result, data can be simultaneously written into a plurality of memory cells at a time. If necessary, it is possible to simultaneously write data to a larger number of memory cells at the same time by raising a plurality of word lines at the same time, so that the screen can be cleared at high speed.

  According to the data transfer circuit 30 of the present embodiment, the data in the memory cell column activated by the word line once raised can be sequentially processed while the word line is raised. The number of times of increase and the number of operations of the sense amplifier are reduced, which is effective in speeding up data processing and reducing power consumption. Further, for example, simultaneously with reading data from the memory cell group selected by the series of data lines DL1, DLq + 1, DL2q + 1,... DL (p-1) q + 1 connected by the signal line SS1, A series of data lines DL2, DLq + 2, DL2q + 2,... Connected by another signal line SS2 can be written to the memory cell group selected by DL (p-1) q + 2. Therefore, it is not necessary to make the arithmetic circuit 40 wait for time for reading / writing, and high-speed data processing can be performed.

  Further, when there is a large gap between the pitch of the data lines of the memory cell array 10 and the width of one arithmetic circuit 40 on the layout of the chip 90, the pitch of the data lines is set when actually designing the chip 90. Although it is necessary to match the width of the arithmetic circuit 40, according to the semiconductor device of this embodiment, the data transfer circuit 30 can relax the data line pitch to q: 2. Therefore, the arithmetic circuit 40 and the memory cell array 10 can be laid out at a high density by setting this ratio according to the pitch.

  The semiconductor device of this embodiment can also be used as a normal memory. In this case, the control circuit 80 receives a control signal and a clock from the outside through the I / O port 81, and controls the sense amplifier 20, the decoder 70, and the serial access memories 50 and 60 according to the clock. The address is input from the input port 71, and data input / output is performed by the serial access memories 50 and 60 through the I / O ports 51 and 61. Therefore, it is possible to use the semiconductor device of this embodiment in a time-sharing manner such that the semiconductor device of this embodiment is usually dedicated to image processing and used as the main memory of the system as a normal memory when necessary. A smaller system configuration is possible by using the apparatus.

  Further, the area of the memory cell array 10 can be divided into a part that is used as a normal memory and a part that is used exclusively by the arithmetic circuit 40. For example, when applied to image processing, it may be desired to change the memory size used exclusively by the arithmetic circuit 40 by the system in order to cope with the nature of the image to be processed, the screen size, the display speed, and the like. In such a case, only the memory required for image processing out of the total memory size is used exclusively for the arithmetic circuit, image processing is performed, and the remaining portion is used as a normal memory for the main memory of the system.

  In this way, since one chip can be used for various applications, it is possible to save labor and time for chip design. In addition, since unnecessary memory can be used for the main memory of the system, a smaller system configuration is possible, and image processing can be performed in parallel with the semiconductor device of this embodiment and another processor, resulting in faster processing. Is possible.

  Further, when an image is displayed on a display or when image data stored in a memory is sequentially processed, data processing is performed on the entire memory cell array 10. Normally, when DRAM is used for a memory cell, refresh is required. However, in the above case, it is not necessary to perform refresh if the time for accessing the entire memory cell array is shorter than the information holding time of the memory cell. Therefore, in such a case, even if a DRAM is used for the memory cell, a refresh cycle is unnecessary, so that a higher speed operation can be expected and a refresh circuit is not necessary. The size can also be reduced.

Here, when configured with a switch _{S j k (j = 1~p,} k = 1~q) a MOS transistor used in the data transfer circuit 30 shown in FIG. 2, as an example switch S _{1 1} As shown in FIG. In FIG. 6, the switch S ₁₁ is composed of two MOS transistors TrR and TrW. In this configuration example, the signal line SS1 to control the switches S _{1 1,} it is necessary to be input to the gates of the MOS transistors, two signal lines SS1R and the signal line SS1W for lightpath connection for lead path connections It becomes. When the MOS transistor TrR is turned on by the signal line SS1R, the data line DL1 is connected to the read path R1, and when the MOS transistor TrW is turned on by the signal line SS1W, the data line DL1 is connected to the write path W1.

Further, in the semiconductor device of this embodiment, a differential amplifier is used as the sense amplifier 20, and the data line pairs DL1T, DL1B, DL2T, DL2B, each having two data lines DL1, DL2,. ...... In some cases, DLqT and DLqB may be used to transfer different signals. In such a case, the switch S _j k (j = 1 to p, k = 1 to q) used in the data transfer circuit 30 can be configured as shown in FIG. Note that FIG. 7 is shown a switch S _{1 1} as an example. In this case, the switch S ₁₁ is composed of four MOS transistors TrRT, TrWT, TrRB, TrWB. Corresponding to the data line pair DL1T, DL1B, the read path R1 and the write path W1 are also each two of the read path pair R1T, R1B and the write path pair W1T, W1B. Similarly to FIG. 6, the signal line SS1 has two signal lines SS1R for connecting the read path and signal line SS1W for connecting the write path. When both the MOS transistors TrRT and TrRB are turned on by the signal line SS1R, the data line pair DL1T and DL1B are connected to the corresponding read path pair R1T and R1B, respectively. In order to connect the data line pair DL1T and DL1B to the corresponding write path pair W1T and W1B, both the MOS transistors TrWT and TrWB may be turned on by the signal line SS1W.

Further, in the case where it is not necessary to make both the read path and the write path both, the switch S ₁₁ may be configured as shown in FIG. The configuration of FIG. 8 is suitable when the pitch of the data line pair is narrow and the transistor is difficult to arrange in the configuration example of FIG. Here, the case where the read path is paired and the write path is one is shown, but it goes without saying that one read path and one write path may be paired if necessary.

As described above, the case where the switch S _j k (j = 1 to p, k = 1 to q) is configured using nMOS transistors has been described as an example with reference to FIGS. 6 to 8. Needless to say, it may be used, or a CMOS transistor may be used.

  FIG. 4 is a block diagram of a basic circuit configuration showing another embodiment of the semiconductor device according to the present invention. For the sake of convenience, the same reference numerals are given to the same components as those shown in FIG. 1 of the first embodiment, and the detailed description thereof will be omitted. That is, in this embodiment, the configuration of the data transfer circuit and the control circuit that controls the data transfer circuit are added with p signal lines SSR1 to SSRp and p signal lines SSW1 to SSWp, and the read path and the write path are hierarchized. The difference is that.

Here, the detailed configuration of the data transfer circuit 32 of this embodiment is shown in FIG. The transfer circuit 32 shown in FIG. 5 is only a part of one of the plurality of data transfer circuits 32 in FIG. 4, and the block 1 of the data transfer circuit 30 shown in FIG. It corresponds to one (for example, the first block in FIG. 2 is shown). The data transfer circuit 32 is composed of a total of x small blocks, with q data lines being further divided into y small blocks, and the y data lines of each small block are signal lines from the control circuit 82. The signals SSR1 to SSRx are connected to one lead path R1 via one switch SR1 to SRx corresponding to each of the small blocks that are connected or released, and are connected to the signal lines SSW1 to SSWx. Each of them is connected to one write path W1 through one switch SW1 to SWx that performs the same operation. Accordingly, in each small block, a required data line is selected from xy (= q) data lines in each small block by the signals of the signal lines SS1 to SSy of the control circuit 82, and the corresponding switch S is selected. the ₁ 1 to S _X y is connected to the read path side connection line or the write path-side connection line, the selected data line is a signal line SSR1~SSRx or SSW1~SSWx signal, switch SR1~SRx or switch SW1~SWx is It can be closed and connected to the corresponding read path R1 or write path W1.

By hierarchizing the read path and the write path in this way, the control circuit 82 of the present embodiment newly needs to control a total of 2x signal lines SSR1 to SSRx and SSW1 to SSWx. There are advantages.
That is, in the configuration of the data transfer circuit 30 shown in FIG. 2, the number of data lines connected to one read path or write path is q, but the data transfer circuit 32 of this embodiment shown in FIG. The number of data lines connected to one read path or write path can be less than q. If the number of data lines is too large, the number of signal lines SS1 to SSq also increases and the capacity appearing on the read path and write path increases, resulting in a slow operation speed. In such a case, the data transfer circuit 32 is hierarchical. The control circuit 82 controls the signal lines SSR1 to SSRx and SSW1 to SSWx that are required in accordance with the conversion, and opens one of the switches SR1 to SRx or the switches SW1 to SWx corresponding to the small blocks that are not required to be connected. Since more data lines can be connected to one read path and write path without increasing the load capacity appearing on the write path, it is possible to speed up the read and write operations.

It will be briefly described that the data transfer circuit 32 having a hierarchical structure has a lighter load capacity than the data transfer circuit 30 of FIG. This constitutes the switch _S 1 1 to S _{x y,} the _S 1 1 to S _p q by two MOS transistors respectively, each switch SR1～SRx, a case where the a single MOS transistor, respectively SW1~SWx Example Explained.

The approximate load capacity when the data line DL1 is connected to the lead path R1 is estimated for each of the data transfer circuits 30 and 32.
When the source / drain capacitance of the MOS transistor and Cd, the load capacitance seen from the read path R1 in the case of the data transfer circuit 30 in FIG. 2, the switch S _{1 1} is in the OFF state is Cd × q. Note that Cd includes parasitic capacitance with the gate. When switch _{S 1} 1 is turned on, the further Cd is applied, the capacitance _{C FIG2} total becomes Cd × (q + 1). On the other hand, in the case of the data transfer circuit 32 of FIG. 5, the load capacity viewed from the lead path R1 is Cd × x when the switches SR1 to SRx are off. When the switch SR1 is turned on, joined by further Cd × (y + 1), further since Cd is applied to the switch _{S 1} 1 is turned on, the capacitance _{C fig5} total becomes Cd × (x + y + 2 ).

Here, taking the ratio of the capacitance C _FIG2 and the capacitance C _FIG5 and assuming that C _FIG2 / C _FIG5 = K is smaller than 1, that is, the case where the capacitance C _FIG5 is larger than the capacitance C _FIG2 , x and y are Since both are positive integers, the following equation is obtained.

従って、（１）式より（ｘ，ｙ）＝（２，３）または（３，２）のときだけ、容量Ｃ_ＦＩＧ５が容量Ｃ_ＦＩＧ２より大きくなる。言い替えると、ｘ，ｙがそれぞれ３以上になれば、データ転送回路３２の負荷容量Ｃ_ＦＩＧ５の方が小さくなる。しかも、ｘ，ｙが大きくなればなるほどＫの値は大きくなるため、データ転送回路３２の負荷容量はデータ転送回路３０に比べて小さくなることが分かる。

Therefore, only the capacitance _{C fig5} is greater than the capacitance _{C FIG2} when (1) from equation (x, y) = (2,3) or (3,2). In other words, if x and y are each 3 or more, the load capacitance C _FIG5 of the data transfer circuit 32 becomes smaller. In addition, it can be seen that the value of K increases as x and y increase, so that the load capacity of the data transfer circuit 32 becomes smaller than that of the data transfer circuit 30.

Further, in the data transfer circuit 32 of the present embodiment, the configuration in which the q data lines in the data transfer circuit 30 in FIG. 2 are divided into one block is divided into x small blocks of x. In the data transfer circuit 30, the number of signal lines for controlling the switches from the control circuit 80 is x × y (= q), whereas in the data transfer circuit 32, the number of signal lines from the control circuit 82 is y + 2x. is there. For this reason, by using the configuration of the data transfer circuit 32 of the present embodiment, it is possible to suppress an increase in the number of signal lines when the number of data lines increases. Since the range of selection of the number of data lines that can be connected to the write path and read path is expanded, the degree of freedom in design is improved. Since the switches S ₁ 1 to S _x y, the S ₁ 1 to S p _q when composed of two MOS transistors, respectively, it is necessary to signal line to each gate is input, the above-described control circuit The number of signal lines SS1 to SSy and SS1 to SSq from 80 and 82 is doubled.

  Similar to the first embodiment, the semiconductor device of this embodiment can also be used as a normal memory, and is usually used exclusively for image processing. When necessary, it is used as a main memory for the main memory of the system. It is also possible to change the usage by time division. Needless to say, the memory cell array region can be used separately from a portion used as a normal memory and a portion used exclusively in an arithmetic circuit.

In addition, the specific configuration by MOS transistors of the switches S ₁ 1 to S x _y for use in the data transfer circuit 32 shown in FIG. 5, in the same manner as in Example 1, one shown in FIGS. 6 to 8 The configuration may be used as necessary.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various design changes can be made without departing from the spirit of the present invention.

1 is a block diagram of a basic configuration showing an embodiment of a semiconductor device according to the present invention. FIG. 2 is a detailed circuit configuration diagram illustrating an example of a data transfer circuit used in the semiconductor device of FIG. 1. FIGS. 3A and 3B are diagrams for comparing and explaining the operation of the semiconductor device according to the present invention and the conventional operation. FIGS. 3A and 3B are timing diagrams showing an example of the operation of the semiconductor device of FIG. It is a block diagram of a basic composition showing another example of a semiconductor device concerning the present invention. FIG. 5 is a detailed circuit configuration diagram illustrating an example of a data transfer circuit used in the semiconductor device of FIG. 4. Is a circuit diagram showing an example of a specific configuration of the switches S _{1 1} to be used in the data transfer circuit of the semiconductor device according to the present invention. It is a circuit diagram showing another example of the switch S _{1 1} of a specific configuration example for use in the data transfer circuit of the semiconductor device according to the present invention. It is also a circuit configuration diagram showing another example of a specific configuration of the switches S _{1 1} to be used in the data transfer circuit of the semiconductor device according to the present invention.

Explanation of symbols

10: Memory cell array,
20 ... sense amplifier,
30: Data transfer circuit,
32. Data transfer circuit,
40. Arithmetic circuit,
50 ... Serial access memory,
51 ... I / O port,
60 ... serial access memory,
61 ... I / O port,
70: Decoder,
71: Input port,
80 ... control circuit,
81 ... I / O port,
82 ... control circuit,
90 ... silicon chip,
C _ij (i = 1 to n, j = 0 to m)... Memory cell
DLj, DLj '(j = 1 to m) ... data line,
DL1B, DL1T ... data lines,
WLi (i = 1 to n) ... word line,
S _j k (j = 1 to p, k = 1 to q)... Switch
SR1-SRx ... switch,
SW1 to SWy ... switch
SSj (j = 1 to q), SS1R, SS1W... Signal line,
SSR1 to SSRy ... signal line,
SSW1 to SSWx: signal lines,
TrR, TrRB, TrRT ... transistor,
TrW, TrWB, TrWT ... transistor,
Rj (j = 1 to p), R1B, R1T ... lead path,
Wj (j = 1 to p), W1B, W1T... Write path.

Claims (4)

A memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells;
An arithmetic circuit;
P read paths and P write paths connected to the arithmetic circuit;
Wherein the plurality of connecting P number of the bit lines to the P number of the read path, the plurality of one switch circuit for the bit line sac Chi other of P and is connected to the P number of light paths of the chip A semiconductor device integrated on the top,
The semiconductor device includes a read operation to transfer the data of P bits to the arithmetic circuit through the P number of read path from said memory cell array, an arithmetic operation for processing the data in the arithmetic circuit, the P number from said arithmetic circuit a of the operation result of the arithmetic operation through the light path can be executed, and the write operation for transfer to said memory cell array,
In the read operation, P bits of the plurality of bit lines are connected to the P read paths through the switch circuit from a memory cell selected by one word line of the plurality of word lines. Is an operation to read data,
The arithmetic operation is executed based on data read from the memory cell array by the read operation,
In the write operation, the P memory cells selected by the one word line that is the same as the read operation are transferred to the memory cells selected by the single word line via the switch circuit. And writing the calculation result of the calculation operation by connecting to the P light paths,
The semiconductor device performs the read operation and the write operation in parallel within a period selected by the one word line,
Each of the read operation, the arithmetic operation, and the write operation is performed within one clock cycle,
The semiconductor device performs the read operation on the first data in a first clock cycle, and an arithmetic operation based on the first data in a second clock cycle following the first clock cycle, and the first data and Performs the read operation on different second data, and in the third clock cycle following the second clock cycle, the write operation on the calculation result based on the first data, the calculation operation based on the second data, and Performing the read operation on third data different from the first and second data;
The semiconductor device according to claim 1, wherein the P bit lines subject to the read operation in the first clock cycle and the P bit lines subject to the write operation in the third clock cycle are the same bit line . A first serial access memory connected to the memory cell array for inputting / outputting data via an I / O port;
2. The semiconductor device according to claim 1, wherein the first serial access memory sequentially reads out data sequentially from the memory cell array and outputs the data to image display means connected to the outside. An address decoder;
2. The semiconductor device according to claim 1, wherein the address decoder designates an address on the memory cell array as a result of decoding the address. A second serial access memory connected to the arithmetic circuit;
4. The calculation operation according to claim 1, wherein the arithmetic operation is executed between data read from the memory cell array by the read operation and data given to the second serial access memory. The semiconductor device according to 1 .

Images