JP3604482B2 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
With the increase in density and miniaturization of semiconductor devices, introduction of a trench isolation technique as an element isolation technique has been attempted.
[0003]
As a method of flattening a trench pattern accompanying such trench isolation, a resist which is a flattening material is coated so as to fill a step of an insulating film deposited on a substrate on which the trench pattern is formed, and a resist is etched over the entire surface. There is an etch back method, or a chemical mechanical polishing method (CMP method) in which an insulating film deposited on a substrate on which a trench pattern is formed is mechanically shaved using a chemical polishing agent, a pad, or the like to flatten the insulating film. .
[0004]
In the planarization by the resist etch-back method, the planarizing material must be affected by the step of the insulating film, and the pattern dependence of the planarity is more remarkable than the CMP method. Is a technology that has attracted attention as a technology for completely planarizing an insulating film.
[0005]
Hereinafter, a conventional example using the CMP method will be described with reference to FIG.
[0006]
First, as shown in FIG. 16A, a trench pattern 21 is formed on a silicon substrate 11 by dry etching using an active region forming mask 51.
[0007]
Next, as shown in FIG. 16B, a silicon oxide film 23 is deposited on the trench pattern 21 as an insulating film. Here, the silicon oxide film 23 needs to be deposited thicker than the depth of the trench pattern 21.
[0008]
Then, as shown in FIG. 16C, the silicon oxide film 23 is polished by the CMP method using the chemical polishing material and the polishing pad 61. This polishing is continued until the silicon substrate surface is exposed, and at the end of the polishing, the state shown in FIG. 16D is obtained.
[0009]
Next, as shown in FIG. 16E, a wiring 41 is formed with a transistor including the gate electrode 31 and the source / drain 32 by a known technique.
[0010]
[Problems to be solved by the invention]
However, in such a conventional example, as shown in FIG. 16C, when the width of the trench pattern 21 is large, the polishing pad 61 is pressed against the concave portion on the surface of the silicon oxide film. Therefore, not only the projections but also the depressions on the surface of the silicon oxide film are polished, and after polishing, the surface of the silicon oxide film 22 at the center is dented as shown in FIG. In particular, when the width of the trench pattern is as large as several hundred μm, the silicon oxide film used for embedding the trench pattern may be completely polished.
[0011]
As described above, since the steps are formed even after the CMP polishing, the depth of focus cannot be secured in the lithography process, which is a problem in miniaturizing the element.
[0012]
On the other hand, a configuration shown in FIG. 17 in which the semiconductor device described in JP-A-3-278533 is applied to a MOS device can be considered. In FIG. 17, parts corresponding to those in FIG. 16 are denoted by the same reference numerals.
[0013]
The device shown in FIG. 17 forms the trench pattern 21 around the active region 33 and forms the same structure as the periphery of the active region below the wiring 41, that is, the trench pattern 25 having the same depth and width. It is. Moreover, the width of the trench 25 is smaller than the width of the wiring 41, and a silicon oxide film 75 is formed as an insulating film to insulate the wiring 41 from the silicon substrate 11. Thus, by forming the trench pattern 25 under the wiring, the effect of reducing the capacitance between the wiring 41 and the silicon substrate 11 can be obtained.
[0014]
In the conventional example shown in FIG. 17, the width of the trench pattern is the same everywhere, and a trench pattern having a wide width as in the conventional example of FIG. 16 does not exist. Can be prevented from being polished.
[0015]
However, in the planarization technique by the CMP method, the polishing time becomes longer as the surface area of the convex portion becomes larger. Therefore, in the conventional example of FIG. 17, the insulating film in the trench pattern in the region where the surface area of the convex portion is small is formed. It will be polished more than necessary, and the flatness of the surface will be impaired.
[0016]
If there is no misalignment of the semiconductor mask, the cross-sectional structure of the semiconductor device is as shown in FIG. 18A, and the capacitance between the wiring 41 and the substrate 11 is minimized. As a result, as shown in FIG. 18B, the rate at which the trench pattern 25 does not exist under the wiring due to misalignment of the mask increases, which causes a problem that the capacitance increases. This is because it is difficult to improve the misalignment accuracy of the semiconductor mask in the lithography process with respect to the miniaturization of the processing size. Misalignment occurs.
[0017]
The present invention has been made in view of the above technical problems, and has a main object to solve the problem of the depth of focus in a lithography process by increasing the flatness of a trench by a CMP method or an etch-back method, Still another object is to prevent an increase in capacitance between the wiring and the substrate due to misalignment of the semiconductor mask.
[0018]
[Means for Solving the Problems]
The present invention is directed to a semiconductor device in which elements are formed in a plurality of element regions each separated by a trench pattern, in a region other than the element region, and in a region excluding the trench pattern, a groove or a hole is formed. A dummy pattern that is an array pattern is formed, and the convex sections defined by the dummy pattern are present with regular repetition, the distance between adjacent convex sections is 10 μm or less, andPer element region in all of the plurality of element regionsThe ratio between the average area and the area of the basic unit of the repetition of the protrusion is 0.5 or more and 2 or less, and the trench pattern and the dummy pattern are buried with an insulating film.
[0019]
According to the semiconductor device of the present invention, a dummy pattern which is an arrangement pattern of regularly repeated grooves or holes is provided outside the element region, and the projections defined by the dummy pattern are formed in a regularly repeated pattern. Since the projections are arranged so that the projections are uniformly distributed, the pattern dependence of the flatness of the trench is reduced, and the flatness of the trench by the CMP method or the etch-back method can be improved. Thus, the problem of the depth of focus in the lithography process can be solved.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
The present invention according to claim 1, wherein in a semiconductor device in which elements are respectively formed in a plurality of element regions separated by a trench pattern, in a region other than the element region and in a region excluding the trench pattern. A dummy pattern, which is an array pattern of grooves or holes, is formed, and the convex sections defined by the dummy pattern are present with regular repetition, and the distance between adjacent convex sections is 10 μm or less. AndPer element region in all of the plurality of element regionsThe ratio between the average area and the area of the basic unit of the repetition of the convex portion is 0.5 or more and 2 or less, and the trench pattern and the dummy pattern are configured to be buried with an insulating film. The dummy pattern can reduce the pattern dependency of the flatness of the trench and increase the flatness of the trench by the CMP method or the etch-back method, thereby solving the problem of the depth of focus in the lithography process. it can.
[0021]
Claim2 notesThe invention described above isIn a semiconductor device in which an element is formed in each of a plurality of element regions separated by a trench pattern, an array pattern of grooves or holes is formed in a region other than the element region and excluding the trench pattern. A dummy pattern is formed, and the convex sections defined by the dummy pattern are present with regular repetition, the distance between adjacent convex sections is 10 μm or less, and the plurality of The ratio of the average area per element region of the element with the highest frequency of formation to the area of the basic unit of the repetition of the convex portion is 0. . 5 or more and 2 or less, wherein the trench pattern and the dummy pattern are configured to be buried with an insulating film.The required element area isThe plurality of element regionsMostIs also an element region with a high frequency of formation,The dummy pattern corresponds to the trench pattern for element isolation, and the flatness of the trench can be further improved.
[0022]
Claim3In the present invention described above, the dummy pattern is formed in a regular lattice shape, and the flatness of the trench can be improved by the dummy pattern having a relatively simple configuration.
[0023]
Claim4According to the present invention, a trench pattern for well isolation is formed at a boundary between an n-well and a p-well in a region where the dummy pattern is formed, and the trench pattern for well isolation is The structure is buried with a film, whereby the n-well and the p-well are completely electrically separated from each other, diffusion of impurities can be prevented, and device characteristics are improved.
[0024]
Claim5According to the present invention, the under-wiring trench pattern is formed in a region where the dummy pattern is formed, and the under-wiring trench pattern is buried with the insulating film. Wiring narrower than the trench pattern for under wiring is formed, and the capacitance between the wiring and the substrate can be reduced, and the capacitance between the wiring and the substrate due to misalignment of the semiconductor mask can be prevented. it can.According to a sixth aspect of the present invention, the insulating film is a laminated film. For example, by using a laminated film having excellent filling characteristics such as polysilicon, the element can be miniaturized.
[0025]
According to a seventh aspect of the present invention, the insulating film is a laminated film. For example, by using a laminated film having excellent filling characteristics such as polysilicon, the element can be miniaturized.
[0026]
According to the present invention, a mask pattern for simultaneously forming at least two patterns of a trench pattern surrounding each of the peripheral portions of the plurality of element regions and a dummy pattern which is an array pattern of grooves or holes is formed. A mask pattern forming step, an etching step of simultaneously forming at least the trench pattern and the dummy pattern by dry etching using the mask pattern as a mask, an insulating film depositing step of depositing an insulating film, and a chemical mechanical polishing method. A polishing step of polishing and flattening the insulating film; and an element forming step of forming an element in the element region,
The dummy pattern is a region other than the element region and is formed in a region excluding the trench pattern, and the dummy pattern has a regular section formed by the dummy pattern. And the distance between adjacent convex portions is 10 μm or less,In addition, the ratio of the average area per element region in all the element regions of the plurality of element regions to the area of the basic unit of the repetition of the projection is 0. . 5 or more and 2 or less, and the required element region is the entire element region of the plurality of element regions, and the dummy pattern corresponds to the trench pattern for element isolation. Can further enhance the flatness of the trench.
[0027]
In the method of manufacturing a semiconductor device according to the ninth aspect of the present invention, at least two patterns, that is, a trench pattern surrounding each of a plurality of element regions and a dummy pattern which is an array pattern of grooves or holes are simultaneously formed. A mask pattern forming step of forming a mask pattern, an etching step of simultaneously forming at least the trench pattern and the dummy pattern by dry etching using the mask pattern as a mask, and an insulating film depositing step of depositing an insulating film,A polishing step of polishing and flattening the insulating film by a chemical mechanical polishing method, and an element forming step of forming an element in the element region, wherein the dummy pattern is a region other than the element region,In addition, the dummy pattern is formed in a region excluding the trench pattern, and the dummy pattern has convex portions defined and formed by the dummy pattern in a repetition having regularity, and a distance between adjacent convex portions. Is 10 μm or less, andThe ratio between the average area per element region of the element with the highest frequency of formation among the plurality of element regions and the area of the basic unit of the repetition of the convex portion is 0. . The dummy pattern is in accordance with the trench pattern for element isolation, and the flatness of the trench by the CMP method or the etch-back method can be further improved.
[0028]
Claim10The method of manufacturing a semiconductor device of the present invention describedA mask pattern forming step of forming a mask pattern for simultaneously forming at least two patterns of a trench pattern each surrounding a periphery of a plurality of element regions and a dummy pattern which is an array pattern of grooves or holes; An etching step of simultaneously forming at least the trench pattern and the dummy pattern by dry etching using a mask as a mask, an insulating film depositing step of depositing an insulating film, a planarizing material forming step of forming a planarizing material, and dry etching. An etch back step of etching back the insulating film and the planarizing material by technology, and an element forming step of forming an element in the element region, wherein the dummy pattern is a region other than the element region. And formed in a region excluding the trench pattern. In the dummy pattern, the projections defined by the dummy pattern are present in a repetition having regularity, the distance between adjacent projections is 10 μm or less, and the The ratio of the average area per element region in all the element regions to the area of the basic unit of the repetition of the projection is 0. . 5 or more and 2 or less, and the required element region is the entire element region of the plurality of element regions, and the dummy pattern corresponds to the trench pattern for element isolation. Can further enhance the flatness of the trench.
[0029]
Claim11In the method for manufacturing a semiconductor according to the present invention, the mask pattern in the mask pattern forming step simultaneously forms a trench pattern for separating an n-well and a p-well in a region where the dummy pattern is formed. The etching step is to simultaneously form at least the trench pattern, the dummy pattern and the well separating trench pattern by dry etching, whereby the n-well and the p-well are formed. It is electrically separated completely, diffusion of impurities can be prevented, and device characteristics are improved.
[0030]
Claim12In the method for manufacturing a semiconductor device according to the present invention, the mask pattern in the mask pattern forming step is for simultaneously forming an under-wiring trench pattern in a region where the dummy pattern is formed, In the etching step, at least the trench pattern, the dummy pattern, and the trench pattern for under-wiring are simultaneously formed by dry etching, and the under-wiring trench pattern is formed on the insulating film in which the under-wiring trench pattern is buried. And a wiring forming step of forming a wiring having a width smaller than the width of the trench pattern for use. This makes it possible to reduce the capacitance between the wiring and the substrate, and to reduce the misalignment of the semiconductor mask between the wiring and the substrate. Can be prevented from increasing.
[0031]
ClaimThirteenThe method for manufacturing a semiconductor device according to the present invention includes a stacked film forming step of forming a stacked film made of different films in the trench pattern and the dummy pattern. By using the laminated film, the element can be miniaturized.
[0032]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0033]
(Embodiment 1)
FIG. 1 is a plan view of a semiconductor device according to one embodiment of the present invention as viewed from above, FIG. 2 is a plan view of a main part of FIG. 1 from which a dummy pattern is removed, and FIG. FIG. 3 is an enlarged structural cross-sectional view and a plan view showing a main part of FIG. 2.
[0034]
In this embodiment, in a region outside the active region 33 as an element region formed by the gate electrode 32 and the source / drain region 32, a wiring 41, a trench pattern 21 for element isolation, and a trench pattern 25, a well separating trench pattern 26 for separating the n-well 34 and the p-well 35, and a dummy pattern 27 in which a groove arrangement pattern is formed in a lattice pattern, are formed by a silicon oxide film. 22 buried. Hereinafter, each configuration will be specifically described.
[0035]
The trench pattern 21 around the active region 33 has a certain width so as to surround the active region 33 in a ring shape, and is buried with the silicon oxide film 22. The trench pattern 21 functions as element isolation. Therefore, the width of the trench pattern 21 only needs to be equal to or larger than the minimum width capable of functioning as element isolation. Needless to say, the minimum width is determined by the generation and characteristics of the semiconductor device and the semiconductor manufacturing process conditions.
[0036]
On the other hand, the maximum width is determined by a limit at which no digging occurs by polishing by the CMP method. Alternatively, the wiring formed on the trench pattern is determined within a range where there is no problem in the depth of focus even if the trench is dug. It goes without saying that the maximum width varies depending on the polishing conditions in the CMP method, for example, the pressure, the number of revolutions, the pad material, the type of the abrasive, and the like.
[0037]
The dummy pattern 27 is for reducing the pattern dependence of the planarization of the trench by the CMP method or the etch-back method, as shown in FIG. In this embodiment, in order to make the area density of each of them substantially constant, that is, to make the distribution of the convex portions uniform, the lattice pattern is regularly arranged. The distance between adjacent island patterns 36, which are convex portions defined by the above, is set to 10 μm or less, which is a distance at which no digging occurs by polishing by the CMP method.
[0038]
In general, in the planarization technique by the CMP method, the polishing rate increases as the area of the convex portion on the surface decreases. Since the time required for polishing becomes longer as the pattern constituting the area of the convex portion on the surface becomes longer, the insulating film in the trench pattern is polished more than necessary in the region where the convex portion area is small, The flatness of the surface will be impaired.
[0039]
Therefore, considering the application of the CMP method to the planarization of the trench pattern in the present invention, one area of the rectangular island pattern 36 which is a basic unit of repetition defined by the dummy pattern 27 is the most repetitive. It is desirable to select an element region of a semiconductor element that is often used, and make the area substantially equal to the area of the source / drain region of the semiconductor element. In order to further reduce the pattern dependence of the flatness, it is preferable to keep the required pattern area density per unit area substantially constant.
[0040]
However, in the logic LSI, it is difficult to keep the pattern area density per unit area constant because the size of the semiconductor elements in the same chip is not constant and the arrangement is not constant. Therefore, the average area per source / drain region and the area of one island pattern, which is a basic unit for repeating the dummy pattern, are made substantially constant.
[0041]
On the other hand, the above-described pattern dependence of the flatness in the CMP method varies depending on the polishing conditions of the CMP, for example, pressure, rotation speed, pad material, type of abrasive, and the like. It is possible to give a width to the ratio of the area of the island pattern and the area of one of the island-shaped patterns defined by the dummy pattern. Actually, there is no problem if the ratio of the area is 0.5 or more and 2 or less.
[0042]
That is, in the present invention, the ratio between the average area of the element region and the area of the basic unit of repeating the convex portion by the dummy pattern is set to 0.5 or more and 2 or less. The ratio between the average area of the region 32 and one area of the island pattern 36 may be set to 0.5 or more and 2 or less.
[0043]
Note that instead of the average area of all the element regions, the average area of the element region of the element that is most frequently formed may be used.
[0044]
In a semiconductor memory, since the memory cell portion occupies the largest area in a semiconductor chip, the area of the island-shaped pattern is set to be approximately the same as the source / drain region portion forming the memory cell. The pattern area density per area becomes almost constant.
[0045]
In the present embodiment, the n-well 34 and the p-well 35 are electrically separated by the presence of the trench pattern 26, and the width of the trench pattern 26 at the boundary between the n-well 34 and the p-well 35 Should be at least the minimum width that can function as inter-well separation. Needless to say, the minimum width is determined by the generation and characteristics of the semiconductor device and the semiconductor manufacturing process conditions. On the other hand, the maximum width is determined by a limit at which no digging occurs by polishing by the CMP method. Alternatively, the wiring formed on the trench pattern is determined within a range where there is no problem in the depth of focus even if the digging occurs. It goes without saying that the maximum width varies depending on the polishing conditions in the CMP method, for example, the pressure, the number of revolutions, the material of the pad, the type of the abrasive, and the like.
[0046]
When the wiring 41 and the silicon oxide film 22 are in direct contact, the trench pattern 25 below the wiring 41 functions as an insulator with respect to the silicon substrate. Therefore, as a feature of the trench pattern 25, as shown in the structural sectional view of the semiconductor device in FIG. 3A, misalignment of the mask between the wiring pattern 41 and the trench pattern 25, the overlap capacitance between the wiring 41 and the silicon substrate. In consideration of the above, the width of the trench pattern 25 is wider than the width of the wiring 41.
[0047]
The alignment margin between the wiring pattern 41 and the trench pattern 25 only needs to have a width equal to or greater than the maximum mask misalignment amount on one side. That is, if the width of the trench pattern 25 is {(wiring width) + (twice the maximum misalignment amount)} or more, even if misalignment occurs as shown in FIG. I will not. Needless to say, the alignment margin also changes depending on the semiconductor manufacturing process conditions and the like.
[0048]
In this embodiment, a silicon oxide film is used as a film for filling the trench pattern, but another insulating film such as a silicon nitride film may be used. Further, different films such as a CVD oxide film and a thermal oxide film may be laminated and used.
[0049]
The semiconductor device having the above configuration has the following functions and effects.
[0050]
In other words, the configuration in which there is a dummy pattern having a regularity such that the distribution of the projections is uniform and the pattern area density is constant is present. The effect of reducing the pattern dependency and reducing the amount of over-etching during polishing of the silicon oxide film 22 used for filling can be obtained.
[0051]
Further, the pattern dependency of the flatness can be reduced by flattening using a dry etching technique such as a resist etch-back method instead of the CMP method. By reducing the pattern dependence of the flatness, the trench can be completely flattened, and the problem of securing the depth of focus in the lithography process can be solved.
[0052]
Further, with the configuration in which the trench pattern 26 exists at the boundary between the n-well and the p-well, the n-well and the p-well are completely electrically separated from each other, and diffusion of impurities can be prevented. Can be achieved.
[0053]
Also, the trench pattern 25 under the wiring is wider than the wiring width in consideration of misalignment of the semiconductor mask and the overlap capacitance between the wiring and the silicon substrate, so that even if there is no insulating film between the wiring and the trench pattern. There is no contact between the wiring and the silicon substrate due to misalignment. Further, unlike the conventional example, the trench pattern does not exist immediately below the wiring due to misalignment, and the capacitance does not increase.
[0054]
In this embodiment, the dummy pattern 27 is an array pattern of grooves, and the convex portions are formed in an island shape and in a lattice shape. As long as the area ratio satisfies the above condition, the shape and arrangement of the dummy patterns are not limited. In addition, the present invention can be similarly implemented in a state where the unevenness is reversed, that is, when the dummy pattern 27 is an array pattern of holes scattered in a hole shape. In this case, the convex sections defined by the dummy patterns are continuous, but the basic unit of repetition is the L-shaped portion A shown in FIG.
[0055]
(Embodiment 2)
FIG. 5 is a structural sectional view of a main part of a semiconductor device according to a second embodiment of the present invention, and portions corresponding to the above-described first embodiment are denoted by the same reference numerals.
[0056]
In the above-described first embodiment, a silicon oxide film is used for embedding a trench pattern. However, in the second embodiment, polysilicon is used instead of a silicon oxide film.
[0057]
That is, the trench patterns 21, 25, 26 and the dummy pattern 27 are buried with the polysilicon 72 and the silicon oxide film 71, and the upper portion of the trench pattern is covered with the silicon oxide film 73. There is no direct contact. Other configurations are the same as those in the first embodiment.
[0058]
The reason why the silicon oxide films 71 and 73 are present around the polysilicon 72 is to prevent deterioration of the characteristics of the device due to diffusion of impurities in the polysilicon and to enhance insulation.
[0059]
Further, polysilicon has better filling characteristics than a silicon oxide film, and can fill grooves having a higher aspect ratio. Therefore, by using polysilicon for embedding the trench pattern, the width of the trench pattern can be reduced, and the miniaturization of the element can be further promoted.
[0060]
(Embodiment 3)
FIG. 6 is a sectional view of a main part of a semiconductor device according to the third embodiment of the present invention, and portions corresponding to the above-described first embodiment are denoted by the same reference numerals.
[0061]
In the third embodiment, an insulating film layer exists between a wiring 42 and a semiconductor substrate including a trench pattern and an active region 33.
[0062]
That is, the silicon oxide film 74 is formed between the semiconductor substrate 11 and the wiring 42 as an insulating film. Other configurations are the same as those in the first embodiment.
[0063]
In the third embodiment, since the silicon oxide film layer 74 is formed on the semiconductor substrate 11 before forming the wiring, the wiring 42 is formed on the active region 33 without bypassing the periphery of the active region as compared with the above-described embodiment. Can be traversed, and an effect that high integration of elements can be achieved is produced.
[0064]
(Embodiment 4)
Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings.
[0065]
First, a method for manufacturing a semiconductor mask required to obtain a semiconductor device will be described with reference to FIGS.
[0066]
In this embodiment, a trench pattern is automatically formed using a computer by using an active region forming mask, a gate electrode pattern forming mask, a wiring pattern forming mask, an n-well forming mask, and grid-like dummy pattern forming data. A mask is manufactured so that all the trench patterns can be formed at once with one semiconductor mask.
[0067]
The trench pattern formation mask is formed by three semiconductor mask data of the active region formation mask of FIG. 7A, the gate electrode pattern formation mask of FIG. 7B, and the wiring pattern formation mask of FIG. 7C. It is obtained automatically by computer processing in the following procedure.
[0068]
First, as a procedure 1, as shown in FIG. 8A, a first intermediate mask region 102 is formed by enlarging the active region 101 graphically by a certain width. At this time, the enlarged width is set to be equal to or larger than the minimum width at which element isolation is possible, and the maximum width is set to be equal to or smaller than a limit at which digging occurs by polishing by the CMP method. Needless to say, the minimum width is determined by the generation and characteristics of the semiconductor device and the semiconductor manufacturing process conditions.
[0069]
Next, as a procedure 2, as shown in FIG. 8B, the second intermediate mask region 202 is formed by enlarging the gate electrode pattern 201 graphically with a constant width. The enlargement width at this time is set to be equal to or larger than the maximum misalignment amount of the mask that can occur.
[0070]
As a procedure 3, as shown in FIG. 8C, the third intermediate mask region 302 is formed by enlarging the wiring pattern 301 graphically with a constant width. The enlargement width at this time is set to be equal to or larger than the maximum misalignment amount of the mask that can occur.
[0071]
As a procedure 4, as shown in FIG. 9A, the active region 101 is simply inverted graphically to form a fourth intermediate mask region 103.
[0072]
It should be noted that the execution order of the procedure 1, the procedure 2, the procedure 3, and the procedure 4 does not matter.
[0073]
Next, as a procedure 5, as shown in FIG. 9B, the logical sum of the first intermediate mask area 102, the second intermediate mask area 202, and the third intermediate mask area 302 is calculated, and the fifth An intermediate mask area 401 is formed.
[0074]
Next, as a procedure 6, as shown in FIG. 10B, the sixth intermediate mask region 502 is formed by enlarging the n-well region 501 of FIG.
[0075]
As a procedure 7, as shown in FIG. 11A, from the sixth intermediate mask region 502, a seventh intermediate mask region 503 obtained by reducing the n-well region 501 graphically by a constant width is obtained. Then, an eighth intermediate mask region 504 is formed.
[0076]
Here, the enlarged width and the reduced width in FIGS. 10B and 11A are equal to or larger than the minimum width at which the n-well and the p-well can be electrically separated, and the maximum width is polishing by the CMP method. Is set below the limit at which digging occurs. Needless to say, the minimum width is determined by the generation and characteristics of the semiconductor device and the semiconductor manufacturing process conditions.
[0077]
As a procedure 8, as shown in FIG. 11B, the logical sum of the fifth intermediate mask area 401 and the eighth intermediate mask area 504 formed in FIG. 411 are formed.
[0078]
Next, as a procedure 9, as shown in FIG. 12A, mask data of a grid-like dummy pattern 601 in which the dummy regions 602 are arranged in a grid pattern is prepared. Here, the area covered with oblique lines is the area graphically enclosed. A is a basic unit of repetition of the other embodiments described above. The pattern area density of the dummy pattern is constant in order to prevent the CMP polishing rate from being dependent on the pattern. Further, it is desirable that the area of the dummy region 602, that is, the area of the island-shaped pattern serving as a protrusion is the same as the area of the active region pattern 101 shown in FIG.
[0079]
In step 10, as shown in FIG. 12B, the ninth intermediate mask area 411 formed in FIG. 11B and the grid-like dummy pattern 601 are logically ORed to form the tenth intermediate mask area 421. Form.
[0080]
Next, as a procedure 11, as shown in FIG. 13A, the logical product of the fourth intermediate mask area 103 and the twelfth intermediate mask area 421 formed in FIG. A region 422 is formed.
[0081]
As step 12, as shown in FIG. 13B, the eleventh intermediate mask region 422 is simply inverted graphically. The semiconductor mask data obtained at this time serves as a trench pattern forming mask, and the pattern 424, which is a blank portion in the drawing, serves as a trench pattern forming portion.
[0082]
Here, the description has been made on the assumption that mask data for forming an n-well is used. However, the present invention can be similarly implemented using mask data for forming a p-well.
[0083]
Note that the method of manufacturing a semiconductor mask described here is an example in which a mask is manufactured in accordance with a specific mask processing logical expression, and if given by a similar logical expression, the same configuration can be obtained even if the procedure is changed. A semiconductor mask can be manufactured.
[0084]
Using the semiconductor mask manufactured as described above, an actual manufacturing process of a semiconductor device will be described.
[0085]
First, as shown in FIG. 14A, a resist pattern 81 is formed on the silicon substrate 11 using the trench pattern forming mask manufactured as described above, and the trench patterns 21 and 25 and the dummy pattern are formed by dry etching. A pattern 27 and a well isolation trench pattern 26 are formed.
[0086]
The trench pattern forming mask includes an element isolation trench pattern 21 disposed in the periphery of the active region, a trench pattern 25 disposed under the wiring, and a well isolation trench pattern formed at the boundary between the n-well and the p-well. 26, a desired trench pattern is formed at one time because all of the dummy patterns 27, which are lattice-like trench patterns, are drawn. The trench pattern 25 formed at this time is wider than the width of the wiring 41 formed later.
[0087]
Next, as shown in FIG. 14B, a silicon oxide film 23 is deposited as an insulating film on the trench patterns 21, 25, 27. Here, the silicon oxide film 23 needs to be deposited thicker than the depth of the trench pattern.
[0088]
Then, as shown in FIG. 14C, the silicon oxide film 23 is polished by the CMP method. Polishing is continued until the silicon substrate surface is exposed, and a state shown in FIG.
[0089]
Next, as shown in FIG. 14E, a transistor including the gate electrode 31 and the source / drain region 32 and the wiring 41 are formed by a known technique to obtain the semiconductor device of the above-described embodiment. is there.
[0090]
According to the manufacturing method of this embodiment, since the lattice-shaped dummy patterns are arranged so that the pattern area density is substantially constant, the recess of the trench pattern is dug down by the CMP method as in the conventional example. In addition to preventing such pattern dependence of the flatness, the pattern dependence of the polishing rate can be prevented, and the amount of over-etching during polishing of the insulating film used for filling can be reduced. No surface condition is obtained. Therefore, the depth of focus in the lithography process can be sufficiently ensured, and the miniaturization of the device can be facilitated.
[0091]
The trench pattern forming mask in this embodiment is automatically produced from mask data such as an active region forming mask, a gate electrode pattern forming mask, a wiring pattern forming mask, a well forming mask, and grid-like dummy pattern data. Therefore, it is not necessary to newly input a mask for forming a trench pattern. Therefore, the present invention can be directly applied to the semiconductor mask data that has been conventionally owned, and past assets can be effectively used.
[0092]
Further, in manufacturing the semiconductor device of the present invention, it is only necessary to replace the conventional active region forming mask with a trench pattern forming mask, and there is no additional process.
[0093]
As for the method of manufacturing the semiconductor device of the embodiment shown in FIG. 5, a stacked film deposition process of polysilicon and a silicon oxide film and an oxide film formation process on polysilicon are added to the manufacturing method of this embodiment. The method of manufacturing the semiconductor device according to the embodiment shown in FIG. 6 can be performed only by adding an insulating film deposition step to the method of manufacturing the semiconductor device of this embodiment. An effect similar to that of this embodiment can be obtained.
[0094]
(Embodiment 5)
Next, a method for manufacturing a semiconductor device according to another embodiment of the present invention will be described with reference to the drawings.
[0095]
First, a semiconductor mask, that is, a trench pattern forming mask is manufactured in the same manner as in the fourth embodiment.
[0096]
Next, as shown in FIG. 15A, a resist pattern 81 is formed on the silicon substrate 11 using the formed trench pattern forming mask, and the trench patterns 21 and 25, the dummy pattern 27, and the well are formed by dry etching. An isolation trench pattern 26 is formed. The trench pattern forming mask includes an element isolation trench pattern 21 disposed in the periphery of the active region, a trench pattern 25 disposed under the wiring, and a well isolation trench pattern formed at the boundary between the n-well and the p-well. 26, a desired trench pattern is formed at one time because all of the dummy patterns 27, which are lattice-like trench patterns, are drawn. The trench pattern 25 formed at this time is wider than the width of the wiring 41 formed later.
[0097]
Next, as shown in FIG. 15B, a silicon oxide film 23 is deposited as an insulating film on the trench patterns 21, 25, 26, 27. Here, the silicon oxide film 23 needs to be deposited thicker than the depth of the trench pattern.
[0098]
Then, as shown in FIG. 15C, a flattening resist 82 is applied to flatten the surface. If the maximum width of the trench pattern is 1 to 1.5 μm, complete planarization can be achieved only by the conditions for depositing a silicon oxide film and applying the resist. If there is a trench pattern having a large width of 2 μm or more, a resist block may be formed in a concave portion on the surface before applying a flattening resist.
[0099]
Next, as shown in FIG. 15D, the silicon oxide film 23 and the flattening resist 82 are etched back using a dry etching technique in which the etching rates are equal.
[0100]
Then, as shown in FIG. 15E, a transistor including the gate electrode 31 and the source / drain region 32 and the wiring 41 are formed by a known technique to obtain the semiconductor device of the above-described embodiment. is there.
[0101]
According to the manufacturing method of this embodiment, since the lattice-shaped dummy patterns are arranged so that the pattern area density is almost constant, the thickness variation of the silicon oxide film 23 and the planarization resist 82 is eliminated. In addition, since the pattern aperture ratio per unit area is constant within the semiconductor substrate surface, the dependence of the etching rate on the pattern aperture ratio can be prevented.
[0102]
Therefore, even in an etch-back method using a dry etching technique, complete planarization without pattern dependence can be realized, a sufficient depth of focus can be secured in a lithography process, and miniaturization of elements can be facilitated.
[0103]
As for the method of manufacturing the semiconductor device of the embodiment shown in FIG. 5, a stacked film deposition process of polysilicon and a silicon oxide film and an oxide film formation process on polysilicon are added to the manufacturing method of this embodiment. The method of manufacturing the semiconductor device according to the embodiment shown in FIG. 6 can be performed only by adding an insulating film deposition step to the method of manufacturing the semiconductor device of this embodiment. An effect similar to that of this embodiment can be obtained.
[0104]
In each of the above-described embodiments, the description has been made by applying the present invention to a MOS transistor. However, the present invention is not limited to the MOS transistor, but may be applied to other elements.
[0105]
【The invention's effect】
As described above, in the present invention, the pattern dependency of the polishing rate is reduced by providing a dummy pattern that is a repetitive pattern of regularity such that the distribution of the protrusions becomes uniform and the pattern area density becomes almost constant. It is possible to form a trench pattern that has been completely flattened with no steps on the surface, and to improve the depth of focus in the lithography process and contribute to miniaturization of the element. Even when the technology is applied, complete flattening without pattern dependence can be realized.
[0106]
Also, in the trench pattern under the wiring, even if misalignment of the semiconductor mask occurs, the trench pattern always exists under the wiring, so that the parasitic capacitance between the wiring and the substrate can be reduced, and the speed of the semiconductor device can be reduced. It can also contribute to the development.
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a plan view of a main part of the semiconductor device of FIG. 1 excluding a dummy pattern.
3 is an enlarged structural sectional view and a plan view of a main part of FIG. 2;
FIG. 4 is a structural sectional view showing misalignment of a semiconductor mask.
FIG. 5 is a structural sectional view of a semiconductor device according to a second embodiment of the present invention;
FIG. 6 is a structural sectional view of a semiconductor device according to a third embodiment of the present invention;
FIG. 7 is a diagram illustrating a method for manufacturing a semiconductor mask in a method for manufacturing a semiconductor device according to the present invention.
FIG. 8 is a diagram illustrating a method for manufacturing a semiconductor mask in a method for manufacturing a semiconductor device according to the present invention.
FIG. 9 is a diagram illustrating a method of forming a semiconductor mask in a method of manufacturing a semiconductor device according to the present invention.
FIG. 10 is a diagram illustrating a method of forming a semiconductor mask in a method of manufacturing a semiconductor device according to the present invention.
FIG. 11 is a diagram illustrating a method of forming a semiconductor mask in a method of manufacturing a semiconductor device according to the present invention.
FIG. 12 is a diagram illustrating a method of forming a semiconductor mask in a method of manufacturing a semiconductor device according to the present invention.
FIG. 13 is a diagram illustrating a method of forming a semiconductor mask in a method of manufacturing a semiconductor device according to the present invention.
FIG. 14 is a structural sectional view illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.
FIG. 15 is a structural sectional view illustrating the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention.
FIG. 16 is a structural sectional view showing a manufacturing method of a conventional example.
FIG. 17 is a structural sectional view of a conventional semiconductor device.
FIG. 18 is a structural sectional view showing misalignment of a semiconductor mask.
[Explanation of symbols]
11 Silicon substrate
21,25,26 Trench pattern
27 Dummy pattern
22-24, 71, 73-75 Silicon oxide film
31 Gate electrode
32 source / drain
33 Active area
34 n-well
35 p-well
36 island pattern
41, 42 Wiring
61 polishing pad
81 resist pattern
82 Planarization resist

Claims (13)

In a semiconductor device in which elements are respectively formed in a plurality of element regions separated by a trench pattern,
In a region other than the element region, and in a region other than the trench pattern, a dummy pattern that is an array pattern of grooves or holes is formed, and the projections defined by the dummy pattern have regularity. While being present repeatedly, the distance between adjacent convex portions is 10 μm or less, and the average area per element region in all the element regions of the plurality of element regions , and the basis of the repetition of the convex portions. A semiconductor device, wherein a ratio to a unit area is 0.5 or more and 2 or less, and the trench pattern and the dummy pattern are buried with an insulating film. In a semiconductor device in which elements are respectively formed in a plurality of element regions separated by trench patterns,
In a region other than the element region, and in a region excluding the trench pattern, a dummy pattern that is an array pattern of grooves or holes is formed, and the projections defined by the dummy pattern have regularity. The distance between adjacent protrusions is 10 μm or less, and the average area per one element region in the most frequently formed element among the plurality of element regions, Is 0. The ratio of the repeating unit to the area of the basic unit is 0. . The semiconductor device, wherein the number is 5 or more and 2 or less, and the trench pattern and the dummy pattern are buried in an insulating film. The dummy patterns A semiconductor device according to claim 1 or 2, wherein a lattice shape having regularity. A well isolation trench pattern is formed at a boundary between an n-well and a p-well in a region where the dummy pattern is formed, and the well isolation trench pattern is buried with the insulating film. Item 4. The semiconductor device according to any one of Items 1 to 3 . An under-wiring trench pattern is formed in the region where the dummy pattern is formed, and the under-wiring trench pattern is buried with the insulating film. the semiconductor device according to any one of claims 1 to 4 also narrow wiring width is formed. The insulating layer, the semiconductor device according to any one of claims 1 is a laminated film 5. A mask pattern forming step of forming a mask pattern for simultaneously forming at least two patterns of a trench pattern each surrounding a periphery of a plurality of element regions and a dummy pattern which is an array pattern of grooves or holes; An etching step of simultaneously forming at least the trench pattern and the dummy pattern by dry etching using a mask as a mask, an insulating film depositing step of depositing an insulating film, and polishing and flattening the insulating film by a chemical mechanical polishing method. Polishing step, comprising an element forming step of forming an element in the element region,
The dummy pattern is a region other than the element region and is formed in a region excluding the trench pattern, and the dummy pattern has a regularity defined by the dummy pattern. And the distance between adjacent convex portions is 10 μm or less, and the average area per one element region in all the device regions of the plurality of element regions, and the repetition of the convex portions The ratio of the basic unit to the area is 0 . A method for manufacturing a semiconductor device, wherein the number is 5 or more and 2 or less. A mask pattern forming step of forming a mask pattern for simultaneously forming at least two patterns of a trench pattern each surrounding a periphery of a plurality of element regions and a dummy pattern which is an array pattern of grooves or holes; An etching step of simultaneously forming at least the trench pattern and the dummy pattern by dry etching using a mask as a mask, an insulating film depositing step of depositing an insulating film, and polishing and flattening the insulating film by a chemical mechanical polishing method. Polishing step, comprising an element forming step of forming an element in the element region,
The dummy pattern is a region other than the element region and is formed in a region excluding the trench pattern, and the dummy pattern has a regular section formed by the dummy pattern. And the distance between adjacent protrusions is 10 μm or less, and the average area per element region in the element with the highest frequency of formation among the plurality of element regions ; and A method for manufacturing a semiconductor device, wherein the ratio of the area of the basic unit of the repetition of the projection to the area is 0.5 or more and 2 or less. A mask pattern forming step of forming a mask pattern for simultaneously forming at least two patterns of a trench pattern each surrounding a periphery of a plurality of element regions and a dummy pattern which is an array pattern of grooves or holes; An etching step of simultaneously forming at least the trench pattern and the dummy pattern by dry etching using a mask as a mask, an insulating film depositing step of depositing an insulating film, a planarizing material forming step of forming a planarizing material, and dry etching. An etch back step of etching back the insulating film and the planarizing material by a technique, and an element forming step of forming an element in the element region,
The dummy pattern is a region other than the element region and is formed in a region excluding the trench pattern, and the dummy pattern has a regular section formed by the dummy pattern. And the distance between adjacent convex portions is 10 μm or less, and the average area per one element region in all the device regions of the plurality of element regions , and the repetition of the convex portions Wherein the ratio of the basic unit to the area of the basic unit is 0.5 or more and 2 or less. A mask pattern forming step of forming a mask pattern for simultaneously forming at least two patterns of a trench pattern each surrounding a periphery of a plurality of element regions and a dummy pattern which is an array pattern of grooves or holes; An etching step of simultaneously forming at least the trench pattern and the dummy pattern by dry etching using a mask as a mask, an insulating film depositing step of depositing an insulating film, a planarizing material forming step of forming a planarizing material, and dry etching. An etch back step of etching back the insulating film and the planarizing material by a technique, and an element forming step of forming an element in the element region,
The dummy pattern is a region other than the element region and is formed in a region excluding the trench pattern, and the dummy pattern has a regularity defined by the dummy pattern. And the distance between adjacent protrusions is 10 μm or less, and the average area per element region in the element with the highest frequency of formation among the plurality of element regions; and The ratio of the area of the basic unit of the repetition of the convex portion to 0 . A method for manufacturing a semiconductor device, wherein the number is 5 or more and 2 or less. The mask pattern in the mask pattern forming step is for simultaneously forming a well-separating trench pattern of an n-well and a p-well in a region where the dummy pattern is to be formed. 11. The method of manufacturing a semiconductor device according to claim 7 , wherein at least the trench pattern, the dummy pattern, and the well separating trench pattern are simultaneously formed by dry etching. The mask pattern in the mask pattern forming step is for simultaneously forming an under-wiring trench pattern in a region where the dummy pattern is formed, and the etching step is performed by dry etching at least the trench pattern. Forming the dummy pattern and the under-wiring trench pattern simultaneously,
12. The semiconductor according to claim 7, further comprising a wiring forming step of forming a wiring having a width smaller than the width of the wiring-underlying trench pattern on the insulating film in which the wiring-underlying trench pattern is buried. Device manufacturing method. The method of manufacturing a semiconductor device according to any one of claims 7 to 10, further comprising a stacked film forming step of forming a stacked film made of different films in the trench pattern and the dummy pattern.

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