JP3611698B2 - Multiplexing method for time division multiplexer - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention Time division multiplexing device that time-division multiplexes digital data from a number of data terminal devices having various data transmission speeds and efficiently transmits them using a high-speed digital line Multiplexing method About.
[0002]
[Prior art]
An example of a conventional time division multiplexing apparatus is shown in FIG. In this configuration, various terminal interfaces DATAI / F, a high-speed digital interface SDII / F, and a control device CONT are connected in a bus format by a highway HW.
[0003]
The low-speed data of the terminal interface DATA I / F is transferred to the high-speed digital interface SDII / F bit by bit according to an instruction from the control device CONT, and bit multiplexing is performed.
[0004]
An example of this method is disclosed in Japanese Patent Application Laid-Open No. 61-163741, but this method is often used in a relatively small time division multiplexing apparatus because of its simple configuration.
[0005]
FIG. 19 is a drawing quoted from “Advanced MTDM System Configuration” taken from page 1,435 to page 1,453 of NTT Research Practical Report Vol. 36, No. 11 (1987).
[0006]
This example has a time-division switch TSW that performs time-division switching at a basic rate of 64 kilobits per second (hereinafter referred to as Kbps). Each of 3.2 Kbps, 8 Kbps, and 0.4 Kbps performs bit multiplexing using the time slot switching unit TSI.
[0007]
A method for placing low-speed data from a terminal interface on a 64 Kbps channel is described in Recommendation X. of the International Telecommunication Union Telecommunication Standardization Sector (hereinafter referred to as ITU-T). The purpose of this is to perform end-to-end communication between low-speed terminal devices through an integrated service digital network ISDN (hereinafter referred to as ISDN) line, and repeatedly transmits low-speed data to a 64 Kbps channel. A method of putting the data into an apparent data of 64 Kbps is used.
[0008]
ITU-T recommendations include V.C. 110. However, as in the case of a time division multiplexing apparatus, in order to perform bit multiplexing while providing a switching function with a time division switch, in order to put low-speed data of a terminal interface on a 64 Kbps channel, Recommendation V. 110 is complex and difficult to control.
[0009]
[Problems to be solved by the invention]
However, in the conventional method as described above,
The method without a time division switch does not require low-speed data to be placed on a 64 Kbps channel, but has a drawback that it is difficult to cope with a change in the line configuration accompanying a change in traffic, and it is difficult to expand the scale.
[0010]
In a system having a time division switch, in order to perform bit multiplexing while providing a switching function, low-speed data of a terminal interface is placed on a 64 Kbps channel, and for the purpose of always efficiently re-multiplexing, ITU-T Recommendation X. The use of 50 is redundant, and there is a drawback that the communication speed that can be supported is limited.
[0011]
Also, Recommendation V. Even if the method according to 110 is adopted, there is a drawback that the size of the hardware becomes complicated and complicated.
[0012]
The present invention has been made to solve such a conventional problem. When low-speed data is put on a channel having a basic speed of, for example, 64 Kbps, the signal data is not repeatedly put on the channel of 64 Kbps. Economical time division multiplexer by making it possible to identify whether data is on board Multiplexing method The purpose is to provide.
[0013]
[Means for Solving the Problems]
In order to solve the above problem, the invention according to claim 1 In a multiplexing method of a time division multiplexing apparatus for multiplexing and transmitting data from a plurality of data terminal apparatuses by a multiplexing unit, A multi-frame having a period of 1 / integer of the frame period of a digital channel having a preset basic speed is provided, and each frame in the multi-frame Said A status bit is provided to indicate that signal data from the data terminal device is contained, Above From data terminal equipment De When the data is put on a frame in the multiframe, the status bit of the frame is turned on, Said In the multiplexing unit, from the frame in which the status bit is turned on in the multiframe, Said Only the signal bits of the data signal from the data terminal device are taken out and mapped according to the contents written in the mapping table, thereby multiplexing in bit units.
[0014]
According to the present invention, it is possible to identify which frame in the multiframe contains the signal data from the data terminal device by providing the status bit, so that the low-speed signal data from the data terminal device is It is possible to put on the digital channel of the basic speed without repeatedly putting on the digital channel, and when the signal bit of the data signal from multiple data terminal devices is taken out from the multi-frame, the frame with the signal bit is displayed with the status bit Therefore, multiplexing in bit units can be easily performed.
[0015]
The invention according to claim 2 of the present invention is In a multiplexing method of a time division multiplexing apparatus that performs time division exchange connection with data from a plurality of data terminal apparatuses by using a time division switch and then multiplexes and transmits the data by a multiplexing unit. A multi-frame having a period of 1 / integer of the frame period of a digital channel having a preset basic speed is provided, and each frame in the multi-frame is provided for each frame. Above A status bit is provided to indicate that signal data from the data terminal device is contained, Said From data terminal equipment De When the data is put on the frame in the multi-frame, the status bit of the frame is turned on, Said In time division switch Is , Make a time division exchange connection with a digital channel of basic speed, Above In the multiplexing unit, from the frame in which the status bit is turned on in the multiframe, Above Only the signal bits of the data signal from the data terminal device are taken out and mapped according to the contents written in the mapping table, and multiplexed in bit units.
[0016]
According to the present invention, a time division switch performs time division exchange connection with a basic speed digital channel by displaying a frame in a multiframe containing low-speed signal data from a data terminal device by a status bit. In the multiplexing unit, only the signal bits are extracted from the frame in which the status bit of the multi-frame is turned on, and mapping can be easily performed in bit units.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a system configuration diagram showing an embodiment of the present invention, and 10 has various data transmission rates, for example, a data transmission rate that is an integral multiple of 1.2 kilobits per second (hereinafter referred to as Kbps). A data terminal device having a data transmission rate of 1.2 Kbps, or a data transmission rate of an integral multiple of 8 Kbps, and having a data transmission rate of 8 Kbps. DTE, 20 is a time division multiplexing apparatus according to the present invention, and 30 is a high-speed digital having an integral multiple of a basic rate such as 64 Kbps in an integrated service digital network ISDN (hereinafter referred to as ISDN), for example. It is a line.
[0018]
The data terminal device DTE 10 (the device number is shown in parentheses) is connected to the time division multiplexing device 20 via the terminal 1 of the time division multiplexing device 20 (the circuit number is shown in parentheses). The time division multiplexing apparatus 20 is further connected to the high-speed digital line 30 of each route via a terminal 9 (the circuit number is shown in parentheses), and further connected to the time division multiplexing apparatus 20 of the other station, to connect the network. It is composed.
[0019]
The network referred to in this embodiment is a network in which a data terminal device and a data terminal device are semi-fixedly connected, unlike an exchange network that connects for each call.
[0020]
Time division multiplexing apparatus in the present embodiment Multiplexing method The main purpose is to multiplex the data at a relatively low speed of the data terminal device and select a plurality of terminal data with a channel having a relatively high basic speed such as 64 Kbps. When doing.
[0021]
FIG. 2 is a block configuration diagram of the time division multiplexing apparatus 20 showing an example of the embodiment of the present invention. The basic speed of the digital line can be freely set in advance. However, in the following description of the time division multiplexing apparatus 20, the basic speed is set to 64 Kbps, and ISDN that provides a high-speed digital line having an integral multiple of the basic speed is used. Assume that the network is configured by a high-speed digital line having a standard I interface of the International Telecommunication Union Telecommunication Standardization Sector (hereinafter referred to as ITU-T) for subscribers.
[0022]
In FIG. 2, reference numeral 1 denotes a terminal to which various types of data terminal devices DTE are connected, and representatively represents a group of terminals. Alphanumeric characters in parentheses after the symbols represent circuit numbers. That is, in the embodiment of FIG. 2, n terminals 1 (1) to (n) are provided, indicating that n data terminal devices DTE can be connected. Here, n is an arbitrary integer.
[0023]
Reference numeral 2 denotes a terminal interface (hereinafter, the interface is referred to as I / F) having a function of placing data from the data terminal device DTE on a 64 Kbps transmission highway.
[0024]
As already described, the data transmission rate of the data terminal equipment DTE is an integer multiple of 1.2 Kbps, for example, a data transmission rate of 1.2 Kbps system such as 2.4 Kbps, 4.8 Kbps, and an integer multiple of 8 Kbps, for example, There are 8 Kbps data transmission speeds such as 16 Kbps and 32 Kbps.
[0025]
Since there is a difference between the two controls in the embodiment of the present invention, the following description distinguishes them.
[0026]
Reference numeral 3 denotes a time division switch TSW, which performs time division exchange connection in units of 64 Kbps channels.
[0027]
A multiplexing unit MUX 4 includes a plurality of bit multiplexers / demultiplexers BITMPX / DMPX and sub-rate multiplexers / demultiplexers SUBRATEMPX / DMPX that multiplex them.
[0028]
Reference numeral 5 denotes a part of the multiplexing unit 4, which is a bit multiplexer / demultiplexer BITMPX / DMPX that multiplexes the low-speed data of the data terminal device DTE that has been put on the 64 Kbps channel from the time division switch TSW 3 in bit units.
[0029]
6 is also a part of the multiplexing unit 4, and a digital signal sent from a plurality of bit multiplexers / demultiplexers BITMPX / DMPX5 is time-division multiplexed and sent to the forward highway FHW. DMPX.
[0030]
Reference numeral 7 denotes a transmission line I / F, which extracts data from the forward highway FHW to its own transmission line and sends it to the transmission line in accordance with the speed of the high-speed digital line.
.
[0031]
A system clock generator 8 generates a clock synchronized with a synchronization signal from the transmission path and generates all clock signals necessary in the time division multiplexing apparatus.
[0032]
Next, the outline of the operation of the time division multiplexing apparatus 20 will be described with reference to FIG.
[0033]
In the terminal I / F2, data from data terminal devices of various data transmission speeds and data terminals of both synchronous and asynchronous types are sent to the 64 Kbps channel of the sending highway SHW with the basic unit of the 64 Kbps channel. Put it on. In the present embodiment, description will be given assuming that the highway speed is 64 Kbps channel, 64 channel speed, 4.096 megabit per second (hereinafter abbreviated as 4 Mbps).
[0034]
The data placed on the 64 Kbps channel of the sending highway SHW is connected to one of the receiving highways RHW of the multiplexing unit MUX4 by the time division switch TSW3. This receiving highway RHW is connected to one of the bit multiplexer / demultiplexer BITMPX / DMPX5 in the multiplexing unit MUX4.
[0035]
Here again, the alphanumeric characters in parentheses after the reference numeral 5 represent circuit numbers, and so on. In the following description, i = 4.
[0036]
The receiving highway RHW entering the bit multiplexer / demultiplexer BITMPX / DMPX5 is very inefficient because 1.2 Kbps low-speed data is also carried on a 64 Kbps channel.
[0037]
For this reason, the multiplexer MPX unit of the bit multiplexer / demultiplexer BITMPX / DMPX5 uses meaningful bit data (hereinafter referred to as significant data) sent from the data terminal device using the bit multiplexing technique described in detail later. Only).
[0038]
The data multiplexed in this way is sent to the upstream highway UHW. This data is also sent to the sub-rate multiplexer / demultiplexer SUBRATEMPX / DMPX6 in the multiplexing unit MUX4.
[0039]
At this time, the output of the other bit multiplexer / demultiplexer BITMPX / DMPX5 is also sent to the sub-rate multiplexer / demultiplexer SUBRATEMPX / DMPX6.
[0040]
The multiplexer MPX section of the sub-rate multiplexer / demultiplexer SUBRATEMPX / DMPX6 multiplexes data from four (i = 4) upstream highways UHW for each route of the transmission path to be output and sends them to the forward highway FHW.
[0041]
J transmission lines I / F7 are connected to the forward highway FHW. Here, the transmission line I / F 7 interfaces with, for example, an ISDN digital line terminator DSU and is connected to a high-speed digital line.
[0042]
Each transmission line I / F 7 takes in only the data assigned to its own line from the forward highway FHW, and this data is output according to the clock from the system clock generator SCLK 8 to the corresponding output terminals 9 (1) to 9 ( to j) at a speed consistent with the data transmission speed of the transmission path.
[0043]
On the other hand, the data sent to the terminal 9 from the transmission path is extracted in the transmission path I / F 7 and placed in an empty time slot of the reverse highway BHW.
[0044]
The data on the reverse highway BHW is sent to the downstream highway DHW by the demultiplexer DMPX unit of the sub-rate multiplexer / demultiplexer SUBRATEMPX / DMPX6 in the multiplexing unit MUX4.
[0045]
The bit multiplexer / demultiplexer BITMPX / DMPX5 that has received data from the downlink highway DHW is a demultiplexer DMPX unit, and a data terminal device that is a transmission partner of data on the downlink highway by a bit mapping table not shown in FIG. Each data is decomposed and placed on a 64 Kbps channel and sent to the sending highway SHW.
[0046]
The 64 Kbps channel time-division multiplexed on the sending highway SHW is connected to the receiving highway RHW of the terminal I / F2 corresponding to the data terminal device of the transmission partner by the time division switch TSW3, and the receiving highway RHW is connected to the terminal I / F2. The data of the 64 Kbps channel allocated to itself is taken in, converted to the data transmission rate of the data terminal device, and if it is an asynchronous terminal, synchronous / asynchronous conversion is also performed and sent to terminal 1.
[0047]
The above is the outline of the operation of the time division multiplexing apparatus according to FIG. 2. Next, the details of the operation of each part and the principle of multiplexing will be described with reference to FIG.
[0048]
FIG. 3 is a block diagram showing the configuration of the terminal I / F 2. The data terminal device DTE is connected to the five terminals on the left side of FIG.
[0049]
In FIG. 3, 2-1 to 2-3 are cable driver CDs, and 2-4 and 2-5 are cable receivers CR, which match the logic level in the terminal I / F with the external cable.
[0050]
A variable frequency divider 2-6 receives a clock signal from the system clock generator SCLK8 and divides the frequency to generate a necessary clock in the terminal I / F.
[0051]
2-7 and 2-22 are circuits that absorb the phase difference between the synchronous signals of the synchronous terminal device and the terminal I / F, and 2-8 is a circuit that converts the signals of the asynchronous terminal device into synchronous signals. Is a circuit for asynchronously converting a synchronous signal in the terminal I / F for an asynchronous terminal, and 2-9 and 2-24 are selectors SEL for selecting a synchronous terminal or an asynchronous terminal.
[0052]
2-10 is a circuit for controlling generation of a pseudo carrier signal to be sent before and after transmission of signal data, 2-26 is a circuit for detecting a received pseudo carrier signal, and 2-11 is a pseudo circuit generated in 2-10. Multiplexers MPX, 2-25 for placing carriers before and after the data signal are selectors SEL that select whether the control signal is a pseudo carrier or can be directly received.
[0053]
2-13 and 2-19 are the sending and receiving time slot switching units TSI, 2-12, and 2-17 are the write address controllers of TSI2-13 and 2-19, respectively, 2-14, and 2-20 are These are read address controllers of TSI 2-13 and 2-19, respectively.
[0054]
2-15 is a multiplexer MPX that multiplexes data from each terminal device and sends it to the sending highway, and 2-21 is a demultiplexer DMPX that separates signals on the receiving side.
[0055]
Reference numerals 2-16 and 2-18 denote circuits for adding and detecting an F bit indicating that data is on the frame. Details of the F bit will be described later.
[0056]
Next, the operation of the terminal I / F 2 will be described with reference to FIG.
[0057]
The terminal, reception data RD, carrier detection CD, transmission data SD, transmission request RS, and clock CLK in FIG. 3 are a breakdown of what is collectively referred to as terminal 1 in FIGS.
[0058]
When the data terminal apparatus DTE requests transmission, a signal is transmitted from the terminal apparatus to the terminal RS. This signal is received by the cable receiver CR2-5, converted to a logical level, and sent to the pseudo carrier control unit and time slot switching unit TSI (A), (B) 2-13.
[0059]
There are two methods for transmitting the transmission request RS. One is a method of sending a scramble signal called a pseudo carrier signal on the main signal at the beginning and end of communication, which is also a recommendation V13 of ITU-T, for example, and the other is S described in detail later. This is a method of sending a signal bit named a bit.
[0060]
When the pseudo carrier signal is used, the pseudo carrier control unit 2-10 (scramble circuit) receives the transmission request signal and generates a pseudo carrier signal, and passes through the multiplexer MPX2-11 to the time slot switching unit TSI (A), (B) 2 ―Send to 13.
[0061]
When the S bit which is a signal bit is used, the transmission request RS is written in the S bit position of the time slot switching units TSI (A) and (B) 2-13 under the control of the write address controller WAC2-12.
[0062]
The transmission data is sent to the terminal SD. The data terminal device DTE includes a synchronous terminal device and an asynchronous terminal device. A clock signal is sent from the cable driver CD2-3 to the synchronous terminal device through the terminal CLK. The synchronous terminal device transmits the transmission data SD in synchronization with this clock. I will send you.
[0063]
The asynchronous terminal device does not receive the clock CLK from the terminal I / F2. Asynchronous terminal apparatuses include, for example, an asynchronous terminal apparatus that transmits a start signal and a stop signal before and after a series of data signals.
[0064]
In the case of a synchronous terminal device, the transmission data sent to the terminal SD is converted to a logic level by the cable receiver CR2-4, and the phase of the transmission data clock and the internal clock are matched by the phase difference absorption circuit 2-7. It is selected by the selector SEL2-9 that selects either synchronous or asynchronous and enters the multiplexer MPX2-11.
[0065]
In the case of an asynchronous terminal device, the asynchronous data signal passed through the cable receiver CR2-4 is converted into a synchronous signal by the asynchronous / synchronous conversion unit 2-8, and is selected by the selector SEL2-9 that selects whether it is synchronous or asynchronous. Enters the multiplexer MPX2-11.
[0066]
In the multiplexer MPX2-11, the data signal and the pseudo carrier signal are multiplexed and sent to the time slot switching units TSI (A) and (B) 2-13. The signal from the multiplexer MPX2-11 is sequentially written in the time slot switching units TSI (A) and (B) 2-13 by the control of the write address controller WAC2-12, and on the highway by the control of the read address controller RAC2-14. It is randomly read according to the data format and placed in the specified time slot.
[0067]
When the control signal is sent using the S bit which is the signal bit without using the pseudo carrier, the multiplexer MPX2-11 does not multiplex with the pseudo carrier, and the control signal and the write address controller WAC2- By the control of 12, the time slot switching unit TSI (A) and the S bit position of (B) are sequentially written. Data and control signals read in a predetermined time slot under the control of the read address controller RAC2-14 are multiplexed by the multiplexer MPX2-15 and arranged in the same format.
[0068]
The time slot switching units TSI (A) and (B) 2-13 in FIG. 3 have the same two surfaces and are alternately used for writing and reading every 0.8 KHz so that writing and reading can be performed simultaneously. It has become. Other than the time slot switching units TSI (A) and (B) 2-13, those indicated by (A) and (B) after the symbol in the drawing are alternately used. The other indicates that the reading is performed.
[0069]
Here, how to put data in the time slot will be described with reference to FIGS.
[0070]
In FIG. 7, in addition to the 8 KHz period frame that is the basis of the 64 Kbps channel, 10 frames of 8 KHz frame, which is convenient for processing low-speed data, becomes 1 / 10th 0.8 KHz. A multi-frame, 0.8 KHz multi-frame is defined. Therefore, the length of one frame is 1.25 ms in the 0.8 KHz multiframe.
[0071]
Here, 10 frames of 8 KHz frames are one multi-frame, but 20 frames of 8 KHz frames may be one multi-frame and a 0.4 KHz multi-frame may be defined.
[0072]
FIG. 7 shows the relationship between this 0.8 KHz multiframe and the received data of 2.4 Kbps, 9.6 Kbps, and 38.4 Kbps, which are 1.2 Kbps data transmission rates. It shows how many bits of data are received during each period. As shown in the figure, 3 bits are received at 2.4 Kbps, 12 bits are received at 9.6 Kbps, and 48 bits are received at 38.4 Kbps.
[0073]
In this embodiment, it is decided to carry 3 bits in one 8 KHz frame and carry 6 bits when 3 bits are insufficient. FIG. 8 illustrates which 8 KHz frames of 10 multiframes should be transmitted under such an arrangement, and is in a time relationship delayed by one multiframe, that is, 1.25 m from FIG.
[0074]
As apparent from FIG. 8, in the case of 2.4 Kbps, only the first frame F1 of 10 multiframes, and in the case of 9.6 Kbps, the first, third, sixth, and eighth of the 10 multiframes. Each frame carries three bits in four frames, ie, F1, F3, F6, and F8.
[0075]
In the case of 38.4 Kbps, even if 3 bits are sent in all 10 frames, only 3 bits are sent and only 30 bits at a bit rate of 30 bits × 0.8 KHz = 24 Kbps. In this case, 6 bits are sent in one frame. . If it does in this way, as shown in FIG. 8, it turns out that what is necessary is just to send by 8 frames except the 5th, 10th frame.
[0076]
In the case of 1.2 Kbps, the same data is sent twice, so that it is apparently sent at 2.4 Kbps. In this case, transmission for two multiframes, that is, 2.5 ms transmission is delayed.
[0077]
As a result, as shown in FIG. 8, a frame with data and a frame without data are generated even within a 0.8 KHz multiframe.
[0078]
An example of the format of the highway time slot in the present embodiment is shown in FIG. In the figure, B7 to B0 indicate bits in an arbitrary time slot, B7 is the most significant bit MSB (Most Significant Bit), and B0 is the least significant bit LSB (Least Significant Bit). F1 to F10 indicate 10 frames in the 0.8 KHz multiframe shown in FIGS.
[0079]
The B7 bit, which is the MSB, is used as a status bit for indicating whether or not data exists in the frame, and is on (for example, 0) when there is data, and is off (for example, 1) when there is no data. Set to. In the present embodiment, this B7 bit, which is the status bit, is called an F bit.
[0080]
The B6 bit in FIG. 9 is used to carry the terminal control line signal and is called the S bit. S1 in the figure is used for a signal such as a transmission request. Other S2, S3, etc. can be used for other purposes as required.
[0081]
FIG. 9 shows the bit configuration of each frame corresponding to FIG. 8 when sending low-speed data of 2.4 Kbps, 9.6 Kbps, and 38.4 Kbps to each time slot of the sending highway SHW of FIG. , D1 to D48 indicate individual data bits in the 0.8 KHz multiframe.
[0082]
FIG. 10 shows a bit configuration diagram similar to FIG. 9 for 8 Kbps, 56 Kbps, and 64 Kbps among 8 Kbps data transmission rates, and is based on the assumption that transmission is performed using all 10 frames. There is no such F bit.
[0083]
The S bit of the signal bit can also be used at 56 Kbps or less, but cannot be used at 64 Kbps because all bits are used as data bits.
[0084]
Note that transmission of data faster than 64 Kbps can be performed using a plurality of 64 Kbps channels.
[0085]
7 to 10, some data transmission rates have been described, but FIG. 11 shows the main numbers including other data transmission rates. The numbers shown in FIG. 11 are defined in the present embodiment and are merely examples.
[0086]
Returning to FIG. 3, the read address controller RAC2-14 uses the time slot switching unit TSI (A) or (B) in the format shown in FIG. 9, FIG. 10 or a similar format according to the data transmission speed of the data terminal device. The data is read from 2-13, and when the F bit is necessary, the F bit adding unit 2-16 is instructed to add the F bit and send it out to the designated time slot of the sending highway SHW.
[0087]
The data placed on the time-division multiplexed 64 Kbps channel of the transmission highway SHW of the terminal I / F2 is transferred from the four bit multiplexer / demultiplexers BITMPX / DMPX5 (1) in the multiplexing unit MUX4 by the time division switch TSW3. (4) Connected to a certain time slot of one receiving highway RHW.
[0088]
The time division multiplexing apparatus 20 efficiently multiplexes data using a high-speed digital line that is an integral multiple of 64 Kbps in the middle by bit-multiplexing relatively low-speed data between the two data terminal apparatuses DTE10. Although it is intended and does not inherently have a switching function, the introduction of the time division switch TSW3 makes it possible to change the line setting on demand to some extent.
[0089]
The change of the line setting by the time division switch TSW3 is limited to the change between the terminal I / F 2 and the multiplexing unit 4, and the connection change within the setting range of the multiplexing unit 4 is stopped.
[0090]
In the sending highway SHW of the terminal I / F 2, the highway speed is set to 4 Mbps as described above. Therefore, the receiving highway RHW in FIG. 4 has data of various speeds loaded on the 64 Kbps channel at the maximum of 64 channels. It comes divided and multiplexed.
[0091]
Next, an outline of each device in FIG. 4 will be described.
[0092]
Since the feed highway SHW described in FIG. 3 passes through the time division switch 3, it is connected to the receiving highway RHW shown in FIG.
[0093]
Reference numeral 5-1 denotes an F-bit detection unit already described, and reference numeral 5-17 denotes an F-bit addition unit. 5-3 and 5-13 are memories MEM for storing upstream and downstream data, 5-2 and 5-14 are write address controllers of the memory MEM, and 5-4 and 5-16 are read addresses of the same memory MEM. It is a controller.
[0094]
Reference numeral 5-5 denotes a transmission bit synchronization pattern generation unit, which will be described later, and 5-6 denotes a multiplexer MPX that multiplexes the synchronization pattern into signal data.
[0095]
5-7 is a detection unit provided for each route in order to detect multi-frames of downstream signal data, 5-9 is a reception width register that indicates the reception width of signal data for each route, and 5-8 is a route for each route. And a write address controller that writes downstream signal data to the memory MEM5-11 based on information from the corresponding multiframe detection unit 5-7.
[0096]
Reference numeral 5-10 denotes a multiplexer MPX that multiplexes write signals from the write address controller WAC5-8 and controls the memory MEM5-11.
[0097]
Reference numeral 5-12 denotes a read address controller RAC for controlling the reading of data stored in the memory MEM5-11, and 5-15 denotes a bit mapping table which is a key for bit multiplexing, which will be described in detail below.
[0098]
Next, the operation of the bit multiplexing unit on the sending side will be described with reference to FIG. 4. The principle will be described with reference to FIGS.
[0099]
The diagram on the left side of FIG. 12 corresponds to the bit pattern of FIGS. 9 and 10 and represents all bits within one 0.8 KHz multiframe of a time slot.
[0100]
The memories MEM (A) and (B) 5-3 in FIG. 4 each have a memory area for storing the bit pattern on the left side in FIG. 12 for each time slot. In these memory areas, data of which bit rate is stored according to data written in a bit mapping table described later, in other words, a received bit pattern as shown in FIGS. 9 and 10 is determined.
[0101]
Therefore, in the 4 Mbps highway signal entering the receiving highway RHW in FIG. 4, the F bit detection unit 5-1 detects the F bit for each time slot, and only significant data identified by the F bit is written to the write address controller WAC5. It is written in the determined memory area under the control of -2.
[0102]
As already described in the time slot switching units TSI (A) and (B) 2-13 in FIG. 3, (A) and (B) of the memory MEM5-3 are the same, and data is written to the memory area. The writing and reading are switched every 1.25 ms, that is, at a period of 0.8 KHz, and when writing is performed on one side, reading is performed on the other side.
[0103]
Next, a bit multiplexing method will be described with reference to FIG.
[0104]
As shown in FIGS. 9 and 10, in the case of low-speed data, the amount of data written in the memory area on the left side of FIG. 12 is small, and if it is sent as it is to the transmission path, there is a lot of invalid data and the efficiency is low. . Therefore, in order to convert the data on the left side of FIG. 12 into the transmission format, a table on the right side of FIG. 12 is virtually created and the data is transferred. This virtual table is hereinafter referred to as a virtual table.
[0105]
In order for the size of this virtual table to correspond to any transmission rate, it is sufficient if the memory area on the left side of FIG. Theoretically, the vertical and horizontal lengths of the virtual table can be freely determined. The only restriction is that the number obtained by multiplying the vertical length by the number of horizontal bits is the number obtained by multiplying the number of bits in the left table by the number of time slots.
[0106]
Since this virtual table is for mapping only significant data in the memory area shown in the left side of FIG. 12, it is not necessary to have all of the left side memory area and 64 time slots described above. It is also possible to compress the data volume by making the table smaller.
[0107]
In this embodiment, the virtual table is not compressed and the sub-rate multiplexer / demultiplexer SUBRATEMPX / DMPX6 reduces the speed to half. However, the virtual table is half, that is, 512 bits in the horizontal direction in FIG. The same effect can be obtained by setting the half of 256 bits.
[0108]
Here, a virtual table in which the number of bits obtained by multiplying the memory area (10 frames × 8 bits) on the left side of FIG. 12 by 64 time slots is the same width 10 as the number of frames of one multiframe and each has 512 bits. To map. This corresponds to F1 to F10 in the vertical direction and 512 bits in the horizontal direction in the diagram on the right side of FIG.
[0109]
Further, 512 bits in the horizontal direction are divided for each route of the transmission path. The division is performed according to the data amount for each route, and here, the number of routes is assumed to be eight. In FIG. 12, R1 to R8 bits are assigned for each route. The sum total of R1 to R8 is 512.
[0110]
If the significant data written in the memory area shown on the left side of FIG. 12 is a 2.4 Kbps signal, it is 3 bits as shown in FIG. This is written as data bits 3, 4, and 5 in B5, B4, and B3 of F1 on the memory area on the left side of FIG. 12, so if the destination is route 1, for example, route 1 of the table on the right side of FIG. Are allocated to F1, F2, and F3 of the second bit.
[0111]
In this way, significant data of other time slots are also allocated by allocating them from the left, for example, to an empty place in the table on the right side of FIG. Therefore, bits other than significant data on the left memory area are not mapped to the right table.
[0112]
When such an operation is performed for all the time slots, only the significant data is packed from the left for each route in the right table. If the right table to which significant data is assigned in this way is read from left to right, for example, from top to bottom, significant data is regularly arranged for each route. Can be taken out and sent to the transmission line.
[0113]
Note that F1, F2, and F3 (hatched portions in the figure) of bit number 1 of each route in the table on the right side of FIG. 12 cannot be loaded with data in order to carry a synchronization signal described later.
[0114]
How the writing and reading on the virtual table described above are actually performed will be described with reference to FIG.
[0115]
The upper table of FIG. 13 is a copy of the table on the right side of FIG. This table represents all bits sent in one 0.8 KHz multiframe on a 4 Mbps highway. The table from F1 to F10 at the bottom of FIG. 13 is the contents of the bit mapping table 5-15 in FIG. 4, and the small frame corresponds to 1 bit of the upper virtual table.
[0116]
In this small frame, the original bit number (one of bit numbers 1 to 80 on the memory area on the left side of FIG. 12) mapped on the corresponding virtual table and the time when the bit was carried The slot number TS, in other words, the address of the input data bit written in the memories MEM (A) and (B) 5-3 in FIG. 4 is written.
[0117]
Therefore, under the control of the read address controller 5-4 in FIG. 4, the address of F1 in the bit mapping table shown in the lower part of FIG. 13 (that is, the bit mapping table 5-15 in FIG. 4) is sequentially read from left to right, If the data at the address on the memories MEM (A) and (B) 5-3 is read and this is repeated from F2 to F10, the data on the virtual table on the right side of FIG. 12 is changed from left to right and from top to bottom. It will be read out.
[0118]
In this way, extracting only significant data from low-speed data placed on a 64 Kbps channel and compressing it is called bit multiplexing.
[0119]
The data read from the memories MEM (A) and (B) 5-3 in this way is sent to the multiplexer MPX5-6 in FIG. 4 at a speed of 4 Mbps.
[0120]
As can be seen from the above description, the data rate for each route is determined by the bit mapping table 5-15 in FIG. Therefore, if the data of the bit mapping table 5-15 is rewritten, the network configuration can be freely set within the range of the number of routes of the time division multiplexing apparatus.
[0121]
Since there is also a request to change the line configuration between day and night, the bit mapping table 5-15 also has two sides. By rewriting the spare side in advance and switching to the spare side at the switching time, The line configuration can be changed.
[0122]
In the multiplexer MPX5-6 in FIG. 4, a synchronization signal with the counterpart station is added. Two patterns for synchronization acquisition and synchronization maintenance shown in FIG. 14 are prepared for the synchronization signal. In the present embodiment, the initial synchronization establishment pattern for capturing synchronization shown in FIG. 14 (1) is composed of 7 bits, and is exchanged with the partner station prior to the start of communication. An additional 1-bit answer bit represented by A in FIG. 14A is added to this synchronization establishment pattern. This is to inform the other station whether or not synchronization is established. When synchronization is not established, 0 is sent, and when the 7-bit initial synchronization establishment pattern from the other station is detected continuously, for example, eight times, Assuming that synchronization has been established, A = 1 and a synchronization establishment signal is sent to the partner station. If the initial synchronization establishment pattern A from the partner station also becomes 1, it means that the establishment of synchronization is confirmed with each other. Therefore, in this embodiment, the synchronization signal is set to 3 for maintaining synchronization shown in FIG. Switch to the degenerate synchronization pattern of bits.
[0123]
If the initial synchronization establishment pattern is lengthened, the number of continuous detections required for confirming the establishment of synchronization can be reduced, and if the initial synchronization establishment pattern is shortened, the number of continuous detections required for confirming the establishment of synchronization is increased. The time required for establishing synchronization is short, and if the pattern is short, the time required for establishing synchronization is long. In this embodiment, 7 bits are used for the initial synchronization establishment pattern and the number of continuous detections is 8. However, after synchronization is established, synchronization can be maintained, so that data can be sent in a part of the synchronization signal area. Switch to 3-bit degenerate synchronization pattern.
[0124]
Although the timing of establishing the initial synchronization differs depending on the route, the transmission of the 3-bit degenerate synchronization pattern is sent at the head of the 0.8 KHz multiframe for each route, as shown by hatching in FIG.
[0125]
The synchronization pattern described above is generated by the transmission bit synchronization pattern generation unit 5-5 in FIG. 4, multiplexed with the transmission data by the multiplexer MPX5-6, and sent to the upstream highway UHW.
[0126]
FIG. 15 is a state transition diagram for establishing and maintaining synchronization described above, and transitions between the four states of the hunting mode, the synchronization pull-in mode, the game synchronization confirmation mode, and the synchronization monitoring mode. The hunting mode is a state in which a synchronization pattern is not detected and a 7-bit synchronization pattern is being searched for.
[0127]
When a 7-bit synchronization pattern is detected in the multiframe, the synchronization pull-in mode is entered, and this state is maintained until this pattern is detected a predetermined number of times, for example, 8 times. Once in this mode, if the synchronization pattern is not detected a predetermined number of times, the mode returns to the hunting mode again.
[0128]
When the 7-bit pattern is detected a predetermined number of times, the A bit is transmitted to notify the opposite apparatus side that the initial synchronization has been established. A device that has received initial A synchronization and has received the A bit determines that the opposite side has completed synchronization establishment, and transitions to the synchronization monitoring mode. During communication, it is in the synchronous monitoring mode.
[0129]
If the synchronization is lost for some reason during the synchronization monitoring mode, the mode returns to the hunting mode.
[0130]
Although this synchronization signal is necessary for bit multiplexing, when there are a plurality of bit multiplexing areas (roots), the synchronization sequence of each area (root) operates independently, and each is based on FIG.
[0131]
Note that Rk in FIG. 14 represents the number of bits for each route in FIG.
[0132]
5, 6-2 is an upstream data storage memory MEM, 6-7 (1)-(4) is a downstream data storage memory MEM, and the downstream memory MEM is the bit multiplexer / demultiplexer of FIG. There are four memories MEM in the number of BITMPX / DMPX, that is, in this embodiment.
[0133]
6-1 writes data from the upstream highway UHW (1)-(4) into the memory MEM6-2, and the write address controller WAC, 6-4 stores the memory MEM6- according to the contents of the upstream subrate mapping table 6-5. 2 is a read address controller RAC that reads out only necessary data from 2 and gives a multiplexing instruction to the forward highway FHW to the multiplexer MPX of 6-3.
[0134]
A write address controller WAC 6-6 writes data from the reverse highway BHW to all the memories MEM6-7.
[0135]
6-8 (1)-(4) are provided corresponding to the memories MEM6-7 (1)-(4), respectively, and correspond to each downlink highway DHW according to the contents of the downlink sub-rate mapping table 6-9. A read address controller RAC that reads only data.
[0136]
Next, the operation of the sub-rate multiplexer / demultiplexer SUBRATEMPX / DMPX6 will be described with reference to FIG.
[0137]
The uplink highway UHW in FIG. 4 is connected to one of the uplink highways UHW (1) to (4) of the sub-rate multiplexer / demultiplexer SUBRATEMPX / DMPX6 shown in FIG.
[0138]
As already described, since the numbers in parentheses indicate circuit numbers, in this embodiment, the multiplexing unit 4 is provided with four upstream highways UHW and four downstream highways DHW, that is, four bit multiplexers / demultiplexers BITMPX / This indicates that there is DMPX5.
[0139]
In the memories MEM (A) and (B) 6-2 shown in FIG. 5, four 4 Mbps upstream highways UHW are input. These input data are sequentially written in the memories MEM (A) and (B) 6-2 under the control of the write address controller WAC6-1.
[0140]
As described above, the data written in the memories MEM (A) and (B) 6-2 takes the form of reading the virtual table on the right side of FIG. 12 from left to right and from top to bottom. These data written to the four uplink highways UHW (1) to (4) are read according to the contents of the uplink sub-rate mapping table 6-5 shown on the left side of FIG. 16 under the control of the read address controller RAC6-4. It is.
[0141]
Uplink highways UHW (1) to (4) have less significant data sent relative to the highway bit rate if the data rate of the data terminal device connected to terminal I / F2 is low.
[0142]
However, assuming that all data terminal devices are 64 Kbps synchronous terminals, all 4 Mbps highways will carry data and will be used 100%.
[0143]
Considering such an extreme case, the reading speed of the memories MEM (A) and (B) 6-2 must be 4 Mbps, which is the same as the writing speed, and the output side of the multiplexer MPX6-3 is 4 times 16 Mbps. It must be.
[0144]
However, in such an extreme case, it is meaningless to place a time division multiplexing device itself, and the purpose of placing the time division multiplexing device is to communicate relatively low speed data terminal devices at a high speed in units of 64 Kbps. Since it is performed efficiently using a digital line, the sub-rate multiplexer / demultiplexer SUBRATEMPX / DMPX6 reduces the speed to increase the efficiency of the transmission path.
[0145]
Since the data rate of the data terminal device is often lower than the basic rate of 64 Kbps, in this embodiment, the speed of the forward highway FHW is reduced to half of 8 Mbps.
[0146]
The table for one frame of the sub-rate mapping table 6-5 is configured as an uplink sub-rate mapping table on the left side of FIG. That is, 1,024 bits are assigned to each frame, and each of the upstream highway UHW numbers (1) to (4) and the bit number in the highway are written for each bit.
[0147]
Since each upstream highway UHW has 512 bits per frame, the number of bits is reduced to half by this sub-rate mapping table.
[0148]
As described above, the data on the uplink highway UHW is assigned to the sub-rate mapping table 6-5 on a bit-by-bit basis. However, the degenerate synchronization pattern shown in FIG. Be placed.
[0149]
The read address controller RAC6-4 reads the data on the memories MEM (A) and (B) 6-2 instructed by the sub-rate mapping table 6-5 bit by bit, and multiplexes the data by the multiplexer MPX6-3. All data is sent to the forward highway FHW at a speed of 8 Mbps.
[0150]
Transmission lines I / F 7 (1) to 7 (j) are connected to a forward highway FHW having a data rate of 8 Mbps.
[0151]
In FIG. 6, reference numerals 7-1 and 7-8 denote an upstream time slot replacement unit TSI and a downstream time slot replacement unit TSI, respectively, and 7-2 and 7-9 denote write address controllers RAC of the respective time slot replacement unit TSI, Reference numerals 7-3 and 7-10 denote read address controllers RAC of the respective time slot switching units.
[0152]
Reference numerals 7-4 and 7-7 denote frame conversion and frame reverse conversion units for adjusting the internal speed of the transmission path I / F 7 to the transmission speed of the transmission path.
[0153]
7-5 and 7-6 are interface circuits that match electrical conditions with the transmission and reception high-speed digital lines, respectively, and 7-11 extracts the synchronization signal from the transmission path reception I / F 7-6 and divides it. This is a frequency dividing circuit that circulates to generate an 8 kHz clock CLK.
[0154]
The terminal 9 on the transmission line side is composed of Tx on the transmission side and Rx on the reception side.
[0155]
In the transmission path I / F 7 of FIG. 6, the write address controller WAC 7-2 has bit number information on the forward highway FHW to be taken by itself, and the data is replaced with the time slot switching unit TSI (A), ( B) Write to 7-1.
[0156]
The data read out in a form that is easily controlled in units of 64 Kbps by the control of the read address controller RAC7-3 is frame-converted by the frame conversion unit 7-4 according to the transmission path speed, for example, 64 Kbps, 128 Kbps, 384 Kbps, etc. The data is sent to the transmission terminal Tx through the transmission I / F 7-5.
[0157]
Here, the terminals 9 (1) to 9 (j) in FIG. 2 are representative of the transmission terminals Tx corresponding to the j transmission lines I / F 7 (1) to 7 (j) and the receiving terminal Rx described later. It is a representation.
[0158]
As a transmission line in the present embodiment, a dedicated line having an I interface that is an interface between ISDN and a user terminal according to the ITU-T standard recommendation, or an ISDN line is assumed.
[0159]
Next, input data from the transmission line will be described.
[0160]
Among the terminals 9 shown in FIG. 2, the signal that has entered the receiving terminal Rx shown in FIG. 6 enters the transmission path reception I / F 7-6, and the synchronization signal is extracted, and the frequency dividing circuit 7-11 generates a clock of 8 KHz. The frequency is divided and sent to the system clock generator SCLK8 for each circuit.
[0161]
In the frame inverse conversion unit 7-7, only the signal data is fetched from the transmission path reception I / F 7-6, and the time slot switching units TSI (A) and (B) 7-8 are sequentially transferred under the control of the write address controller WAC7-9. Write.
[0162]
The read address controller RAC7-10 reads this data bit by bit in synchronization with the clock from the system clock SCLK8 and puts it on a predetermined bit position of the reverse highway BHW of 8 MHz.
[0163]
In the demultiplexer unit DMPX of the sub-rate multiplexer / demultiplexer SUBRATEMPX / DMPX6 in FIG. ) Write to all of 6-7 (1) to (4).
[0164]
The read address controllers RAC6-8 (1) to (4) correspond to the memories MEM (A) and (B) 6-7 (1) to (4), respectively. Each of the read address controllers RAC6-8 (1) to (4) corresponds to the downstream subrate mapping table 6- 9, only the data corresponding to its own controller is read out.
[0165]
As shown on the right side of FIG. 16, the downlink sub-rate mapping table 6-9 is provided for each frame for each downlink highway DHW, and the bit number of the reverse highway BHW to be read is written. The figure shows only one frame.
[0166]
The data sent to the downlink highway DHW enters the downlink highway DHW of the bit multiplexer / demultiplexer BITMPX / DMPX5 in FIG. 4 and is received by the multiframe detectors 5-7 (1) to (8) provided for each route. A synchronization signal is detected. At this time, the multi-frame detectors 5-7 (1) to (8) are given the bit position that becomes the boundary of the route by the reception width register 5-9, in other words, the width of the data bit for each route.
[0167]
Accordingly, the write address controllers WAC5-8 (1) to (8) corresponding to the route receive the information on the head position of the data for each route from the corresponding multi-frame detection units 5-7 (1) to (8). . Write signals output from the write address controllers WAC5-8 (1) to (8) are multiplexed by the multiplexer MPX5-10 so that they do not overlap in time, and the data on the downstream highway is written to the memory MEM5-11. .
[0168]
As shown in the upper diagram of FIG. 17, the position of the synchronization signal for bit multiplexing of each route is input to the memory MEM 5-11 in a random form. In the figure, F1, F2, and F3 represent the synchronization signals in the degenerate mode of the 3-bit pattern already described, and mean the head of data for each route.
[0169]
When the feed signal is bit-multiplexed by the bit multiplexer / demultiplexer BITMPX / DMPX5, the synchronization bits are arranged in F1, F2, and F3 from the first bit for each route as shown in FIG. Therefore, in order to perform bit demultiplexing, that is, bit demultiplexing, it is necessary to rearrange the synchronization bits F1, F2, and F3 at the head position of each route as shown in the lower diagram of FIG.
[0170]
Therefore, the read address controller RAC5-12 reads the contents of the memory MEM5-11 in which the synchronization bits F1, F2, and F3 are randomly arranged for each route as shown in the upper diagram of FIG. Read and transfer to memory MEM (A), (B) 5-13.
[0171]
This is the same as when the upper diagram in FIG. 13 is read from left to right and from top to bottom, so the bit mapping table 5-15 in which the lower table in FIG. Multiplexing, ie bit demultiplexing, is possible.
[0172]
The memories MEM (A) and (B) 5-13 have an 8-bit × 10-frame 80-bit table representing the 0.8 KHz multi-frame shown on the left side of FIG. . The write address controller WAC5-14 writes the data transferred from the memory MEM5-11 to the position instructed by the bit mapping table 5-15 in the memory MEM (A), (B) 5-13.
[0173]
As a result, a bit pattern as shown in the examples of FIGS. 9 and 10 is obtained in the memories MEM (A) and (B) 5-13.
[0174]
As described above, there are two bit mapping tables 5-15. However, like the reception width register 5-9, the memory MEM5-11, the sub-rate mapping tables 6-5 and 6-9, (A), ( The fact that there are two surfaces that are not displayed as B) indicates that one surface has a reserve for instantaneously changing the line configuration setting, but details are omitted.
[0175]
The read address controller RAC5-16 reads the data stored in the memories MEM (A) and (B) 5-13 from the bits B7 to B0 in the left diagram of FIG. In the case of 2 Kbps data, the F bit adding unit 5-17 adds F bit 0 to the B7 bit indicating that there is significant data, and sends it to the 4 Mbps transmission highway SHW.
[0176]
This sending highway SHW is connected to a receiving highway RHW to which a target terminal I / F 2 is connected by a time division switch TSW3.
[0177]
In the data entering the receiving highway RHW of the terminal I / F2 in FIG. 3, the F bit of the time slot allocated by the F bit detection unit 2-18 is detected, and the system clock and the clock are controlled by the write address controller WAC2-17. While synchronizing, only significant data is written to the time slot switching unit TSI (A), (B) 2-19.
[0178]
The read address controller RAC2-20 reads data from the time slot switching units TSI (A), (B) 2-19 according to the transmission rate of the terminal, and sends the data to the demultiplexer DMPX2-21.
[0179]
The signal separated by the demultiplexer DMPX2-21 is converted into an asynchronous signal by the synchronous / asynchronous conversion unit 2-23 if it is an asynchronous terminal, and the phase difference is absorbed by the phase difference absorption unit 2-22 if it is a synchronous terminal. One is selected by the selector SEL2-24 and sent to the data receiving terminal RD through the cable driver CD2-1.
[0180]
On the other hand, when a pseudo carrier signal is adopted as the terminal control signal, the pseudo carrier is detected before and after the main signal, and the carrier detection signal CD is sent to the selector SEL2-25. When the S bit which is a signal bit is used for transmission of the control signal, the S bit is taken out and sent to the selector SEL2-25. The selector SEL2-25 selects one of them and sends it to the carrier detection signal terminal CD through the cable driver CD2-2.
[0181]
As for the clock to be sent to the terminal, the variable frequency divider 2-6 receives the clock signals of 5.376 MHz and 8.064 MHz from the system clock SCLK8, and divides this to generate a necessary clock to generate a cable driver. The data is sent to the clock terminal CLK through CD2-3.
[0182]
According to the present invention, when a signal bit of a data signal from a plurality of data terminal apparatuses DTE is put on a digital channel having a preset basic speed, a frame on which the signal bit is placed can be identified by a status bit. Economical time-division multiplexing device that facilitates bit multiplexing processing Multiplexing method Can be realized.
[0183]
According to the present invention, since the frame on which the signal bit is carried can be identified by the status bit, bit multiplexing does not become complicated even if the connection is switched by the time division switch.
[Brief description of the drawings]
FIG. 1 is a system configuration diagram according to an embodiment of the present invention.
2 is a block diagram showing a configuration of a time division multiplexing apparatus in FIG. 1. FIG.
FIG. 3 is a block diagram showing a configuration of a terminal interface in FIG. 2;
4 is a block diagram showing a configuration of a bit multiplexer / demultiplexer in FIG. 2. FIG.
5 is a block diagram showing a configuration of a sub-rate multiplexer / demultiplexer in FIG. 2. FIG.
6 is a block diagram showing a configuration of a transmission path interface in FIG. 2. FIG.
FIG. 7 is an explanatory diagram showing a relationship between a frame, a multi-frame, and 1.2 Kbps data.
FIG. 8 is an explanatory diagram showing frames and multi-frames, and 1.2 Kbps data transmission using them.
FIG. 9 is an explanatory diagram showing a case where 1.2 Kbps data is placed on a multiframe.
FIG. 10 is an explanatory diagram when 8 Kbps data is placed in a multi-frame.
FIG. 11 is an explanatory diagram when data of 1.2 Kbps system and 8 Kbps system is transmitted using multiframes.
FIG. 12 is an explanatory diagram in which bit multiplexing is performed using multiframes.
FIG. 13 is an explanatory diagram of a bit mapping table on a memory.
FIG. 14 is an explanatory diagram of an initial synchronization establishment pattern and a degenerate synchronization pattern.
FIG. 15 is a state transition diagram between respective modes for establishing and maintaining synchronization;
FIG. 16 is an explanatory diagram of uplink and downlink sub-rate mapping tables.
FIG. 17 is an explanatory diagram of data on a memory for performing bit demultiplexing;
FIG. 18 is a block diagram of a bus connection system showing an example of conventional technology.
FIG. 19 is a block diagram of a time division switch system showing an example of the prior art.
[Explanation of symbols]
10 Data terminal equipment
20 Time division multiplexing equipment
30 High-speed digital line
2 Terminal interface
3 Time division switch
4 Multiplexer
5-bit multiplexer / demultiplexer
6 Sub-rate multiplexer / demultiplexer
7 Transmission line interface
2-7, 2-22 Phase difference absorption circuit
2-8 Asynchronous / synchronous converter
2-23 Synchronous / Asynchronous Conversion Unit
2-10 Pseudo carrier control unit
2-26 Pseudo carrier detector
2-11, 2-15, 5-6, 5-10, 6-3 Multiplexer
2-21 Demultiplexer
2-12, 2-17, 5-2, 5-8, 5-14, 6-1, 6-6,
7-2, 7-9 Write address controller
2-14, 2-20, 5-4, 5-12, 5-16, 6-4,
6-8, 7-3, 7-10 Read address controller
2-13, 2-19, 7-1, 7-8 Time slot replacement section
2-16, 5-17 F bit addition part
2-18, 5-1 F bit detector
5-3, 5-11, 5-13, 6-2, 6-7 Memory
5-5 Transmission bit synchronization pattern generator
5-7 Multiframe detector
5-9 Receive width register
5-15 Bit mapping table
6-5 Sub-rate mapping table (uplink)
6-9 Sub-rate mapping table (downlink)
7-4 Frame converter
7-7 Frame inverse transform section
7-5 Transmission path transmission interface
7-6 Transmission path reception interface

Claims (2)

In a multiplexing method of a time division multiplexing apparatus for multiplexing and transmitting data from a plurality of data terminal apparatuses by a multiplexing unit,
State with preset providing a multi-frame having a first period of an integral fraction of the frame period of the digital channels of the basic rate, indicating that it contains the signal data from the data terminal equipment on each frame in the multiframe provided bit, the data from the data terminal equipment the state bit of the frame is turned on when carrying the frames in the multiframe,
In the multiplexing unit, mapping the in multiframe, from the frame in which the status bit is on, according to what only the removed signal bit data signals, written in the mapping table from the data terminal equipment A multiplexing method for a time division multiplexing apparatus , wherein multiplexing is performed in bit units. In a multiplexing method of a time division multiplexing apparatus for performing time division switching connection with data from a plurality of data terminal apparatuses by using a time division switch and then multiplexing and transmitting by a multiplexing unit,
State with preset providing a multi-frame having a first period of an integral fraction of the frame period of the digital channels of the basic rate, indicating that it contains the signal data from the data terminal equipment on each frame in the multiframe provided bit, the data from the data terminal equipment the state bit of the frame is turned on when carrying the frames in the multiframe,
In the time division switch performs time division switching connection in a digital channel of the basic rate,
In the multiplexing unit, mapping the in multiframe, from the frame in which the status bit is on, according to what only the removed signal bit data signals, written in the mapping table from the data terminal equipment A multiplexing method for a time division multiplexing apparatus , wherein multiplexing is performed in bit units.

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