JP3624344B2 - Reference frequency generator - Google Patents

Description

となる。
【００２５】
従って、分周器３の出力である基準周波数信号１０８の周波数”ｆｒ”はシステムクロック信号１０３を式（１）の分周比で分周したものであるから、

となる。
【００２６】
また、”ｎｃ＝ｔｇ×ｆｃ”であるから式（２）に代入して、

となる。
【００２７】
すなわち、システムクロック信号１０３の周波数の誤差が相殺されて設定された基準周波数になるので、精度等の低いシステムクロックを用いても高精度の基準周波数信号を発生させることが可能になる。
【００２８】
ここで、さらに、具体的な数値を用いて説明する。例えば、”ｆｃ＝２４［ＭＨｚ］”、”ｆＤ１＝１２［ＫＨｚ］”、”ｔｇ＝０．１０４２［ｍｓｅｃ］（＝１／９６００［ｓｅｃ］）とすると、公称カウント値”ｎｃ”は、

となる。
【００２９】
また、データセレクタ回路４の出力値”ｋ”は、

となる。
【００３０】
ところで、システムクロック信号１０３の周波数が公称周波数”ｆｃ”に一致せず誤差があり、カウンタ回路２の実測カウント値が”ｎ＝２４９０”であったとする。このため、分周器３の分周比”ｎ／ｋ”は、

となる。
【００３１】
また、実際のシステムクロック信号１０３の周波数”ｆｓ”は、実測カウント値”ｎ”から逆算して、

である。
【００３２】
従って、分周器３の出力である基準周波数信号１０８の周波数”ｆｒ”は式（７）の周波数のシステムクロック信号１０３を式（６）の分周比で分周したものであるから、

となる。
【００３３】
すなわち、システムクロック信号１０３の周波数の誤差が相殺され設定された基準周波数になるので、精度等の低いシステムクロックを用いても高精度の基準周波数信号を発生させることが可能になる。
【００３４】
この結果、システムクロック信号１０３の実際の周波数をカウントして分周器３の分周比を調整することにより、システムクロック信号１０３の公称周波数からの誤差が相殺されるので、精度等の低いシステムクロックを用いても高精度の基準周波数信号を発生させることが可能になる。また、基準周波数発生回路には発振周波数精度の高い水晶振動子が不要なのでコストアップも防止できる。
【００３５】
また、選択信号１０５によりデータセレクタ回路４に接続された複数のデータ信号を選択することにより、複数個の基準周波数を切り換えて出力させることが可能になる。
【００３６】
なお、図１に示す実施例ではシステムクロック信号１０３で直接カウンタ回路２をカウントしているが前段に分周器を設けてシステムクロック信号を適宜分周した分周信号をカウントしても構わない。このような構成にすることにより、カウンタ回路２が低速であっても良くなるのでコストダウンが可能になる。
【００３７】
また、選択信号１０５によりデータセレクタ回路４を制御して複数のデータ信号の内一を選択しているが、発生させる基準周波数が１つである場合はデータ信号を分周器の”ｋ”入力端子に直接接続すれば良いのでデータセレクタ回路４は不要になる。
【００３８】
また、図１に示す実施例ではゲート信号１０２を既知の時間”ｔｇ”だけ”１”になる信号としているが、カウンタ回路２のカウントを動作させるコマンドとカウントを停止させるコマンドとを外部から供給して、既知の時間”ｔｇ”だけカウンタ回路２にカウント動作をさせるものであっても構わない。このような構成にすることにより、ゲート信号ラインとコマンド通信ラインを兼用することができ、コストダウンが可能になる。
【００３９】
また、データ信号１０４ａ〜１０４ｃに関しては公称周波数”ｆｃ”、既知の時間”ｔｇ”及び発生させたい基準周波数”ｆＤｉ”から一意に算出できる値であるので内部のレジスタ回路等の記憶手段や、外部のレジスタ回路やＲＯＭ等の記憶手段に格納しておけば良い。
【００４０】
また、ゲート信号１０２を外部から供給する手段としてはパーソナルコンピュータ、信号発生器等既知の時間”ｔｇ”を出力できるものであればどのような装置であっても構わない。
【００４１】
また、データ信号１０４ａ〜１０４ｃとしてはそれそれ”ｎｃ×ｆＤ１／ｆｃ”，”ｎｃ×ｆＤ２／ｆｃ”及び”ｎｃ×ｆＤ３／ｆｃ”としていたが、”ｎｃ＝ｔｇ×ｆｃ”を代入すれば、”ｔｇ×ｆＤ１”、”ｔｇ×ｆＤ２”及び”ｔｇ×ｆＤ３”となるので、これらの値であっても構わない。
【００４２】
【発明の効果】
以上説明したことから明らかなように、本発明によれば次のような効果がある。
請求項１，５及び請求項６の発明によれば、システムクロック信号の実際の周波数をカウントして分周器の分周比を調整することにより、システムクロック信号の公称周波数からの誤差が相殺されるので、精度等の低いシステムクロックを用いても高精度の基準周波数信号を発生させることが可能になる。また、基準周波数発生回路には発振周波数精度の高い水晶振動子が不要なのでコストアップも防止できる。
【００４３】
また、請求項２の発明によれば、データセレクタ回路に接続された複数のデータ信号を選択することにより、複数個の基準周波数を切り換えて出力させることが可能になる。
【００４４】
また、請求項３の発明によれば、システムクロック信号を適宜分周した分周信号でカウンタ回路をカウントすることにより、カウンタ回路が低速であっても良くなるのでコストダウンが可能になる。
【００４５】
また、請求項４の発明によれば、カウンタ回路のカウントを動作させるコマンドとカウントを停止させるコマンドとを外部から供給して、既知の時間だけカウンタ回路にカウント動作をさせることにより、ゲート信号ラインとコマンド通信ラインを兼用することができ、コストダウンが可能になる。
【図面の簡単な説明】
【図１】本発明に係る基準周波数発生回路の一実施例を示す構成図である。
【図２】従来の基準信号発生回路の一例を示す構成ブロック図である。
【符号の説明】
１，３ 分周器
２ カウンタ回路
４ データセレクタ回路
１００，１０３ システムクロック信号
１０１，１０８ 基準周波数信号
１０２ ゲート信号
１０４ａ，１０４ｂ，１０４ｃ データ信号
１０５ 選択信号
１０６，１０７ 出力信号[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a reference frequency generation circuit used in a signal conditioner that performs signal processing on outputs from various sensor circuits, and particularly generates a high-precision reference frequency signal even when a system clock signal with low accuracy is used. The present invention relates to a reference frequency generating circuit that can
[0002]
[Prior art]
In a conventional reference signal generation circuit, a system clock signal is appropriately divided by a frequency divider to generate a reference frequency signal. For example, the generated reference frequency signal is used to determine the integration period when the output signal from the sensor circuit is integrated in the signal conditioner.
[0003]
FIG. 2 is a block diagram showing an example of such a conventional reference signal generating circuit. In FIG. 2, 1 is a frequency divider, 100 is a system clock signal, and 101 is a generated reference frequency signal.
[0004]
The system clock signal 100 is input to the frequency divider 1, and the reference frequency signal 101 is output from the frequency divider 1.
[0005]
[Problems to be solved by the invention]
However, one of the reasons for integrating the output signal of the sensor circuit in the signal conditioner is for normal mode rejection of the commercial frequency. In order to maximize the effect, the integration period must be an integral multiple of the commercial frequency. There must be.
[0006]
Since this integration period is determined by the above-described reference frequency signal 101, the accuracy of the reference frequency signal 101 that is generated when there is an error in the frequency of the system clock signal 100 that is the basis of the reference frequency signal 101 is reduced to the commercial frequency. There is a problem in that the normal mode rejection ratio is reduced.
[0007]
In order to prevent the accuracy of the reference frequency signal 101 from being lowered, it is sufficient to generate the system clock signal 100 using a crystal resonator having a high oscillation frequency accuracy.
Therefore, the problem to be solved by the present invention is to realize a reference frequency generating circuit capable of generating a highly accurate reference frequency signal even when a system clock having a low accuracy is used.
[0008]
[Means for Solving the Problems]
In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a reference frequency generation circuit used in a signal conditioner that performs signal processing,
A counter circuit that counts a known gate signal with a system clock signal; and
A frequency divider that divides the system clock signal by setting the ratio of the count value “n” of the counter circuit to the input data signal “k” as the frequency division ratio “n / k”. Since the error from the nominal frequency of the clock signal is canceled out, it is possible to generate a highly accurate reference frequency signal even using a system clock with low accuracy. Further, since the reference frequency generating circuit does not require a crystal oscillator with high oscillation frequency accuracy, it is possible to prevent an increase in cost.
[0009]
The invention according to claim 2
In the reference frequency generation circuit according to the invention of claim 1,
By providing a data selector circuit that selects one of a plurality of data signals and inputs the data signal to the frequency divider, it is possible to switch and output a plurality of reference frequencies.
[0010]
The invention described in claim 3
In the reference frequency generation circuit according to the invention of claim 1,
The counter circuit is
By counting the known gate signal with a frequency-divided signal obtained by dividing the system clock signal, the counter circuit can be operated at a low speed, so that the cost can be reduced.
[0011]
The invention according to claim 4
In the reference frequency generation circuit according to the invention of claim 1,
A command for operating the counter circuit and a command for stopping the counting are supplied from the outside, and the counter circuit performs a counting operation for a known time so that the gate signal line and the command communication line are combined. And cost reduction is possible.
[0012]
The invention according to claim 5
In the reference frequency generation circuit according to the invention of claim 1,
When the nominal frequency of the system clock signal is “fc”, the nominal count value calculated when counting the known gate signal at the nominal frequency is “nc”, and the frequency of the reference frequency signal is “fD”,
Since the value of the data signal is “nc × fD / fc”, an error from the nominal frequency of the system clock signal is canceled out. Therefore, even if a system clock with low accuracy is used, a high-precision reference frequency signal can be obtained. Can be generated. Further, since the reference frequency generating circuit does not require a crystal oscillator with high oscillation frequency accuracy, it is possible to prevent an increase in cost.
[0013]
The invention described in claim 6
In the reference frequency generation circuit according to the invention of claim 1,
When the gate time of the known gate signal is “tg” and the frequency of the reference frequency signal is “fD”,
Since the value of the data signal is “tg × fD”, an error from the nominal frequency of the system clock signal is canceled out, so that a high-precision reference frequency signal is generated even when a low-precision system clock is used. It becomes possible. Further, since the reference frequency generating circuit does not require a crystal oscillator with high oscillation frequency accuracy, it is possible to prevent an increase in cost.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a reference frequency generating circuit according to the present invention. In FIG. 1, 2 is a counter circuit, 3 is a division ratio of “n / k”, and it is possible to input values of “n” and “k” from the outside. In other words, the division ratio is set externally. Possible dividers, 4 is a data selector circuit, 102 is a known gate signal supplied from the outside, 103 is a system clock signal, 104a, 104b and 104c are known data signals for determining a division ratio, 105 Is a selection signal, 106 and 107 are output signals, and 108 is a reference frequency signal.
[0015]
The gate signal 102 is connected to the gate input terminal of the counter circuit 2, and the system clock signal 103 is connected to the clock input terminal of the counter circuit 2 and the clock input terminal of the frequency divider 3.
[0016]
The data signals 104 a to 104 c are connected to the respective input terminals of the data selector circuit 4, and the selection signal 105 is connected to the control terminal of the data selector circuit 4.
[0017]
The output signal 106 of the counter circuit 2 is connected to the “n” input terminal of the frequency divider 3, and the output signal 107 of the data selector circuit 4 is connected to the “k” input terminal of the frequency divider 3. Further, the frequency divider 3 outputs a reference frequency signal 108.
[0018]
Here, the operation of the embodiment shown in FIG. 1 will be described. The counter circuit 2 counts the system clock signal 103 by the gate time of the gate signal 102 and supplies the count value to the frequency divider 3 as “n” of the frequency division ratio “n / k”.
[0019]
On the other hand, the data selector circuit 4 selects one of the data signals 104a to 104c based on the selection signal 105 and supplies the selection signal to the frequency divider 3 as “k” of the frequency division ratio “n / k”. .
[0020]
Finally, the frequency divider 3 divides the system clock signal 103 by the frequency division ratio “n / k” and outputs it as the reference frequency signal 108.
[0021]
For example, the gate signal 102 is a signal that becomes “1” only for a known time “tg [sec]”, the frequency of the system clock signal 103 is “fs [Hz]”, and the data signals 104 a, 104 b, and 104 c are “nc ×” respectively. fD1 / fc ”,“ nc × fD2 / fc ”, and“ nc × fD3 / fc ”.
[0022]
However, “fc” is the nominal frequency of the system clock signal 103, “nc (= tg × fc)” is a nominal count value calculated when the nominal frequency is counted by “tg”, and “fDi (i = 1 to 3). [Hz] "is the frequency of the reference frequency signal to be generated.
[0023]
The actual count value “n” in the counter circuit 2 is “n = fs × tg”, and if the data signal 104a is selected by the data selector circuit 4, “nc × fD1 / fc = k” is output.
[0024]
Under such conditions, the frequency division ratio “n / k” of the frequency divider 3 is

It becomes.
[0025]
Therefore, the frequency “fr” of the reference frequency signal 108 that is the output of the frequency divider 3 is obtained by dividing the system clock signal 103 by the frequency division ratio of the equation (1).

It becomes.
[0026]
Also, since “nc = tg × fc”, it is substituted into the equation (2),

It becomes.
[0027]
That is, since the frequency error of the system clock signal 103 is canceled and the set reference frequency is obtained, it is possible to generate a high-accuracy reference frequency signal even when a system clock with low accuracy is used.
[0028]
Here, further description will be made using specific numerical values. For example, if “fc = 24 [MHz]”, “fD1 = 12 [KHz]”, “tg = 0.1042 [msec] (= 1/9600 [sec]), the nominal count value“ nc ”is

It becomes.
[0029]
The output value “k” of the data selector circuit 4 is

It becomes.
[0030]
By the way, it is assumed that the frequency of the system clock signal 103 does not match the nominal frequency “fc” and there is an error, and the actually measured count value of the counter circuit 2 is “n = 2490”. Therefore, the frequency division ratio “n / k” of the frequency divider 3 is

It becomes.
[0031]
Further, the frequency “fs” of the actual system clock signal 103 is calculated backward from the actually measured count value “n”.

It is.
[0032]
Therefore, the frequency “fr” of the reference frequency signal 108 that is the output of the frequency divider 3 is obtained by dividing the system clock signal 103 having the frequency of Expression (7) by the frequency dividing ratio of Expression (6).

It becomes.
[0033]
That is, since the frequency error of the system clock signal 103 is canceled out and becomes a set reference frequency, it is possible to generate a highly accurate reference frequency signal even when a system clock with low accuracy is used.
[0034]
As a result, since the error from the nominal frequency of the system clock signal 103 is canceled by counting the actual frequency of the system clock signal 103 and adjusting the frequency division ratio of the frequency divider 3, the system with low accuracy or the like Even with a clock, it is possible to generate a highly accurate reference frequency signal. Further, since the reference frequency generating circuit does not require a crystal oscillator with high oscillation frequency accuracy, it is possible to prevent an increase in cost.
[0035]
Further, by selecting a plurality of data signals connected to the data selector circuit 4 by the selection signal 105, it becomes possible to switch and output a plurality of reference frequencies.
[0036]
In the embodiment shown in FIG. 1, the counter circuit 2 is directly counted by the system clock signal 103. However, a frequency divider signal may be counted by appropriately dividing the system clock signal by providing a frequency divider in the preceding stage. . By adopting such a configuration, the counter circuit 2 can be operated at a low speed, so that the cost can be reduced.
[0037]
In addition, the data selector circuit 4 is controlled by the selection signal 105 to select one of a plurality of data signals. If there is only one reference frequency to be generated, the data signal is input to the frequency divider “k”. The data selector circuit 4 is unnecessary because it is sufficient to connect directly to the terminals.
[0038]
In the embodiment shown in FIG. 1, the gate signal 102 is a signal that becomes “1” for a known time “tg”, but a command for operating the counter circuit 2 and a command for stopping the count are supplied from the outside. Then, the counter circuit 2 may be allowed to perform a counting operation for a known time “tg”. With such a configuration, the gate signal line and the command communication line can be used together, and the cost can be reduced.
[0039]
Since the data signals 104a to 104c are values that can be uniquely calculated from the nominal frequency “fc”, the known time “tg”, and the reference frequency “fDi” to be generated, storage means such as an internal register circuit, It may be stored in a storage means such as a register circuit or a ROM.
[0040]
As a means for supplying the gate signal 102 from the outside, any device such as a personal computer or a signal generator capable of outputting a known time “tg” may be used.
[0041]
The data signals 104a to 104c are “nc × fD1 / fc”, “nc × fD2 / fc”, and “nc × fD3 / fc”, respectively, but if “nc = tg × fc” is substituted, Since “tg × fD1”, “tg × fD2”, and “tg × fD3”, these values may be used.
[0042]
【The invention's effect】
As is apparent from the above description, the present invention has the following effects.
According to the first, fifth and sixth aspects of the present invention, the error from the nominal frequency of the system clock signal is canceled by counting the actual frequency of the system clock signal and adjusting the division ratio of the divider. Therefore, it is possible to generate a highly accurate reference frequency signal even using a system clock with low accuracy. Further, since the reference frequency generating circuit does not require a crystal oscillator with high oscillation frequency accuracy, it is possible to prevent an increase in cost.
[0043]
According to the invention of claim 2, it is possible to switch and output a plurality of reference frequencies by selecting a plurality of data signals connected to the data selector circuit.
[0044]
According to the invention of claim 3, by counting the counter circuit with the frequency-divided signal obtained by appropriately dividing the system clock signal, the counter circuit can be operated at a low speed, so that the cost can be reduced.
[0045]
According to a fourth aspect of the present invention, a command for operating the counter circuit and a command for stopping the count are supplied from the outside, and the counter circuit performs the counting operation for a known time, thereby causing the gate signal line And the command communication line can be used together, and the cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a reference frequency generating circuit according to the present invention.
FIG. 2 is a block diagram showing an example of a conventional reference signal generation circuit.
[Explanation of symbols]
1, 3 Frequency divider 2 Counter circuit 4 Data selector circuit 100, 103 System clock signal 101, 108 Reference frequency signal 102 Gate signal 104a, 104b, 104c Data signal 105 Selection signal 106, 107 Output signal

Claims (6)

In a reference frequency generation circuit used in a signal conditioner that performs signal processing,
A counter circuit that counts a known gate signal with a system clock signal;
And a frequency divider that divides the system clock signal by setting a ratio of the count value “n” of the counter circuit to the input data signal “k” as a frequency division ratio “n / k”. Reference frequency generation circuit. 2. The reference frequency generating circuit according to claim 1, further comprising a data selector circuit that selects one of a plurality of data signals and inputs the selected data signal to the frequency divider. The counter circuit is
2. The reference frequency generating circuit according to claim 1, wherein the known gate signal is counted by a frequency-divided signal obtained by dividing the system clock signal. 2. The reference frequency generating circuit according to claim 1, wherein a command for operating counting of the counter circuit and a command for stopping counting are supplied from the outside, and the counter circuit is caused to perform a counting operation for a known time. When the nominal frequency of the system clock signal is “fc”, the nominal count value calculated when the nominal frequency is counted by the known gate signal is “nc”, and the frequency of the reference frequency signal is “fD”,
2. The reference frequency generation circuit according to claim 1, wherein the value of the data signal is “nc × fD / fc”. When the gate time of the known gate signal is “tg” and the frequency of the reference frequency signal is “fD”,
2. The reference frequency generation circuit according to claim 1, wherein the value of the data signal is “tg × fD”.

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