JP3625122B2 - A / D converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an A / D converter, and more particularly to a sigma delta type A / D converter.
[0002]
[Prior art]
In the A / D converter, when only a signal is extracted from an input signal carrying excessive noise, the input signal is usually integrated to obtain an average value. An integral A / D converter or a sigma delta converter has been used as such an A / D converter.
[0003]
The integration type A / D converter performs integration by an analog circuit, and the sigma delta type A / D converter performs integration by a digital filter. More specifically, the sigma-delta A / D converter includes a modulator including an analog integrator and a comparator that outputs a binary signal by comparing its output with a reference value, and integrates the modulation output with a digital filter. It is supposed to do.
[0004]
[Problems to be solved by the invention]
However, the integration type A / D converter generates various errors during the A / D conversion and has a limit in improving the resolution. On the other hand, with the sigma-delta A / D converter, the resolution is improved by 10 to 100 times. However, if noise is added to the input signal near full scale, the internal circuit may be noisy even if the average value of the signal is less than the limit value. , The output value is erroneously saturated, so that there is a drawback in that the dynamic range cannot be used effectively because a sufficient margin from full scale must be used in actual use.
[0005]
An object of the present invention is to provide a sigma-delta A / D converter that can effectively use a dynamic range.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, an A / D converter according to a first aspect of the present invention provides a sigma delta, even if the sigma delta A / D converter is saturated on the input side of the sigma delta A / D converter. A first integrator having a capacitor having a capacitance value for holding an input signal until the type A / D converter is in a linear operation, and a gain circuit for increasing the gain of the output of the first integrator are connected. It is characterized by that.
[0008]
According to a second aspect of the present invention, in the first aspect of the invention, the sigma-delta A / D converter includes a second integrator having a capacitor having a smaller capacitance value than the capacitor of the first integrator, A comparator that compares the output of the integrator with a reference value, a D flip-flop that uses the output of the comparator as a D input, a clock source that supplies a clock to the clock terminal of the D flip-flop, and an output of the D flip-flop A third resistor that feeds back to the input of the second integrator, and a digital filter connected to the output terminal of the D flip-flop. The second integrator, comparator, D flip-flop, and clock source are modulated. Make up the vessel.
[0009]
According to such a configuration of the present invention, even if saturation occurs in a part of the sigma-delta A / D converter (for example, a modulator) due to noise riding on an input signal near the full scale of the sigma-delta A / D converter. Since the input signal is sufficiently held by the first integrator having a large capacity, a digital value equal to the input signal can be obtained if the sigma-delta A / D converter portion returns to the linear region by feedback during that time. The gain is reduced by the first integrator, but this is corrected by the gain circuit.
[0010]
In other words, in a feedback system including an integrator (in this case, the modulator part), if the integrator placed in the foremost stage does not saturate, the output value of the entire system will not be saturated even if it is saturated at any point in the subsequent stage. Since it becomes equal to the integral value of the input signal, an accurate value can be obtained even if the output of the modulator is integrated by a digital filter.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the embodiment of the present invention shown in FIG. 1 will be described. In the figure, 1 is an input signal source, and 2 is a first integrator. Reference numeral 3 denotes a gain circuit that increases the output of the first integrator 2. Reference numeral 4 denotes a sigma delta A / D converter, which includes a modulator 4a and a digital filter 4b.
[0012]
The first integrator 2 includes an operational amplifier 5, a capacitor C _O having a large capacitance value connected between its inverting terminal (−) and the output terminal, and a feedback resistor R _O. The non-inverting terminal (+) of the operational amplifier 5 is connected to a DC voltage, and the inverting terminal (−) is connected to the signal source 1.
[0013]
The gain circuit 3 includes a first resistor R1 connected to the output terminal of the first integrator 2 and a feedback second resistor R2. The values of these resistors are selected in the relationship of R1 <R2, and specifically, it is not particularly limited to this, but R1 is set to 1/10 of R2. As a result, the gain becomes R2 / R1 = 10, and the gain is sufficiently increased.
[0014]
The modulator 4 a of the sigma-delta A / D converter 4 includes two integrators 11 and 12, a comparator 8, a D flip-flop 9, and a clock source 11. The integrator 11 is composed of an operational amplifier 6 and a capacitor C ₁ Tokyo, integrator 12 is an operational amplifier 7 and the capacitor C ₂ Prefecture. The values of these capacitors C ₁ and C ₂ are sufficiently smaller than that of the capacitor _CO . R3 is a third resistor, and R4 is a fourth resistor for feedback. The resistance value of R3 and the resistance value of R4 are equal, and the resistance value of R2 is also equal. The non-inverting terminals of the operational amplifiers 11 and 12 are each connected to a predetermined DC voltage.
[0015]
Reference numeral 8 denotes a comparator. The output of the integrator 12 is input to the (−) terminal, and the reference voltage Vref is input to the (+) terminal. The comparator 8 outputs a high level if the input at the (−) terminal is smaller than Vref, and a low level if the input is larger than Vref. The output of the comparator 9 is given to the D terminal of the D flip-flop 9. The D flip-flop 9 is operated by the clock CLK from the clock source 11.
[0016]
The -Q output is fed back to the first integrator 2 and the integrator 12 via the resistors R0 and R4, respectively, and the Q output is fed back to the integrator 11 via the resistor R2. The fed -Q output and Q output are respectively integrated after being subtracted from the input signal at points (a), (b), and (c). The Q output of the D flip-flop is supplied to the digital filter 4b at the next stage. The digital filter 4b has a D flip-flop 10, and the clock CLK from the clock source 11 is applied to its clock terminal.
[0017]
In the present embodiment configured as described above, since the integrator 2 has a large time constant due to the large capacitance C 2 _O , the time for holding the input is long. Therefore, even if the modulator 4 a is saturated due to noise on a signal near full scale, the input signal is held by the first integrator 2. In the meantime, if the modulator 4a returns (returns) from the saturation region to the linear region by feedback, the signal held in the integrator 2 is modulated in the linear region, so that the output as a whole is the integrated value of the input. Is equal to The input signal whose gain has been reduced by the first integrator 2 is input to the Σ-delta A / D converter 4 in a form in which the gain has been raised (returned to the original value) by the gain circuit 3 at the next stage.
[0018]
【The invention's effect】
As described above, according to the present invention, even if saturation occurs in the sigma delta A / D converter portion due to noise on the input signal near the full scale of the sigma delta A / D converter, The correct output is obtained. In other words, in the present invention, the dynamic range of the sigma-delta A / D converter can be expanded and effectively used.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of an A / D converter of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Signal source 2 1st integrator 3 Gain circuit 4 Sigma delta type A / D converter 4a Modulator 4b Digital filter

Claims (2)

Even if the sigma delta type A / D converter is saturated, the input side of the sigma delta type A / D converter has a capacitance value for holding the input signal until the sigma delta type A / D converter becomes a linear operation. An A / D converter comprising: a first integrator having a capacitor; and a gain circuit for increasing a gain of an output of the first integrator. The sigma-delta A / D converter includes a second integrator having a capacitor having a smaller capacitance value than the capacitor of the first integrator, a comparator for comparing the output of the second integrator with a reference value, A D flip-flop having the output of the comparator as a D input; a clock source for supplying a clock to the clock terminal of the D flip-flop; and a third resistor for feeding back the output of the D flip-flop to an input of a second integrator; wherein it is comprised a digital filter connected to the output terminal of the D flip-flop, claim wherein the second integrator, a comparator, a D flip-flop, the clock source is characterized in that it constitutes a modulator 1 A / D converter described in

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