JP3628286B2 - IP header generator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for generating an IP header capable of arbitrarily changing an address with a simple configuration.
[0002]
[Prior art]
When evaluating a network that performs data transmission according to the TCP / IP protocol and a communication device such as a router that constitutes the data, an IP packet is given to the measurement target, and the IP packet is correctly transmitted to a desired destination. It may be measured whether or not it is done.
[0003]
When performing such measurement, it is necessary to generate an IP header in which an arbitrary address is inserted in the source address field and the destination address field.
[0004]
The IP header of the IP packet currently used for communication has a length of 32 bits (4 bytes) × N (N is an integer of 5 or more) as shown in FIG. To the 16th byte of the source address field Fsa is inserted with the source IP address SA, and the destination address field Fda of the 17th to 20th bytes is inserted with the destination IP address DA. .
[0005]
The checksum field CS of the entire IP header is inserted into the checksum field Fcs from the 11th byte to the 12th byte for error detection.
[0006]
This checksum value CS is obtained by obtaining a 1's complement sum for every 16 bits for all data except the checksum field Fcs of the IP header and taking the 1's complement of the final result of the complement sum. .
[0007]
“16's complement sum” of two 16-bit values A and B indicates the addition result (16 bits) when the values A and B are not added and carry, and when the carry is performed , A value obtained by adding “1” to the addition result up to 16 bits. The “1's complement” of the value C indicates a value obtained by inverting each bit of the value C.
[0008]
The option field Fop after the 21st byte is a portion where test data or the like is inserted, and its length is variable (may be 0 bytes). The putting field Fpd following this option field Fop is an option field. This field is used to fill up the IP header so that the entire length of the IP header is an integral multiple of 32 bits even when the Fop length is not 0 or an integral multiple of 32 bits (4 bytes).
[0009]
In this putting field Fpd, data of all 0 bits is inserted so as not to affect the checksum calculation result. A value L indicating the length of the entire IP header is inserted into the header length field Fh from the 5th bit to the 8th bit from the beginning.
[0010]
Further, in the 3rd to 4th byte fields of the IP header, the packet length indicating the length of the entire IP packet including the length of the IP header and the length of the data field (not shown) following the IP header is added. Is inserted.
[0011]
Conventionally, an IP header generator 10 shown in FIG. 7 is used to generate an IP header in which the IP addresses DA and SA can be arbitrarily changed in such a format.
[0012]
The IP header generator 10 includes a primary header generator 11, an address insertion unit 12, a header length extraction unit 13, a calculation unit 14, a variable delay unit 15, and a checksum insertion unit 16.
[0013]
The primary header generation unit 11 selectively outputs primary headers H1a to H1c having different lengths as necessary, for example, as illustrated in (a) to (c) of FIG.
[0014]
In these primary headers H1a to H1c, data of all bits 0 is inserted in the checksum field Fcs, and dummy data (for example, all bits 0) is inserted in the source address field Fsa and the destination address field Fda. It is common.
[0015]
The primary header H1a is the shortest (20 bytes long) that does not include the option field Fop, and the primary header H1b has a total length of 4 bytes (24 bytes in total for the header), including the option field Fop and the putting field Fpd. The primary header H1c has a combined length of the option field Fop and the putting field Fpd of 8 bytes (28 bytes in total for the header).
[0016]
The primary header generator 11 sequentially outputs the primary headers H1a to H1c in a predetermined width (for example, 1 byte width) in synchronization with a clock signal having a predetermined frequency (not shown).
[0017]
The address insertion unit 12 inserts desired IP addresses SA and DA into the source address field Fsa and the destination address field Fda of the primary header H1 output from the primary header generation unit 11, respectively. The header in which SA and DA are inserted is output as the secondary header H2.
[0018]
The header length extraction unit 13 extracts the header length L inserted in the header length field Fh of the secondary header H2 output from the address insertion unit 12, and outputs the header length L to the calculation unit 14 and the variable delay unit 15.
[0019]
The calculation means 14 performs a checksum calculation on the data corresponding to the header length L from the head of the secondary header H2 output from the address insertion means 12.
[0020]
The variable delay means 15 delays the secondary header H2 output from the address insertion means 12 by a time Td corresponding to (L-10) bytes with respect to the header length L. In the checksum insertion means 16, the calculation means The checksum value CS calculated by 14 is correctly inserted into the checksum field Fcs of the secondary header H2.
[0021]
If the time required for the primary header generating means 11 to output one byte of the primary header H1 is Tr, the delay time Td of the variable delay means 15 can be expressed as (L-10) Tr.
[0022]
Here, for example, when the primary header H1a not including the option field Fop described above is output from the primary header generator 11, the IP addresses SA and DA are inserted into the primary header H1a as shown in FIG. Further, the checksum calculation is performed on the entire secondary header H2a by the calculation means 14, and the checksum value CSa obtained by the calculation is output to the checksum insertion means 16 as shown in FIG.
[0023]
On the other hand, the secondary header H2a output from the address insertion unit 12 is transmitted by the variable delay unit 15 for a time Td = (La-10) Tr corresponding to (La-10) bytes as shown in FIG. The data is output to the checksum insertion means 16 with a delay. In this case, since the header length La is 20 bytes, the delay time Td is 10 · Tr.
[0024]
Thus, the checksum field Fcs of the secondary header H2a delayed by the time Td according to the header length La is input to the checksum insertion unit 16 at the timing when the checksum value CSa is calculated by the calculation unit 14. As a result, the checksum insertion means 16 outputs an IP header Hip in which the checksum value CSa is inserted into the checksum field Fcs, as shown in FIG.
[0025]
When the primary header H1b including the option field Fop is output from the primary header generator 11, the source address SA and the destination address DA are inserted into the primary header H1b as shown in FIG. A checksum operation is performed on the entire secondary header H2b, and the checksum value CSb is obtained and output to the checksum insertion means 16 as shown in FIG.
[0026]
Further, the secondary header H2b is delayed by Td = (Lb−10) Tr by the variable delay means 15 as shown in FIG. In this case, since the header length Lb is 24 bytes, the delay time Td is 14 · Tr.
[0027]
Thus, the checksum field Fcs of the secondary header H2b delayed by the time Td according to the header length Lb is input to the checksum insertion unit 16 at the timing when the checksum value CSb is calculated by the calculation unit 14. As a result, the checksum insertion means 16 outputs the IP header Hip in which the checksum value CSb is inserted in the checksum field Fcs, as shown in FIG.
[0028]
When the primary header H1c including the option field Fop is output from the primary header generator 11, the source address SA and the destination address DA are inserted into the primary header H1c as shown in FIG. A checksum operation is performed on the entire secondary header H2c, and the checksum value CSc is obtained and output to the checksum insertion means 16 as shown in FIG.
[0029]
The secondary header H2c is output by the variable delay means 15 to the checksum insertion means 16 after being delayed by Td = (Lc−10) Tr as shown in FIG. In this case, since the header length Lc is 28 bytes, the delay time Td is 18 · Tr.
[0030]
Thus, the checksum field Fcs of the secondary header H2c delayed by the time Td according to the header length Lc is input to the checksum insertion unit 16 at the timing when the checksum value CSc is calculated by the calculation unit 14. As a result, the checksum insertion means 16 outputs the IP header Hip in which the checksum value CSc is inserted into the checksum field Fcs, as shown in FIG.
[0031]
[Problems to be solved by the invention]
However, in the conventional IP header generator 10 described above, the calculation target range of the calculation means 14 and the delay time Td for inserting the calculation result must be varied according to the length of the primary header H1. There is a problem that the hardware configuration becomes complicated.
[0032]
The present invention solves this problem, and even if the length of the primary header changes, it is not necessary to change the calculation target range and the delay time, and the IP packet can be generated by the same processing, and the hardware configuration is The object is to provide a simple IP header generator.
[0033]
[Means for Solving the Problems]
In order to achieve the above object, the IP header generator of the present invention provides:
Previously storing a previously inserted plurality of types of IP header of different lengths were the values checksum field took 1's complement sum of every 16 bits of the entire header excluding the source address field and destination address field as the primary header A primary header generator for outputting any of the primary headers in order from the top ;
Address insertion means for inserting a desired IP address into the source address field and the destination address field of the primary header output from the primary header generator, and outputting the header into which the IP address is inserted as a secondary header in order from the top When,
Data extraction means for extracting each value inserted in the checksum field, source address field and destination address field of the secondary header output from the address insertion means;
For each value extracted from the secondary header by the data extraction means, a 1's complement sum is calculated every 16 bits, and the 1's complement of the calculated value is calculated in real time as the checksum value of the secondary header. Computing means;
Fixed delay means for receiving a secondary header output from the address insertion means, and outputting a delay by a time substantially corresponding to the length from the beginning to immediately before the checksum field;
Checksum insertion means for inserting the checksum value calculated by the arithmetic means into the checksum field of the secondary header output from the fixed delay means and outputting the final IP header in order from the top . .
[0034]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows the configuration of an IP header generator 20 to which the present invention is applied.
[0035]
In FIG. 1, the primary header generation unit 21, for example, as shown in FIGS. 2A to 2C, 1's complement for every 16 bits of the entire header excluding the source address field Fsa and the destination address field Fda. Summed values Kd to Kf store primary headers H1d to H1f inserted in advance in the respective checksum fields Fcs, and sequentially output any of these primary headers H1d to H1f as necessary. .
[0036]
For example, dummy data of 0 is inserted in the source address field Fsa and the destination address field Fda of these primary headers H1d to H1f.
[0037]
The primary header H1d is the shortest (20 bytes long) not including the option field Fop, the primary header H1e is 24 bytes long including the option field Fop, and the primary header H1f is the option field Fop. Is 28 bytes long.
[0038]
The primary header generator 21 sequentially outputs the primary headers H1d to H1f in a predetermined width (for example, 1 byte width) in synchronization with a clock signal having a predetermined frequency (not shown) from the upper left corner to the lower right corner. .
[0039]
The address insertion means 22 inserts desired IP addresses SA and DA into the source address field Fsa and destination address field Fda of the primary header H1 output from the primary header generator 21, and the header into which the IP address is inserted is inserted. Output as the secondary header H2.
[0040]
The IP addresses SA and DA can be set by address setting means (not shown) or can be generated within the address insertion means 22.
[0041]
The data extraction unit 23 extracts the values K, SA, and DA inserted in the checksum field Fcs, the source address field Fsa, and the destination address field Fda of the secondary header H2 output from the address insertion unit 22. To the calculation means 24.
[0042]
The computing means 24 calculates a 1's complement sum for each 16 bits for the values K, SA, DA extracted from the secondary header H2 by the data extracting means 23, and uses the 1's complement of the calculated value as the secondary header. Calculated as the checksum value CS of H2.
[0043]
The fixed delay means 25 applies the time Td corresponding to the length (10 bytes) from the head of the secondary header H2 output from the address insertion means 22 to immediately before the checksum field Fcs, that is, the checksum field from the head. The data is output to the checksum insertion means 26 after being delayed by a time Td necessary to output the data corresponding to the length immediately before Fcs. Here, if the time required for the primary header generating means 21 to output one byte of the primary header is Tr as described above, the delay time Td can be expressed by 10 · Tr.
[0044]
Strictly speaking, it is necessary to add the delay time ΔT of the arithmetic processing of the arithmetic means 24 to the delay time Td. Here, it is assumed that the delay time ΔT can be ignored.
[0045]
The checksum insertion means 26 inserts the checksum value CS calculated by the calculation means 24 into the checksum field Fcs of the secondary header H2 output from the fixed delay means 25, and outputs it as the final IP header Hip. .
[0046]
In the IP header generator 20 configured as described above, for example, when the primary header H1d including no option field is output from the primary header generator 21 of the primary headers H1d to H1f shown in FIG. In the source address field Fsa and the destination address field Fda of H1d, as shown in FIG. 3A, desired IP addresses SA and DA are inserted by the address insertion unit 22, and the IP addresses are inserted. The header is output to the data extraction means 23 and the fixed delay means 25 as the secondary header H2d.
[0047]
The data extraction means 23 then uses the values Kd, SA, DA inserted in the three consecutive fields of the secondary header H2d, that is, the checksum field Fcs, the source address field Fsa, and the destination address field Fda. Is extracted and output to the computing means 24 as shown in FIG.
[0048]
The computing means 24 calculates a 1's complement sum for each of these values Kd, SA, DA every 16 bits, and obtains the 1's complement of the calculation result as the checksum value CSd of the secondary header H2d. .
[0049]
Note that the checksum is calculated in real time in the order of the data extracted by the data extraction means 23.
[0050]
That is, a 1's complement sum is obtained for the 16-bit value Kd extracted first and the subsequent 16-bit data of the IP address DA, and the result and the 16-bit data of the latter half of the IP address DA are 1's complement. Find the sum, find the one's complement sum for the first 16 bits of the IP address SA and the result, find the one's complement sum for the last 16 bits of the IP address SA, and invert the result And the checksum value CSd.
[0051]
The checksum value CSd calculated in this way is checked immediately after the final data in the destination address field Fda of the secondary header H2d is output from the address insertion means 22, as shown in FIG. It is output to the thumb insertion means 26.
[0052]
On the other hand, the secondary header H2d output from the address insertion means 22 to the fixed delay means 25 is delayed by a time Td = 10 · Tr corresponding to 10 bytes as shown in FIG. 26.
[0053]
For this reason, the checksum value CSd calculated by the calculation means 24 is inserted into the checksum field Fcs of the secondary header H2d as shown in FIG. 3E, and this checksum value CSd is inserted. The header is output as the final IP header Hip.
[0054]
When the primary header H1e including the option field Fop is output from the primary header generating unit 21, the source address field Fsa and the destination address field Fda of the primary header H1e are added to the source address field Fsa by the address insertion unit 22 in FIG. As shown in (a), desired IP addresses SA and DA are inserted and output as the secondary header H2e to the data extracting means 23 and the fixed delay means 25. Similarly to the above, the data extracting means 23 sets the secondary header H2e. The values Ke, SA, DA inserted in the checksum field Fcs, the source address field Fsa, and the destination address field Fda are extracted as shown in FIG.
[0055]
Then, the arithmetic means 24 calculates the 1's complement sum for each value Ke, SA, DA and the 1's complement of the calculation result, and the calculation result is obtained as the checksum value CSe of the secondary header H2e. And output to the checksum insertion means 26 as shown in FIG.
[0056]
On the other hand, the secondary header H2e output from the address insertion means 22 to the fixed delay means 25 is delayed by a time Td = 10 · Tr corresponding to 10 bytes as shown in FIG. 26.
[0057]
For this reason, the checksum value CSe calculated by the calculation means 24 is inserted into the checksum field Fcs of the secondary header H2e as shown in FIG. 4D, and this checksum value CSe is inserted. The header is output as the final IP header Hip.
[0058]
When the primary header H1f including the option field Fop is output from the primary header generation unit 21, the source address field Fsa and the destination address field Fda of the primary header H1f are added to the source insertion field 22 by the address insertion unit 22 in FIG. As shown in (a), desired IP addresses SA and DA are inserted and output as the secondary header H2f to the data extracting means 23 and the fixed delay means 25. Similarly to the above, the data extracting means 23 sets the secondary header H2f. The values Kf, SA, DA inserted in the checksum field Fcs, the source address field Fsa, and the destination address field Fda are extracted as shown in FIG.
[0059]
Then, the arithmetic means 24 calculates a 1's complement sum for each value Kf, SA, DA and a 1's complement of the calculation result, and the calculation result is obtained as a checksum value CSf of the secondary header H2f. And output to the checksum insertion means 26 as shown in FIG.
[0060]
On the other hand, the secondary header H2f output from the address insertion means 22 to the fixed delay means 25 is delayed by a time Td = 10 · Tr corresponding to 10 bytes as shown in FIG. 26.
[0061]
For this reason, the checksum value CSf calculated by the calculation means 24 is inserted into the checksum field Fcs of the secondary header H2f as shown in FIG. 5D, and this checksum value CSf is inserted. The header is output as the final IP header Hip.
[0062]
As described above, the IP header generator 20 according to the embodiment includes the IP header in which the value K representing the one's complement sum of the entire header excluding the source address field Fsa and the destination address field Fda is inserted in the checksum field Fcs in advance. Is output from the primary header generation unit 21 as the primary header H1, a desired IP address is inserted into the primary header H1 by the address insertion means 22, and the checksum field of the secondary header H2 output from the address insertion means 22 is output. The values K, SA, DA inserted in the Fcs, the source address field Fsa, and the destination address field Fda are extracted by the data extraction means 23, and one's complement sum for each of the extracted values K, SA, DA Chi E Kkusamu value by calculating the one's complement for resulting in computing means 24 S is obtained, and this checksum value CS is inserted by the fixed delay means 25 into the checksum field Fcs of the secondary header H2 delayed by a predetermined time Td substantially corresponding to the length from the beginning to immediately before the checksum field. The final IP header Hip is generated.
[0063]
For this reason, even when the header length is changed, by performing the same processing on the primary header H1, it is possible to output the IP header Hip with the checksum value correctly inserted in the checksum field. Can be simplified.
[0064]
In the above description, the case where only the IP header of the IP packet is generated and output has been described, but the data in the data field added to the IP header is not subject to the checksum calculation of the IP header.
[0065]
Therefore, for example, the primary header generation unit 21 may add the data of the data field to the primary header H1 and output the data to the address insertion unit 22. In this case, the same processing is performed after the address insertion unit 22 as well. By doing so, an IP packet including an IP header can be generated and output.
[0066]
Further, the data field data is added between the primary header generator 21 and the address insertion means 22, between the address insertion means 22 and the fixed delay means 25, between the fixed delay means 25 and the checksum insertion means 26, or the checksum. By performing the processing after the insertion unit 26, an IP packet including an IP header can be generated and output.
[0067]
However, when adding data field data to the IP header in this way, the value obtained by subtracting the header length field value from the packet length field value of the IP header matches the data length of the data field to be added. Let me.
[0068]
【The invention's effect】
As described above, the IP header generator of the present invention is
Previously storing a previously inserted plurality of types of IP header of different lengths were the values checksum field took 1's complement sum of every 16 bits of the entire header excluding the source address field and destination address field as the primary header A primary header generator for outputting any of the primary headers in order from the top ;
Address insertion means for inserting a desired IP address into the source address field and the destination address field of the primary header output from the primary header generator, and outputting the header into which the IP address is inserted as a secondary header in order from the top When,
Data extraction means for extracting each value inserted in the checksum field, source address field and destination address field of the secondary header output from the address insertion means;
For each value extracted from the secondary header by the data extraction means, a 1's complement sum is calculated every 16 bits, and the 1's complement of the calculated value is calculated in real time as the checksum value of the secondary header. Computing means;
Fixed delay means for receiving a secondary header output from the address insertion means, and outputting a delay by a time substantially corresponding to the length from the beginning to immediately before the checksum field;
Checksum insertion means for inserting the checksum value calculated by the arithmetic means into the checksum field of the secondary header output from the fixed delay means and outputting the final IP header in order from the top . .
[0069]
For this reason, even when the header length is variable, the IP header with the checksum value correctly inserted in the checksum field can be output by performing the same processing on the primary header, and the hardware configuration thereof Can be simplified.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of an embodiment of the present invention. FIG. 2 is a diagram showing a primary header output by a main part of the embodiment. FIG. 3 is a timing diagram for explaining an operation of the embodiment. FIG. 5 is a timing diagram for explaining the operation of the embodiment. FIG. 6 is a diagram showing a format of an IP header. FIG. 7 is a diagram showing a configuration of a conventional apparatus. 8 is a diagram showing a primary header of a conventional device. FIG. 9 is a timing diagram for explaining the operation of the conventional device. FIG. 10 is a timing diagram for explaining the operation of the conventional device. Timing chart for explanation [Explanation of symbols]
20 IP header generator 21 Primary header generator 22 Address insertion means 23 Data extraction means 24 Calculation means 25 Fixed delay means 26 Checksum insertion means

Claims (1)

Previously storing a previously inserted plurality of types of IP header of different lengths were the values checksum field took 1's complement sum of every 16 bits of the entire header excluding the source address field and destination address field as the primary header A primary header generator for outputting any of the primary headers in order from the top ;
Address insertion means for inserting a desired IP address into the source address field and the destination address field of the primary header output from the primary header generator, and outputting the header into which the IP address is inserted as a secondary header in order from the top When,
Data extraction means for extracting each value inserted in the checksum field, source address field and destination address field of the secondary header output from the address insertion means;
For each value extracted from the secondary header by the data extraction means, a 1's complement sum is calculated every 16 bits, and the 1's complement of the calculated value is calculated in real time as the checksum value of the secondary header. Computing means;
Fixed delay means for receiving a secondary header output from the address insertion means, and outputting a delay by a time substantially corresponding to the length from the beginning to immediately before the checksum field;
IP having checksum insertion means for inserting the checksum value calculated by the arithmetic means into the checksum field of the secondary header output from the fixed delay means and outputting the final IP header in order from the top Header generator.

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