JP6567476B2 - Data processing device - Google Patents

Description

The present invention relates to a technique using a DMA controller and a communication processing device. More specifically, the present invention relates to a technique for data transfer processing between a computer and a network interface.

In a network typified by Ethernet (registered trademark), a microprocessor (hereinafter abbreviated as “CPU”) executes transmission / reception with data (packetized) flowing over the network at a network interface.
Data transfer between the network interface and the CPU based on the simplest configuration is executed by the CPU mapping a buffer mounted on the network interface on the memory space of the CPU and issuing a memory access command from the CPU.

  However, when a large amount of packet data must be transmitted and received, processing time increases in issuing and executing a memory access instruction. Then, the packet processing time to be executed by the CPU is compressed, and as a result, the communication throughput is lowered.

As a method to prevent a decrease in communication throughput, a method is generally adopted in which a direct memory access (DMA) and its controller are installed, transferred from the network interface to the CPU memory, and the CPU load consumed for data copying is reduced. The
Here, direct memory access (DMA) refers to direct transfer of data between the memory and the memory or the peripheral device without going through the CPU.
For example, Patent Document 1 discloses a method of using a programmable sequencer as a DMA controller to suppress an increase in cost associated with shortening development efficiency.

  In Patent Document 2, two types of data buses are provided between the network interface and the CPU. Data obtained by performing protocol processing on the network interface is executed on one data bus, and the other data bus is executed by a host computer. A method is disclosed that enables transmission and reception of protocol processing data.

  Further, Patent Document 3 discloses a DMA controller and a communication processing device intended to shorten development efficiency and improve communication throughput.

Based on FIG. 1 (flow chart) and FIG. 2 (block diagram), a general procedure and hardware configuration for transferring large-capacity data such as image data and video data via a network will be described.
An image or video (moving image) is captured by the camera 100, and the captured image data or video data (hereinafter abbreviated as “image data”) is input to the image processing unit 101 by the camera interface (S1). Subsequently, the image processing unit 100 performs image processing on the original image data, and stores the processed image data in the communication receiving unit 22 (S2).

The image data stored in the communication receiving unit 22 is burst transferred to the memory unit 20 under the control of the DMA controller unit 21 (S3). The image data transferred to the memory unit 20 is burst transferred to the TCP payload of the memory unit 50 under the control of the DMA controller 31 (S4).
The image data transferred to the memory unit 20 is burst transferred to the SUM processing unit 10 under the control of the DMA controller 30. The SUM processing unit 10 calculates the SUM value, and the CPU 40 obtains the SUM value (S5).

The CPU 40 stores the SUM value in the TCP header of the memory unit 50 (S6). The TCP packet data stored in the memory unit 50 is burst transferred to the communication transmitting unit 52 under the control of the DMA controller 51 (S7). The communication transmission unit 52 transmits the received TCP packet data to the network (S8).

Japanese Patent Laid-Open No. 11-41297 JP 2000-235536 A JP 2007-27951 A

  For example, if a transfer rate of 50 megabytes / second is required, it is difficult to achieve with the techniques shown in FIGS.

The method of improving various processing speeds and increasing the transfer speed by improving the performance of the CPU is the simplest method and has been widely adopted.
However, when the improvement in CPU performance is achieved, the transfer speed requirement is usually improved. For example, it is required to improve the image quality of image data to be transferred.

The problem to be solved by the present invention is to provide a technique capable of improving the data transfer speed irrespective of the improvement in CPU performance.

  The present application relates to a technique capable of improving the data transfer speed regardless of the improvement in CPU performance by distributing the processing procedure which is a bottleneck by processing by the CPU at the time of data transfer. Provide an invention.

(First invention)
The first invention is a received data memory 20 for storing digital data to be transmitted via a communication network before processing it into protocol-processed data;
A data processing device 10A for calculating a SUM value for the digital data stored in the received data memory 20;
CPU 40 for executing protocol processing on the digital data stored in the received data memory 20;
A transmission data memory 50 for storing the protocol processed data processed by the CPU 40 and the SUM value calculated by the data processing apparatus 10A;
The data processing apparatus 10A according to the data processing apparatus 10A.
A DMA read unit 11 for performing a DMA process on the digital data stored in the received data memory 20 ;
SUM calculation means 12 for calculating a SUM value for transmission of digital data DMA-processed by the DMA read unit 11;
A register unit 13 for storing the SUM value calculated by the SUM calculation means;
A data buffer 15 for temporarily storing digital data stored in the received data memory 20;
A DMA write unit 14 for transferring the digital data stored in the data buffer 15 to the transmission data memory 50 ;
Is provided.
The DMA read unit 11 executes the transfer of the digital data to the SUM calculation unit 12 simultaneously with the storage of the digital data in the data buffer 15.

(Glossary)
As the digital data to be transmitted, data having a large capacity, such as image data (still image, moving image) and audio data, is suitable.
The digital data to be transmitted is subjected to protocol processing or the like for matching with a communication protocol to obtain protocol-processed data. The SUM calculation means (12) includes such protocol processing means (CPU 40) and Prepare separately.
The “data processing apparatus” according to the present application can be integrated into an existing data transmission apparatus, for example, in one chip.

(Function)
The digital data for calculating the SUM value by the SUM calculation means (12) is read from the received data memory (20) by the DMA read unit (11). The SUM calculation means (12) calculates the SUM value for transmission with respect to the read digital data. The SUM value calculated by the SUM calculation means (12) is stored in the register unit (13).
On the other hand, the digital data stored in the reception data memory (20) is transferred by the DMA write unit (14) to the transmission data memory (50) for processing into digital data with a SUM value. The DMA read unit (11) causes the transmission data memory (50) to be transferred and the SUM calculation executed simultaneously.

  Since the SUM calculation by the SUM calculation means (12) and the transmission processing of the digital data to be transmitted to the transmission data memory (50) can be executed at the same time, the total processing time can be reduced and the data transmission speed can be improved. Can do.

(Second invention)
The second invention includes a received data memory 20 for storing digital data to be transmitted via a communication network before processing the data into protocol processed data,
A data processing device 10B for calculating a SUM value for the digital data stored in the received data memory 20,
CPU 40 for executing protocol processing on the digital data stored in the received data memory 20;
A transmission data memory 50 for storing the protocol processed data processed by the CPU 40 and the SUM value calculated by the data processing device 10B;
(Refer to FIG. 6)
It differs from the first invention, DMA write unit (14), also a SUM value stored register unit (13) is a point that is to be transferred to the transmission data memory 50.

(Function)
The DMA write unit (14) transfers the SUM value calculated by the SUM calculation means (12) to the transmission data memory (50). The timing for processing the digital data with the SUM value is adjusted by the DMA write unit (14).

(Variation 2 of the first invention)
The first invention can also be formed as follows.
That is, a read bus (61) for data transfer from the received data memory (20) to the DMA read unit (11), and a transmission data memory (from the DMA write unit (14)) And a write bus (62) for data transfer to (50).

(Function)
In addition to the CPU bus (60), the provision of the read bus (61) and the write bus (62) contributes to an improvement in processing speed or contributes to CPU processing execution in parallel.

According to the first aspect of the present invention, it is possible to provide a data processing device that can reduce the calculation burden on the CPU and increase the transmission speed when transmitting large-capacity digital data.

It is a flowchart which shows the procedure in the case of transmitting the camera image in a general (old system) via a network. It is a block diagram which shows the hardware constitutions which transmit the camera image in a general (old system) via a network. In general (old system), it is a conceptual diagram which shows how the image of the camera which image | photographed the to-be-photographed object is processed. It is a flowchart which shows the procedure in the case of transmitting the camera image via a network in embodiment (new system) which concerns on this application. It is a block diagram which shows the hardware constitutions which transmit the camera image via network in embodiment (new system) which concerns on this application. It is a block diagram which shows the hardware constitutions in the 1st variation of FIG. It is a block diagram which shows the hardware constitutions in the 2nd variation of FIG. It is a block diagram which shows the hardware constitutions in the 3rd variation of FIG. It is a conceptual diagram which shows how the image of the camera which image | photographed the object is processed in embodiment (new system) which concerns on this application. It is a conceptual diagram which shows how the image of the camera which image | photographed the to-be-photographed object is processed in 2nd embodiment.

  Hereinafter, the present invention will be described based on embodiments. The drawings used here are FIGS. 4 to 10. Further, FIG. 3 is referred to and compared as necessary.

(FIGS. 4 and 5)
The configuration and processing procedure of this embodiment will be described with reference to FIGS. 4 and 5.
An image or video (hereinafter referred to as “image”) is taken by the camera 100 and input to the image processing unit 101 via the camera interface (S11).
The image processing unit 101 performs image processing on the original image, and stores the processed image data in the communication receiving unit 22 (S12).
The processed image data stored in the communication receiving unit 22 is burst transferred to the memory unit 20 under the control of the DMA controller unit 21 (S13).

  The image data transferred to the memory unit 20 is burst transferred to the TCP payload of the memory unit 50 under the control of the SUM processing built-in DMA controller 10 (10A in FIG. 5). Simultaneously with the transfer, the SUM calculation unit 12 built in the SUM processing built-in DMA controller 10 calculates the SUM value and stores it in the register unit 13 (S14).

The CPU 40 stores the SUM value stored in the register unit 13 in the TCP header of the memory unit 50 (S15).
The TCP packet data stored in the memory unit 50 is burst transferred to the communication transmission unit 52 under the control of the DMA controller 51 (S16).
The communication transmitter 52 transmits the received TCP packet to the network (S17).

  As shown in FIG. 5, in the SUM processing built-in DMA controller 10A, the data read from the memory unit 20 (received data memory) by the DMA read unit 11 is sent to the SUM calculation unit 12 and also in the FIFO 15 as a data buffer. The timing of writing to the memory unit 50 (transmission data memory) by the DMA write unit 14 is adjusted.

(Fig. 6)
FIG. 6 shows a variation of the embodiment shown in FIG.
In the SUM processing built-in DMA controller 10 </ b> B shown in FIG. 6, the data read from the memory unit 20 (received data memory) by the DMA read unit 11 is sent to the SUM calculation unit 12 and the FIFO 15.

The SUM value calculated by the SUM calculation unit 12 is written in the register unit 13. The DMA write unit 14 transfers the data accumulated in the FIFO 15 and the SUM value written in the register unit 13 to the memory unit 50 (transmission data memory).

(Fig. 7)
FIG. 7 also shows a variation of the embodiment shown in FIG.
7 includes a read bus 61 for data transfer from the memory unit 20 (received data memory) to the DMA read unit 11 in addition to the CPU bus 60. Also, a write bus 62 for data transfer from the DMA write unit 14 to the memory unit 50 (transmission data memory) is provided.

The data accumulated in the FIFO 15 is transferred to the memory unit 50 via the write bus 62 by the DMA write unit 14.
On the other hand, the SUM value stored in the register unit 13 is transferred to the memory unit 50 via the CPU bus 60.

  In this embodiment, since the read bus 61 and the write bus 62 are provided, it contributes to an improvement in processing speed by being able to exchange data without using the CPU bus 60, or contributes to CPU processing execution in parallel. To do.

(Fig. 8)
FIG. 8 also shows a variation of the embodiment shown in FIG.
The embodiment shown in FIG. 8 also includes a read bus 61 and a write bus 62.
The difference from FIG. 7 is that the SUM value stored in the register unit 13 is transferred to the memory unit 50 via the write bus 62 together with the digital data stored in the FIFO 15.

Also in this embodiment, since the read bus 61 and the write bus 62 are provided, it is possible to contribute to an improvement in processing speed by being able to exchange data without using the CPU bus 60, or to execute CPU processing in parallel. Or contribute.

(Fig. 9)
Based on FIG. 9, it will be described how an image of a camera that captured a subject is processed as data, and where it is transmitted and stored. In FIG. 9, what is expressed by a balloon indicates which hardware is mainly performing the process indicated by the direction of the arrow.
If necessary, it becomes clear where the present invention (each embodiment) differs from the prior art when compared with FIG.

  First, when the camera 100 captures a subject, an analog image (which may be a still image or a moving image) is digitized by the image processing unit 101 in the camera 100 to become image data. The digitized image data is stored in the memory unit 20 (received data memory).

The image data stored in the memory unit 20 is subjected to protocol processing so that it can be transmitted through a communication line. This protocol processing is executed by the CPU 40.
On the other hand, the SUM value is calculated using the image data stored in the memory unit 20, and the calculation process is executed by the DMA controller 10A with a built-in SUM process. This will be described in more detail below.

  First, the image data stored in the memory unit 20 is read into the DMA read unit 11. Then, the SUM calculation unit 12 calculates the SUM value. The calculated SUM value is stored in the register unit 13, and the CPU 40 writes the SUM value in the memory unit 50.

The image data stored in the memory unit 20 is also temporarily stored in the FIFO 15. The DMA read unit 11 simultaneously executes data storage in the FIFO 15 and image data transfer to the SUM calculation unit 12.
Note that the DMA write unit 14 controls the timing of transmission to the memory unit 50 (transmission data memory).

  The SUM value and the image data subjected to protocol processing are stored in the memory unit 50 and packetized as image data with a SUM value by the CPU 40. The image data with the SUM value is transmitted to the network by the communication transmission unit 52.

In the processing procedure shown in FIG. 9, the DMA read unit 11 described above contributes to the resolution of the conventional bottleneck and also contributes to the improvement of the image data transmission speed.
The processing procedure shown in FIG. 9 can create packetized data more smoothly than the processing procedure shown in FIG. In the processing procedure of FIG. 3, there is no parallel processing as shown in FIG .

(Fig. 10)
FIG. 10 shows a variation of the embodiment shown in FIG.
The difference from the above-described embodiment is that the image data digitized by the image processing unit 101 in the camera 100 is also stored in the sub memory 25 provided separately from the memory unit 20.
The sub memory 25 includes a case where the sub memory 25 exists by setting a partition in the memory unit 20 in addition to a case where the sub memory 25 is physically different from the memory unit 20.

The DMA read unit 11 of the SUM processing built-in DMA controller 10 </ b> B controls the SUM calculation unit 12 to calculate the SUM value using the image data stored in the sub memory 25. The presence of the sub memory 25 can reduce the load on the memory unit 20.

The present invention has applicability in the manufacturing industry of information communication equipment, the software industry for creating computer software for information communication services, and the like.

DESCRIPTION OF SYMBOLS 10; SUM processing part 10A, 10B, 10C, 10D; SUM processing built-in DMA controller 11; DMA read part 12; SUM calculation part 13; Register part 14; DMA write part 15; FIFO (buffer memory)
20; Memory unit (for receiving image data) 21; DMA controller 22; Image communication receiving unit 25; Sub-memory 30; DMA controller (for SUM transfer)
31; DMA controller (for memory transfer)
40; CPU
50; Memory unit (for storing transmission data) 51; DMA controller 52; Communication transmission unit 60; CPU bus 61; Read bus 62; Write bus 100; Camera 101;

Claims (3)

Received data memory for storing digital data to be transmitted via a communication network before processing into protocol processed data,
A data processing device for calculating a SUM value for the digital data stored in the received data memory;
A CPU that performs protocol processing on the digital data stored in the received data memory and processes the data into protocol-processed data;
A transmission data memory for storing the protocol processed data and the SUM value calculated by the data processing device;
The data processing device in a data transmission device comprising:
A DMA read unit for performing DMA processing on the digital data stored in the received data memory;
SUM calculation means for calculating a SUM value for transmission of digital data DMA-processed by the DMA read unit;
A register unit for storing the SUM value calculated by the SUM calculation means;
A data buffer for temporarily storing the digital data stored in the received data memory;
A DMA write unit for transferring the digital data stored in the data buffer to the transmission data memory;
With
The data read device, wherein the DMA read unit executes the transfer of the digital data to the SUM calculation means simultaneously with the storage of the digital data in a data buffer. Received data memory for storing digital data to be transmitted via a communication network before processing into protocol processed data,
A data processing device for calculating a SUM value for the digital data stored in the received data memory;
A CPU that performs protocol processing on the digital data stored in the received data memory and processes the data into protocol-processed data;
A transmission data memory for storing the protocol processed data and the SUM value calculated by the data processing device;
The data processing device in a data transmission device comprising:
A DMA read unit for performing DMA processing on the digital data stored in the received data memory;
SUM calculation means for calculating a SUM value for transmission of digital data DMA-processed by the DMA read unit;
A register unit for storing the SUM value calculated by the SUM calculation means;
A data buffer for temporarily storing the digital data stored in the received data memory;
A DMA write unit for transferring the digital data stored in the data buffer and the SUM value stored in the register unit to a transmission data memory;
With
The DMA read unit transfers the digital data to the SUM calculation unit.
A data processing apparatus which is executed simultaneously with the storage of the digital data in the data buffer. A read bus for data transfer from the received data memory to the DMA read unit;
A write bus for data transfer from the DMA write unit to the transmission data memory ;
A data processing apparatus according to claim 1, comprising:

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