JP3632111B2 - Semiconductor device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor device.
[0002]
[Prior art]
In the conventional semiconductor device, as shown in FIG. 2, a scribe line 22 is provided between the integrated circuits 21 on the semiconductor substrate. When dicing, the semiconductor substrate is cut along the scribe line 22 with a cutter. It was.
[0003]
[Problems to be solved by the invention]
However, the conventional one has a problem that the space between the integrated circuits 21 is set narrow in order to improve productivity, and therefore the integrated circuit 21 is cut when dicing.
[0004]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device in which cutting into an integrated circuit during dicing is prevented.
[0005]
[Means for Solving the Problems]
Walls are provided on the scribe lines provided between the integrated circuits so as to be separated from the individual integrated circuits so as to surround the individual integrated circuits, and the distance between the pair of walls facing each other on the scribe line is as follows. , The interval is set such that the cutter can enter during dicing, and the wall portion includes a plurality of layers formed in the same step as the step of forming the plurality of layers constituting the integrated circuit. The above object is achieved by a semiconductor device having the same height .
[0006]
Here, the wall portion is preferably formed because it is formed in the same step as the step of forming a layer such as an insulating layer or a wiring layer constituting each integrated circuit.
[0007]
【Example】
Next, a semiconductor device according to an embodiment of the present invention will be described. 1A and 1B are explanatory views showing the configuration of this example. FIG. 1A shows a plane, and FIG. 1B shows a cross section taken along line AA in FIG. In FIG. 1A, reference numeral 1 denotes an integrated circuit, which is provided on a semiconductor substrate (not shown). Reference numeral 2 denotes a scribe line, which is provided between the integrated circuits 1. A wall 3 is provided for each integrated circuit 1 on the scribe line 2 so as to surround each integrated circuit 1. These wall portions 3 are formed of layers such as an insulating layer 10, a wiring layer 11, and a final protective layer 12 on the semiconductor substrate 13 constituting the integrated circuit 1, as shown in FIG. That is, although not particularly illustrated, the pattern of the wall portion 3 is provided on the transfer mask pattern at the time of processing the insulating layer or the like in the semiconductor device manufacturing process and at the time of processing the final protective layer. Therefore, it is not necessary to add a special process to form the wall portion 3. Here, for example, the interval between the integrated circuit 1 and the wall 3 surrounding the integrated circuit 1 is about 3 μm, the width of the wall 3 is about 5 μm, and the wall 3 and the adjacent wall 3 are adjacent to the wall 3. Is about 60 μm.
[0008]
The semiconductor device of this example configured as described above cuts between the wall portions 3 with a cutter (not shown) during dicing. At this time, since the integrated circuit 1 is guarded by the wall portion 3, it is possible to prevent the integrated circuit 1 from being chipped due to the cutting of the cutter. In other words, when the cutter is misaligned due to various factors, chipping of the integrated circuit 1 occurs in the conventional method. However, by providing the wall portion 3, chipping of the integrated circuit 1 due to cutting of the cutter is caused by the wall portion. It stops and does not reach the integrated circuit 1. As the height of the wall 3 is higher and the distance from the integrated circuit 1 is wider, the effect of preventing chipping of the integrated circuit 1 due to the cutting of the cutter is enhanced.
[0009]
Note that the wall 3 may be configured by using any one of the insulating layer 10 and the wiring layer 11 and the final protective layer 12 alone or in any combination. In addition, the wall 3 may be formed later, not limited to the one formed simultaneously during the manufacturing process of the integrated circuit 1.
[0010]
【The invention's effect】
According to the present invention, it is possible to prevent cutting into the integrated circuit during dicing by providing a wall portion surrounding the integrated circuit. For this reason, defects due to chipping of the integrated circuit can be reduced, and there is an effect of stable operation during chip processing and improvement in yield.
[0011]
In addition, since the wall portion is formed of an insulating layer, a wiring layer, or the like that constitutes the integrated circuit, it is not necessary to add a special process and an increase in cost due to the provision of the wall portion can be suppressed.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram for explaining a configuration of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is an explanatory diagram for explaining a configuration of a conventional technique.
[Explanation of symbols]
1 Integrated Circuit 2 Scribe Line 3 Wall

Claims (2)

A wall portion is provided on the scribe line provided between the integrated circuits so as to surround the integrated circuits apart from the integrated circuits .
The interval between the pair of walls facing each other on the scribe line is set to an interval at which the cutter can enter during dicing ,
The wall portion includes a plurality of layers formed in the same step as the step of forming a plurality of layers constituting the integrated circuit, and has substantially the same height as the integrated circuit. Semiconductor device. The wall portion above the insulating layers constituting each integrated circuit, the semiconductor device according to claim 1, characterized in that it is formed from a layer formed by the same process of forming the layer of the wiring layer or the like.

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