JP3637779B2 - Dielectric barrier discharge lamp light source device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
As a kind of discharge lamp used as an ultraviolet light source for photochemical reaction, a so-called dielectric barrier discharge lamp is known in which excimer molecules are formed by dielectric barrier discharge and light emitted from the excimer molecules is used.
The present invention relates to the dielectric barrier discharge lamp light source device, and more particularly, the present invention relates to a dielectric barrier discharge lamp light source device suitable for measuring the afterglow characteristics of a phosphor.
[0002]
[Prior art]
A dielectric barrier discharge lamp fills a discharge vessel with a discharge gas for forming excimer molecules, forms excimer molecules by dielectric barrier discharge, and utilizes light emitted from the excimer molecules (dielectric barrier discharge lamp). For the lighting device and the lighting device, see, for example, Japanese Patent Application No. 10-120336 previously proposed by the present applicant).
FIG. 9 is a diagram showing a principle configuration of a dielectric barrier discharge lamp light source device, and this figure shows a dielectric barrier discharge lamp in which two dielectrics 5 and 6 exist. As shown in the figure, the dielectric barrier discharge lamp 1 has one or two dielectrics between the electrodes with the discharge plasma space interposed therebetween. In the figure, the lamp seal 7 also serves as the dielectrics 5 and 6.
[0003]
When the dielectric barrier discharge lamp 1 is lit, high-frequency AC voltages of, for example, 10 kHz to 200 kHz and 2 kV to 10 kV are applied to the electrodes 3 and 4 of both electrodes from the high frequency power source 9 of the power supply device 8 via the step-up transformer Tr. Apply. As a result, charges having the same sign opposite to that of the surfaces on the electrodes 3 and 4 are induced on the surfaces of the dielectrics 5 and 6 on the discharge plasma space 2 side by polarization of the dielectrics, and the discharge plasma space 2 is sandwiched between them. Discharge occurs between the surfaces of the opposing dielectrics 5 and 6.
In the portion where the discharge has occurred, the charges induced on the surfaces of the dielectrics 5 and 6 on the discharge plasma space 2 side are neutralized by the charges moved by the discharge, and the electric field in the discharge plasma space 2 decreases. For this reason, even if the voltage application to the electrodes 3 and 4 is continued, the discharge current will eventually stop. However, when the voltage applied to the electrodes 3 and 4 further increases, the discharge current continues.
When the discharge is stopped after the discharge is generated once, the discharge is not performed again until the polarity of the voltage applied to the electrodes 3 and 4 is reversed.
[0004]
For example, in the case of a dielectric barrier discharge lamp in which xenon gas is sealed, the xenon gas is separated into ions and electrons by discharge and becomes xenon plasma. In this plasma, xenon excited to a specific energy level binds to form an excimer molecule. Xenon excimer dissociates after a certain lifetime, but the energy released at this time is released as photons of vacuum ultraviolet wavelength.
[0005]
[Problems to be solved by the invention]
Dielectric barrier discharge lamps (hereinafter abbreviated as lamps as necessary), even if voltage application is continued as described above, the discharge stops after a while and redischarges until the polarity of the voltage is reversed. do not do. For this reason, the lamp emits light in pulses every time a voltage is applied, and does not emit light continuously.
Therefore, when the dielectric barrier discharge lamp is used as a light source for measuring the afterglow characteristics of the phosphor, the generation of the light emission pulse train of the dielectric barrier discharge lamp is stopped for a necessary period, and the last light emission pulse of the light emission pulse train is used. Is substantially the same as each light emission pulse in the previous light emission pulse train.
[0006]
That is, as shown in FIGS. 10 (a) and 11 (a), if the last light emission pulse in the light emission pulse train is substantially the same as the previous light emission pulse train, the light emission of the phosphor after the light emission pulse is stopped. The intensity decreases according to the afterglow characteristics as shown in FIGS. 10B and 11B, and the afterglow characteristics of the phosphor can be accurately measured.
However, power supply circuits such as flyback, full bridge, and half bridge systems that are used as high-frequency power sources to turn on the lamps cut off the power supply of the power supply circuit and stopped the gate signal to the switching element. Thereafter, an oscillating voltage is generated by ringing or the like for a while, and the oscillating voltage is applied to the lamp. For this reason, the lamp does not stop emitting light immediately.
[0007]
FIG. 12 shows the lamp applied voltage waveform and the light emission of the lamp when the dielectric barrier discharge lamp is turned on by a flyback power supply circuit and the gate signal to the switching element of the power supply circuit is turned off to shut off the switching element. It is a figure which shows an intensity | strength signal. In the figure, the horizontal axis indicates time (ms), and shows the time when “lighting stop” in the figure cuts off the gate signal to the switching element.
As shown in FIG. 6A, a voltage is applied to the lamp even after the gate signal to the switching element of the power feeding circuit is cut off, and the lamp emits light as shown in FIG. In addition, the last light emission pulse in the light emission pulse train becomes smaller and does not become the same as the previous light emission pulse.
In general, when the light emission of the lamp is stopped by shutting off the gate signal of the switching element of the power feeding circuit, as shown in FIGS. 13 (a) and 13 (b), the light emission intensity of the phosphor also increases as the lamp light emission intensity decreases. It becomes gradually smaller and the afterglow characteristics of the phosphor cannot be measured accurately.
[0008]
Further, the above-described power supply circuit such as the flyback method, the full bridge method, or the half bridge method is provided with a step-up transformer Tr at the output end as shown in FIG. 9, and a lamp is provided on the secondary side of the step-up transformer. It is connected. In addition, the period during which the operation of the power feeding circuit is stopped to measure the afterglow characteristics of the phosphor is much longer than the repetition period of the voltage generated on the secondary side of the step-up transformer.
For this reason, if the circuit operation is stopped in a state where a voltage is applied to the primary side of the step-up transformer in order to stop the light emission of the lamp, the step-up transformer is saturated. Saturation of the step-up transformer must be avoided because it causes destruction of the switching elements of the power supply circuit.
That is, in order to use the dielectric barrier discharge lamp as a light source for measuring the afterglow characteristic of the phosphor, the last light emission pulse of the light emission pulse train is avoided as shown in FIGS. 10 and 11 while avoiding saturation of the step-up transformer. However, it is necessary to stop the light emission of the lamp so as to be substantially the same as the previous light emission pulse train.
[0009]
The present invention has been made in view of the circumstances described above, and can suspend light emission of the light source device for a period necessary to measure the afterglow characteristics of the phosphor without saturating the step-up transformer, and It is an object to provide a dielectric barrier discharge lamp light source device capable of accurately measuring afterglow characteristics of a phosphor.
[0010]
[Means for Solving the Problems]
In the present invention, a dielectric barrier discharge lamp light source device including the above-described dielectric barrier discharge lamp and a power supply device for applying a high voltage to the electrodes of the dielectric barrier discharge lamp is configured as follows.
(1) The dielectric barrier discharge lamp has a rest period via a step-up transformer. Periodic A power supply device that applies a high voltage with a waveform is provided. Periodic The dielectric barrier discharge lamp is turned on by the high voltage of the waveform.
(2) Above After stopping the driving of the switching element for lighting the dielectric barrier discharge lamp, Means for short-circuiting the primary side of the step-up transformer is provided, and when the lighting of the dielectric barrier discharge lamp is stopped in order to measure the persistence characteristic of the phosphor, the primary side of the step-up transformer is short-circuited by the short-circuit means.
In the present invention, the dielectric barrier discharge lamp has a rest period as described above. Periodic Apply high voltage of waveform to light up, After stopping the driving of the switching element, Since the primary side of the step-up transformer is short-circuited to release the energy accumulated in the step-up transformer and the like so that the dielectric barrier discharge lamp stops lighting, the last light emission pulse of the light emission pulse train is the same as the previous light emission pulse train. The light emission of the lamp can be stopped so as to be substantially the same. Further, the step-up transformer does not saturate during the lighting stop period of the dielectric barrier discharge lamp.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram showing a first embodiment of a dielectric barrier discharge lamp light source device according to the present invention. FIG. 1 shows an embodiment when a flyback type power feeding circuit is used.
In the figure, 1 is a dielectric barrier discharge lamp, 11 is a step-up transformer, and 12 is a first switching element. For example, a driving power MOSFET can be used. Reference numeral 13 denotes an oscillator that outputs a clock signal CK0, and reference numeral 14 denotes a gate signal generation circuit that generates a gate signal for driving the first switching element 12.
When the clock signal CK0 rises, the gate signal generation circuit 14 outputs a gate signal G having a predetermined time width if the inhibition signal EN1 output from the D-FF 15b is at a high level (hereinafter referred to as H level).
[0012]
Reference numeral 15 denotes a lighting / light-off control circuit, which includes a delay circuit 15a and a D-flip flop 15b (hereinafter abbreviated as D-FF). The D / FF 15b has a permission / inhibition signal EN0 at a low level (hereinafter referred to as L level). Then, the inhibition signal EN1 is set to L level at the rising timing of the clock CK1 obtained by delaying the clock CK0 by a predetermined time.
Reference numeral 16 denotes a monostable multi-multivibrator (hereinafter abbreviated as MM), which outputs a dump signal DMP having a predetermined time width at the falling timing of the inhibition signal EN1. Reference numeral 17 denotes a damper circuit, and 18 denotes a second switching element composed of a power transistor or the like. The damper circuit 17 turns on the second switching element 18 while the dump signal DMP is being output, and the step-up transformer 11 Short-circuit the primary side. Reference numeral 19 is a capacitor, and 20 is a resistor.
[0013]
FIG. 2 is a diagram showing waveforms at various parts of the light source device shown in FIG. 1, and the operation of the light source device of this embodiment will be described with reference to FIG.
First, the operation in a state where the enable / disable signal EN0 is at the H level and the dielectric barrier discharge lamp is turned on will be described.
A clock signal CK0 (see CK0 in FIG. 2) output from the oscillator 13 is supplied to the gate signal generation circuit 14, and the gate signal generation circuit 14 generates a gate signal G having a predetermined width at the rising timing of the clock signal CK0 (FIG. 2). See G).
When the gate signal G becomes H level, the first switching element 12 is turned on, a current flows through the DC power source + → the primary winding of the step-up transformer 11 and the path of the switching element 12, and energy is stored in the step-up transformer 11. .
[0014]
Next, when the switching element 12 is turned off, the current flowing through the step-up transformer 11 is cut off, so that the energy stored in the step-up transformer 11 is released, as shown in FIG. 2 (see Vs in FIG. 2). A voltage waveform having a steep rise on the secondary side of the step-up transformer 11 is generated. This voltage waveform decays with time, and when the next switching element 12 is turned on and then turned off, a voltage waveform having a steep rise again is generated as described above. That is, a voltage waveform having a steep rise is generated every time the switching element 12 is turned on / off, and a high-frequency voltage that changes positively and negatively is applied to the dielectric barrier discharge lamp 1. Since the dielectric barrier discharge lamp 1 emits light when a voltage is applied, it emits in pulses as shown in FIG. 10 (a) or FIG. 11 (b) when the high frequency voltage rises and falls. To do.
In this state, the permission / inhibition signal EN0 is at the H level, and the outputs of the D-FFs 15b, MM16, and the damper circuit 17 are all at the L level, so the second switching element 18 is off.
[0015]
Next, when the lamp 1 is emitting light as described above, the operation when the enable / disable signal EN0 becomes L level as shown in FIG. 2 will be described.
The delay circuit 15a of the on / off control circuit 15 generates the clock signal CK1 shown in FIG. 2 obtained by delaying the clock signal CK0 for a predetermined time. When the enable / inhibit signal EN0 becomes L level, the rise of the clock signal CK1 is generated. At the timing, the D-FF 15b is set, and its output EN1 becomes L level (see EN1 in FIG. 2).
As a result, the operation of the gate signal generation circuit 14 is prohibited, and the generation of the gate signal G is stopped (see G in FIG. 2). Further, the MM 16 operates to generate a dump signal DMP having a predetermined time width as shown in FIG. The dump signal DMP is given to the damper circuit 17, and the damper circuit 17 turns on the second switching element 18. Therefore, the primary side of the step-up transformer 11 is short-circuited via the switching element 18 and the resistor 20, and the voltage on the secondary side of the step-up transformer 11 becomes 0 as shown by Vs in FIG. For this reason, the lamp 1 stops light emission immediately.
[0016]
Next, when the output of the MM 16 becomes L level and the dump signal DMP becomes L level as shown in FIG. 2, the switching element 18 is turned off. In this state, since the energy stored in the step-up transformer 11 and the like is released through the switching element 18, a voltage that causes the lamp 1 to emit light on the secondary side of the step-up transformer 11 as shown in FIG. Does not occur.
In this state, when the enable / disable signal EN0 becomes H level again, the output of the D-FF 15b becomes H level, the gate signal generation circuit 14 starts generating the gate signal G, and the lamp 1 emits light as described above. Start.
[0017]
The timing at which the primary side of the step-up transformer 11 is short-circuited can be arbitrarily determined by selecting the delay time of the clock signal CK1 with respect to the clock signal CK0 by the delay circuit 15a, and the rising timing of the clock signal CK1 can be determined. By setting when the output voltage of 11 becomes approximately 0, an output waveform as shown by Vs in FIG. 2 can be obtained.
When a flyback circuit is used, the secondary side voltage change of the step-up transformer 11 after the enable / inhibit signal EN0 becomes H level as shown by Vs in FIG. From 0 to 0 level, it becomes smaller than the voltage change during normal lighting. For this reason, the light emission pulse intensity at this time is slightly smaller than the light emission pulse intensity during normal lighting, but there is no practical problem in measuring the afterglow characteristics.
[0018]
FIG. 3 is a diagram showing an example of a permission / prohibition signal generation circuit that generates the permission / prohibition signal EN0. In the figure, 21 is an oscillator for generating a pulse signal, 22 is a frequency setting means for setting the oscillation frequency of the oscillator, 23 is a monostable multivibrator (abbreviated as MM), and 24 is a pulse width output by the MM23. Pulse width setting means.
In the figure, an oscillator 21 generates a pulse signal at a frequency set by frequency setting means 22. When the output pulse of the oscillator 21 rises, the MM 23 generates a pulse having a pulse width set by the pulse width setting means 24, and this signal is sent to the lighting / extinguishing control circuit 15 shown in FIG. Given.
By using the lighting / prohibition signal generation circuit shown in FIG. 3, the H level period and the L level period of the enable / inhibit signal EN0 can be arbitrarily set by the frequency setting means 22 and the pulse width setting means 24. The lighting time and extinguishing time of the dielectric barrier discharge lamp 1 can be arbitrarily controlled.
[0019]
FIG. 4 is a diagram showing measured data of a lamp applied voltage waveform and a lamp emission intensity signal waveform of the light source device of this example.
In the figure, the horizontal axis represents time (ms), and “lighting stop” indicates a point in time when the inhibition signal EN1 becomes L level. As is apparent from the figure, in the light source device of the present embodiment, the light emission of the lamp can be almost completely stopped at the time of “lighting stop”, and the afterglow characteristic of the phosphor can be accurately measured. became. In addition, since the lamp is turned off when the voltage applied to the step-up transformer 11 is zero, the step-up transformer 11 is not saturated.
[0020]
Next, an embodiment in which the present invention is applied to a full bridge type power feeding circuit will be described.
FIG. 5 is a diagram illustrating a main circuit configuration of a full-bridge power supply circuit. In the figure, 1 is a dielectric barrier discharge lamp, 11 is a step-up transformer, 31a to 31d are switching elements such as drive power MOSFETs, 32a to 32d are gate drive circuits, 33a to 33d are diodes, and 34 is a DC power supply. is there.
As shown in the figure, the main circuit of the full bridge system of this embodiment connects the switching elements 31a to 31d in a bridge shape, and the step-up transformer 11 is connected to the connection points of the switching elements 31a and 31d and the switching elements 31c and 31b. The primary winding is connected, and the switching elements 31a to 31d are operated as in the following (1) to (5) to generate an AC voltage in the secondary winding of the step-up transformer 11. The lamp 1 is caused to emit light.
[0021]
(1) The switching element 31a is turned on while the switching element 31c is on and 31d is off. As a result, a path of the switching element 31a → the primary winding of the step-up transformer 11 → the switching element 31c is formed, and the primary winding of the step-up transformer 11 is short-circuited. Thereby, the energy stored in the step-up transformer 11 or the like is released.
(2) With the switching element 31a turned on, the switching element 31c is turned off and the switching element 31b is turned on. As a result, a path of DC power supply 34 → switching element 31a → primary winding of step-up transformer 11 → switching element 31b → DC power supply 34 is formed, and a voltage is applied to the primary winding of step-up transformer 11.
(3) With the switching element 31b turned on, the switching element 31a is turned off and the switching element 31d is turned on. As a result, a path of the switching element 31b → the primary winding of the step-up transformer 11 → the switching element 31d is formed, and the primary winding of the step-up transformer 11 is short-circuited.
(4) With the switching element 31d turned on, the switching element 31b is turned off and the switching element 31c is turned on. As a result, a path of DC power source 34 → switching element 31c → primary winding of step-up transformer 11 → switching element 31d → DC power source 34 is formed, and the primary winding of step-up transformer 11 is in the direction opposite to the above (2). Is applied.
{Circle around (5)} With the switching element 31c turned on, the switching element 31d is turned off, the switching element 31a is turned on, and the process returns to the above {circle around (1)}.
[0022]
FIG. 6 is a diagram showing a configuration of a gate signal generation circuit for driving the switching elements 31a to 31d shown in FIG.
In the figure, reference numeral 41 denotes an oscillator that generates a clock signal CKA. The clock signal CKA generated by the oscillator 41 is input to the clock input terminal and the OR gate 42 of the D-FF 43. The output of the D-FF 43 is input to the other input of the OR gate 42. The D-FF 43 is set to the state of the D input terminal when the clock signal CKA is input. For example, if the D input terminal is at the H level when the clock signal CKA is input, the D-FF 43 outputs an H level signal to the Q output. .
The output of the D-FF 43 is at the L level during normal operation (when the enable / disable signal ENA is at the L level and the lamp lighting is permitted), and the OR gate 42 generates the clock signal CKB having the same phase as the clock signal CKA. The clock signal CKB is input to the clock input terminals of the counter 47, the D-FF 44, and the D-FFs 49a to 49d.
[0023]
The D-FF 44 is set to the state of the D input terminal when the clock signal CKB is input. For example, if the output terminal QD of the counter 47 is at the H level, an L level signal is output to the inverted output Q. The output of the D-FF 44 is input to the AND gate 45. The AND gate 45 generates an H level output when the output of the D-FF 44 is at the H level and the output QD of the counter 47 is at the H level.
The output of the AND gate 45 is input to the AND gate 46, and an enable / inhibit signal ENA for permitting / inhibiting lamp lighting is input to the other input terminal of the AND gate 46. The permission / inhibition signal ENA can be generated using the permission / inhibition signal generation circuit shown in FIG.
[0024]
Since the AND gate 46 generates an L level output when the enable / inhibit signal ENA is at the L level, the output INH of the D-FF 43 is at the L level if the enable / inhibit signal ENA is at the L level. The aforementioned OR gate 42 continues to generate the clock signal CKB.
The counter 47 is, for example, a 4-bit binary counter. The counter 47 counts the clock signal CKB. When eight clock signals CKB are input, the output QD becomes H level, and when the next eight clocks are input, the output QD. Repeats the operation to become L level.
The output of the counter 47 is supplied to the lower delay circuit 51a that generates the gate signal G1, and is also supplied to the lower delay circuit 51b and the D-FF 49a that are inverted by the inverting circuit 48 and generate the gate signal G3.
[0025]
The D-FFs 49a to 49d constitute a delay circuit. When the first clock signal CKB is input, the D-FF 49a is set. When the next clock signal CKB is input, the output of the D-FF 49a is the next. It is set in the D-FF 49b. Similarly, every time the clock signal CKB is input, the D-FF 49c and the D-FF 49d are sequentially set.
That is, the D-FF 49a, D-FF 49b, D-FF 49c, and D-FF 49d output signals delayed by 1, 2, 3, and 4 clock signals, respectively. Therefore, by connecting any of the terminals S1 to S4 with the jumper line J, a necessary delay signal can be taken out.
[0026]
In FIG. 6, the output of the D-FF 49b is taken out and applied to the lower delay circuit 51c and the inverting circuit 50 that generate the gate signal G4. The inverting circuit 50 inverts the output of the D-FF 49b and outputs the inverted signal to the lower delay circuit 51d that generates the gate signal G2.
The lower end delay circuits 51a to 51d are delay circuits provided for adjusting the rising timing of the gate signals G1 to G4, and the outputs of the lower end delay circuits 51a to 51d are gate signals G1 through the inverting circuits 52a to 52d. ~ G4 is output.
[0027]
7 and 8 are diagrams for explaining the operation of the gate signal generation circuit of this embodiment. FIG. 8 is a continuation of FIG. 7, and the dotted lines in FIG. 8 indicate the timing of the clock signals CKA and CKB in FIG.
The operation of this embodiment will be described below with reference to FIGS. 5 and 6 with reference to FIGS.
First, the operation in a state where the enable / disable signal ENA is at the L level and the dielectric barrier discharge lamp is turned on will be described.
When the enable / disable signal is ENA at L level, the output of the D-FF 43 is at L level as described above, and the clock signal CKA (see FIG. 7) output from the oscillator 41 passes through the OR gate 42 and the clock signal CKB. (Refer to FIG. 7), it is given to the counter 47, the D-FF 49a, and the D-FF 44.
The counter 47 counts the clock signal CKB, and as a result, the output QD of the counter 47 changes as shown in FIG.
[0028]
The output QD of the counter 47 is given to the falling edge delay circuit 51a, delayed for a predetermined time when the pulse falls, inverted by the inverting circuit 52a, and output as the gate signal G1 as shown in FIG.
That is, the output of the inverting circuit 52a becomes H level after a predetermined delay time after the signal QD becomes L level, and becomes L level at the same time as the signal QD becomes H level. For this reason, the gate signal G1 with the rising timing delayed as shown in FIG. 8 is generated.
Further, the output QD of the counter 47 is given to the falling end delay circuit 51b and the D-FF 49a through the inverting circuit 48. The falling edge delay circuit 51b delays the fall of the output of the inverting circuit 48 for a predetermined time. The output of the falling edge delay circuit 51b is inverted by the inverting circuit 52b, and is output as a gate signal G3 with the rising timing delayed as shown in FIG.
[0029]
The output of the inverting circuit 48 input to the D-FF 49a is delayed by two clock signals by the D-FF 49a and D-FF 49b, and is provided to the falling edge delay circuit 51c and the inverting circuit 50. The falling edge delay circuit 51c delays the fall of the output of the D-FF 49b for a predetermined time, and this output is inverted by the inversion circuit 52c and output as the gate signal G4 with the rise timing delayed as shown in FIG.
The output of the inverting circuit 50 is given to the falling edge delay circuit 51d. The falling edge delay circuit 51d delays the fall of the output of the inverting circuit 50 for a predetermined time. This output is inverted by the inverting circuit 52d and is output as the gate signal G2 with the rising timing delayed as shown in FIG.
[0030]
By providing the falling edge delay circuits 51a to 51d, it is possible to prevent the switching elements 31a and 31d or the switching elements 31c and 31d from being turned on simultaneously and forming a short circuit.
Further, the period during which the voltage Vs is 0 in FIG. 8 can be changed by changing the connection position of the jumper line J of the delay circuit composed of the D-FF 49a to D-FF 49d. By connecting to the terminal S3 of the D-FF 49c, the period during which the voltage Vs is 0 can be extended by one clock.
[0031]
The switching signals 31a to 31d of the main circuit shown in FIG. 5 are driven by the gate signals G1 to G4, and a high frequency voltage is applied to the step-up transformer 11.
That is, when the gate signal G1 and the gate signal G4 become H level, the switching elements 31a and 31c are turned on, and in this state, the primary winding of the step-up transformer 11 is short-circuited.
Next, when the gate signal G4 becomes L level and the gate signal G2 becomes H level after a predetermined delay time, the switching element 31b is turned on, the DC power supply 34 → the switching element 31a → the primary winding of the step-up transformer 11 → A path from the switching element 31 b to the DC power supply 34 is formed, and a voltage is applied to the primary winding of the step-up transformer 11.
Next, when the gate signal G1 becomes L level and the gate signal G3 becomes H level after a predetermined delay time, the switching element 31d is turned on, and the switching element 31b → the primary winding of the step-up transformer 11 → the switching element 31d. A path is formed, and the primary winding of the step-up transformer 11 is short-circuited.
[0032]
Next, when the gate signal G2 becomes L level and the gate signal G4 becomes H level after a predetermined time, the switching element 31c is turned on, the DC power supply 34 → the switching element 31c → the primary winding of the step-up transformer 11 → the switching element 31d. A voltage is applied to the primary winding of the step-up transformer 11 formed by the path of the DC power supply 34.
By repeating the above operation, a high frequency voltage is applied to the primary winding of the step-up transformer 11, and the voltage Vs shown in FIG. Thereby, the dielectric barrier discharge lamp 1 emits light when the applied voltage changes from 0 to positive and from 0 to negative, and repeats pulsed light emission as described above.
[0033]
Next, the operation when the enable / inhibit signal ENA becomes H level while the lamp 1 is lit as described above will be described.
When the enable / disable signal ENA becomes H level, one input terminal of the AND gate 46 becomes H level. The output of the AND gate 45 is input to the other input terminal of the AND gate 46. The AND gate 45 outputs an output when both the output QI of the D-FF 44 and the output QD of the counter 47 are at the H level. Become H level.
Therefore, as shown in FIG. 7, when both QD and QI are at H level, the other input terminal of AND gate 46 is at H level, and AND gate 46 generates an H level output. The output of the AND gate 46 is input to the D-FF 43, and the output INH of the D-FF 43 becomes H level when the clock signal CKA is input (see INH in FIG. 7).
[0034]
When the signal INH becomes H level, the output of the OR gate 42 becomes H level and the clock signal CKB stops (see CKB in FIG. 7).
For this reason, the counter 47 does not operate, and the operation of the circuit stops when the gate signals G1 and G4 are at the L level and the gate signals G2 and G3 are at the H level, as shown in FIG. Thereby, the switching elements 31a and 31c of the main circuit shown in FIG. 5 are turned off, the switching elements 31b and 31d are turned on, and the primary side of the step-up transformer 11 is short-circuited. Further, no voltage is generated on the secondary side of the step-up transformer 11, and the dielectric barrier discharge lamp stops emitting light.
When the enable / inhibit signal ENA becomes L level again, the output of the D-FF 43 becomes L level, the above operation is started, and the dielectric barrier discharge lamp 1 starts to emit light.
[0035]
In this embodiment, since the circuit operation is stopped in the state where the primary side of the step-up transformer 11 is short-circuited as described above, as shown in FIGS. As described above, the lighting of the lamp can be stopped completely, and when the lighting of the lamp is prohibited, no voltage is applied to the step-up transformer 11. For this reason, saturation of the step-up transformer can be avoided.
In the above embodiment, the lighting of the lamp is stopped when the switching elements 31b and 31d are turned on. However, by appropriately configuring the logic circuit, the lighting of the lamp is performed when the switching elements 31a and 31c are turned on. It can also be stopped.
[0036]
【The invention's effect】
As described above, in the present invention, the dielectric barrier discharge lamp has a rest period. Periodic Apply high voltage of waveform to light up, After stopping the driving of the switching element for lighting the dielectric barrier discharge lamp, Since the primary side of the step-up transformer is short-circuited to prohibit the lighting of the dielectric barrier discharge lamp, the light source device emits light for a period required to measure the afterglow characteristics of the phosphor without saturating the step-up transformer. Can be stopped.
Further, since the last light emission pulse in the light emission pulse train can be stopped so that the light emission pulse train is substantially the same as the previous light emission pulse train, the afterglow characteristics of the phosphor can be accurately measured.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first embodiment of a dielectric barrier discharge lamp light source device according to the present invention.
FIG. 2 is a diagram showing waveforms at various parts of the light source device shown in FIG.
FIG. 3 is a diagram illustrating an example of a permission / prohibition signal generation circuit.
FIG. 4 is a diagram showing measured data of a lamp applied voltage waveform and a lamp emission intensity signal waveform of the light source device of the first embodiment.
FIG. 5 is a diagram showing a main circuit configuration of a full-bridge power feeding circuit according to a second embodiment of the present invention.
FIG. 6 is a diagram showing a configuration of a gate signal generation circuit according to a second embodiment of the present invention.
FIG. 7 is a diagram (1) showing waveforms of respective parts of a second embodiment of the present invention.
FIG. 8 is a diagram (2) showing waveforms of respective parts of the second exemplary embodiment of the present invention.
FIG. 9 is a diagram showing a principle configuration of a dielectric barrier discharge lamp light source device.
FIG. 10 is a diagram showing the lamp emission intensity and the phosphor emission intensity (ideal waveform) capable of measuring the persistence characteristics of the phosphor.
FIG. 11 is a diagram showing a lamp emission intensity and a phosphor emission intensity (a waveform that is not ideal but has no practical problem) that can measure the afterglow characteristics of the phosphor.
12 is a diagram showing measured data of a lamp applied voltage waveform and a lamp emission intensity signal when a switching element of a power feeding circuit is cut off. FIG.
FIG. 13 is a diagram showing the light emission intensity of the phosphor when the light emission intensity of the lamp gradually decreases.
[Explanation of symbols]
1 Dielectric barrier discharge lamp
11 Step-up transformer
12 Switching element
13 Oscillator
14 Gate signal generation circuit
15 ON / OFF control circuit
15a delay circuit
15b D-flip flop
16 Monostable multi-vibrator
17 Damper circuit
18 Switching element
19 Capacitor
20 Resistance.
21 Oscillator
22 Frequency setting means
23 Monostable multivibrator
24 Pulse width setting means
31a to 31d switching element
32a to 32d gate drive circuit
33a to 33d diode
34 DC power supply
41 Oscillator
42 or gate
43,44 D-flip flop
45,46 Andgate
47 counter
48, 50 Inversion circuit
49a-49d D-flip flop
51a-51d bottom delay circuit
52a to 52d inverting circuit

Claims (1)

There is a discharge plasma space filled with a discharge gas that generates excimer molecules by dielectric barrier discharge, and at least one of electrodes of both electrodes for inducing a discharge phenomenon in the discharge gas and the discharge gas In a dielectric barrier discharge lamp light source device having a dielectric barrier discharge lamp having a structure in which a dielectric is interposed in a power supply device for applying a high voltage to the electrode of the dielectric barrier discharge lamp,
The power supply device applies a high voltage having a periodic waveform with a rest period to the dielectric barrier discharge lamp via a step-up transformer by a switching element ,
A dielectric barrier discharge lamp light source device comprising means for short-circuiting a primary side of the step-up transformer after driving of the switching element for lighting the dielectric barrier discharge lamp is stopped .

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