JP3654011B2 - Mask and method for manufacturing semiconductor device using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a mask used in manufacturing various solid-state elements such as a semiconductor element, a superconductor element, a magnetic element, and an optical integrated circuit element, and a method for manufacturing a semiconductor device using the mask.
[0002]
[Prior art]
Conventionally, a reduction projection exposure method, which is one of photolithography methods, has been mainly used to form ultrafine patterns in solid-state devices such as large-scale semiconductor integrated circuits. This method is a method in which a mask pattern formed on a mask or a reticle (hereinafter collectively referred to as a mask) is reduced and transferred onto a substrate using an imaging optical system.
[0003]
In order to manufacture a solid element such as a semiconductor element, it is necessary to superimpose a plurality of layers of circuit patterns on the substrate. When the mask pattern is positioned and transferred with respect to the pattern on the substrate, the position of the mark pattern formed on the substrate is detected, and the mask pattern transfer position is determined from this detection result and positioned and superimposed. Transcript. Here, as a method for detecting the mark pattern position, the pattern formed on the substrate is detected using detection light such as laser light or white light, and the mark pattern edge position is detected from the obtained detection signal. There are a method for obtaining a pattern position, a method for obtaining a mark pattern position by comparing a two-dimensional detection image of a mark pattern with a reference pattern stored in advance in a detection system, and the like.
[0004]
Although the mark pattern is arranged in the exposure shot, there may be a region where the mark pattern cannot be arranged depending on the exposure apparatus used for pattern transfer, but basically it may be at an arbitrary position in the exposure region. .
[0005]
[Problems to be solved by the invention]
For the purpose of expanding process tolerance, etc., the technology used to polish and flatten the substrate surface using substrate flattening technology such as chemical mechanical polishing technology (CMP technology) and chemical mechanical wrapping technology (CML technology). It has been. During planarization, an in-plane distribution of the substrate surface polishing amount occurs depending on the arrangement of patterns formed on the substrate, pattern density, device characteristics, and the like. For this reason, the positioning mark pattern used for overlay exposure in lithography and the overlay deviation measurement pattern (overlay inspection pattern) for measuring the overlay deviation amount as a result of overlay transfer depend on the pattern arrangement and the like. As a result, there is a problem that the measurement pattern variation and measurement error occur, resulting in misalignment of device patterns.
[0006]
[Means for Solving the Problems]
The above problem includes a step of applying a resist film on a base, a step of patterning the resist film by exposure using a mask, and a step of flattening the base after that. A rectangular chip region including a first element region and a second element region; a scribe line region disposed surrounding the chip region; and a positioning mark pattern disposed in the scribe line region. And the positioning mark pattern is arranged in the scribe line region so as to be an intermediate position between the first element region and the second element region, and the pattern arrangement of the first element region The density and the pattern arrangement density of the second element region are symmetric with respect to the positioning mark pattern. The mark pattern for positioning Further, the flattening step is solved by a chemical mechanical polishing method or a chemical mechanical lapping method.
[0007]
Further, the above problem is solved by a method of manufacturing a solid element, which is manufactured by transferring the circuit pattern using the exposure mask, and further using the exposure mask.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
(Example 1)
Hereinafter, the present invention will be described using examples.
[0009]
Here, a manufacturing process of a 256 megabit DRAM (Dynamic Random Access Memory) class large-scale integrated circuit memory element having a minimum design size of 0.2 μm will be described as an example.
[0010]
In this embodiment, a KrF excimer laser (exposure wavelength 248 nm) reduced projection exposure apparatus with a numerical aperture NA = 0.60 and an exposure wavelength of 248 nm and a halftone phase shift mask are used, and the exposure conditions of the exposure apparatus are annular illumination conditions (coherency ( A pattern having a minimum design dimension of 0.2 μm was transferred onto the substrate using a sigma) outer diameter sigma value of 0.8, an inner diameter sigma value of 0.4 and a small sigma illumination condition of a coherency value of 0.3.
[0011]
FIG. 2 schematically shows a mask pattern arrangement state in an exposure shot. In the exposure shot 3, two chips 10-1, 10-2 having the same layout are arranged side by side. A mark pattern for an exposure apparatus used for positioning in overlay exposure, an overlay displacement inspection pattern for measuring an overlay displacement amount, other inspection patterns, and a QC pattern are chips 10-1, 10- which are usually called scribe areas. It is arranged in the area 11 other than 2. The mark pattern for the exposure apparatus includes a cross-shaped mark 33 as schematically shown in FIG. 13, or mark patterns 34 and 35 consisting of a line pattern group as schematically shown in FIGS. Used. As the overlay displacement inspection pattern, for example, a box in box pattern schematically shown in FIG. 12 is used. 12 shows a state where the overlay layer pattern 32 is transferred to the overlay layer pattern 31 formed on the substrate. The overlay deviation amount can be obtained from the relative positional deviation amount of the overlay layer pattern 32 with respect to the overlay layer pattern 31.
[0012]
The patterns in each chip can be roughly divided into a memory cell block 13 in which memory element patterns are collectively arranged and a peripheral circuit pattern area 12 in which patterns for controlling reading and writing of data stored in the memory elements are arranged. Moreover, the pattern density of both was different.
[0013]
The positioning mark pattern used in the exposure apparatus is one for both X and Y directions, when two mark patterns for X direction and Y direction are arranged, and for X direction, Y direction, and shot. For example, there are three mark patterns for rotational measurement.
[0014]
On the other hand, in the substrate flattening process using the CMP method or the like, a polishing amount distribution is generated in the chip and in the wafer depending on the pattern density, pattern arrangement, and polishing apparatus of the pattern formed on the substrate. For example, when a hole pattern is formed on a substrate and the hole is filled with a tungsten film, and then a tungsten film other than the part buried in the hole is polished and planarized by CMP, the hole filled with the tungsten film The polishing rate differs depending on whether the pattern density of the pattern is high or low. In this case, substrate surface irregularities after CMP polishing occur depending on the hole pattern density. For this reason, if the mark pattern is arranged at a location where the CMP polishing rate changes, such as a portion where the peripheral hole pattern density is changing, the mark pattern is asymmetrically polished according to the polishing rate distribution. End up. In the substrate flattening process such as the CMP method, in addition to the polishing distribution depending on the pattern density, a polishing distribution in the wafer surface also occurs. Therefore, the mark pattern arranged in the portion where the polishing speed changes is changed. Polishing variation and asymmetry may be further increased. The polishing asymmetry and the polishing variation as described above cause a mark pattern detection error, and as a result, the overlay accuracy deteriorates.
[0015]
In order to solve the above problem, it is necessary to arrange the mark pattern and the inspection pattern at a position that is not easily affected by the distribution and unevenness of the substrate surface unevenness in the substrate flattening process. For example, the arrangement position of a certain mark pattern may be made symmetrical with respect to the pattern density and arrangement on the substrate around the mark pattern. Hereinafter, an example in which such a pattern arrangement is realized will be described.
[0016]
For example, in the example of FIG. 2, the X mark pattern 14 for the exposure apparatus is disposed so as to overlap the center position 17 between the two chips. The X mark pattern is used for positioning in the X direction. For example, as shown in FIG. 14, a pattern in which a plurality of linear patterns parallel to the Y direction are arranged can be used. Usually, as schematically shown in FIG. 1, exposure shots are repeatedly arranged on a wafer, so the same pattern is repeatedly arranged vertically and adjacently. That is, the pattern density of the arranged pattern is symmetrical with respect to the vertical and horizontal directions of the X mark pattern 14. As a result, a change in the polishing rate near the position where the X mark pattern 14 is arranged is suppressed, and the X mark pattern 14 is flattened and polished symmetrically in the vertical direction and the horizontal direction.
[0017]
Similarly, it is preferable to arrange the Y direction mark at a position where the pattern density of the patterns arranged in the periphery is symmetrical. In the example shown in FIG. 2, the Y mark pattern 15 is arranged so as to overlap the intermediate position 18 of the memory cell block 13 near the center of the chip. The Y mark pattern is used for positioning in the Y direction. For example, as shown in FIG. 15, the mark pattern of FIG. 14 rotated 90 degrees can be used.
[0018]
The mark patterns 14 and 15 had a cross-sectional structure that was directly polished in the substrate planarization process.
[0019]
An example in which the mask pattern having the mark pattern arranged thereon as described above is transferred onto the substrate is schematically shown in FIGS. In FIG. 3, the centers of the mark patterns 15 and 15 ″ are transferred onto the center lines 21-1 and 21-2 of the chip-to-chip boundary and onto the center lines 19-3 of the memory cell blocks 13, 13 ′ and 13 ″. Has been. In FIG. 4, the marks are transferred so that the centers of the mark patterns 15 and 15 ″ overlap on the center lines 21-1 and 21-2 and on the center line 18-2 between the memory cell blocks. Since the pattern density distribution of the patterns arranged in the vicinity of the mark patterns 15 and 15 ″ is symmetrical with respect to the vertical direction and the horizontal direction, the mark patterns 15 and 15 ″ are symmetrically flattened and polished.
[0020]
On the other hand, the overlay misalignment inspection patterns 16-1 to 16-4 may be similarly arranged so that the arrangement positions of the patterns are symmetrical with respect to the pattern density and arrangement around the mark pattern. The inspection patterns 16-1 to 16-4 also have a cross-sectional structure in which the surface is directly polished in the substrate flattening process. In the example shown in FIG. 2, the memory cell blocks 13 are arranged so as to overlap the Y-direction centers 19-1 and 19-2.
[0021]
In the example shown in FIG. 2, the mark patterns 14 and 15 are also preferably arranged at the center of the boundary between chips as a result of transferring the overlay displacement inspection pattern onto the substrate, for example. However, if the overlay misalignment inspection patterns are similarly arranged on the left and right of each shot, the left and right overlay misalignment inspection patterns are superimposed and transferred on the substrate, and thus cannot be used as overlay misalignment inspection patterns. End up. Therefore, in order to keep the symmetry of the peripheral pattern as much as possible and prevent the left and right overlay displacement inspection patterns from being superimposed and transferred on the substrate, for example, as shown schematically in FIG. The overlay displacement inspection patterns 20-1 and 20-2 may be arranged so that 4 is the boundary between the overlay displacement inspection patterns 20-1 and 20-2. At this time, the center positions 21-1 and 21-2 that are the centers of the boundaries between the chips and the centers of the respective inspection patterns can be arranged to overlap each other. When the mask pattern arranged as shown in FIG. 5 is transferred onto the substrate, as shown schematically in FIG. 6, the center lines 21 of the boundaries between the chip E and the chip F and between the chip F and the chip G in FIG. -1, 21-2 and the center of each test pattern 20-1, 20-2, 20-1 ′, 20-2 ′ overlap, and each test pattern is located above and below the center line 19-4 of the memory cell block. Is placed. The same applies to the case where the overlay shift inspection pattern is arranged between the memory cell blocks 13.
[0022]
FIG. 7 shows an example in which overlay displacement inspection patterns 20-1 and 20-2 are arranged side by side on the center line 19-6 of the memory cell block. In this example, the center lines 21-1 and 21-2 at the boundaries between the chip E and the chip F and the chip F and the chip G are arranged symmetrically with respect to the center lines. In this case, the pattern arrangement is symmetrical with respect to the Y direction and substantially symmetrical with respect to the X direction. As a result, the inspection pattern is flattened and polished almost symmetrically, so that detection errors due to the polishing distribution and the like can be suppressed.
[0023]
By the way, in actual device manufacturing, a substrate planarization process may be performed with a plurality of layers. In this case, it becomes difficult to arrange all the mark patterns at optimal positions. Therefore, priorities are assigned to the transfer pattern layers, and the transfer pattern layers are arranged in order from the optimum arrangement position. Here, as a priority order, it may be arranged from the one that is easily influenced by the substrate flattening polishing variation and the one that has a higher required overlay accuracy. For example, in the example shown in FIG. 8, the overlay misalignment inspection patterns are arranged three on one side up and down about the Y-direction center line 19-4 of the memory cell block 13, but the overlay misalignment inspection pattern 20-1 is arranged. And 20-2 are patterns that are most easily affected by polishing and are used when measuring overlay deviation between layers that require the highest overlay accuracy. Here, the inspection patterns 20-1 and 20-2 are the same pattern. Patterns 20-3 and 20-4 were easily affected by polishing after pattern 20-1, and were used as interlayer misalignment measurement patterns that required the same overlay accuracy as pattern 20-1. The pattern 20-5 is easily affected by polishing to the same extent as the pattern 20-3, but the required overlay accuracy is a layer misalignment measurement pattern larger than the pattern 20-3. The reason why the right and left sides of the chip are arranged separately above and below the center line 19-4 is to prevent the left and right patterns from overlapping on the wafer as described with reference to FIG. The pattern 20-3 and the pattern 20-4 are the same, and the pattern 20-5 and the pattern 20-6 are the same pattern.
[0024]
Similarly, the positioning mark patterns used for overlay exposure by the exposure apparatus may be arranged in order from the optimum position with priorities. For example, in the example shown in FIG. 9, the mark patterns 15-1, 15-2, 15-3, and 15-4 are in order of being easily affected by variations in planarization polishing.
[0025]
In the example shown in FIG. 10, the patterns are arranged so that the pattern density in the shot is distributed almost symmetrically with respect to the X and Y directions with respect to the shot center. For this reason, for example, on the center lines 19-7 to 19-10 of the memory cell block 13, on the center lines 18-1 to 18-3 between the memory cell blocks 13, on the center line 17 of the chip-chip boundary, shot When the pattern is transferred onto the substrate at the four corner positions, the peripheral pattern density becomes substantially symmetrical. Therefore, the X mark patterns 27 and 28 used in the overlay exposure are placed on the intersection of the center 21-4 and the center lines 19-7 and 17 of the scribe area below the shot, and the Y mark patterns 25 and 26 are placed on the scribe area on the left side of the shot. The center 21-1 and the center lines 19-9 and 18-1 are arranged on the intersections. Further, the overlay misalignment inspection patterns 16-1 to 16-4 are arranged on the center lines 19-8 and 19-10 of the memory cell block 13 so as not to overlap the scribe areas on the left and right sides of the shot when the pattern is transferred onto the substrate. It arrange | positioned up and down and on the centerlines 21-1 and 21-2 of a scribe area | region.
[0026]
In addition, overlay misalignment inspection patterns 24-1 to 24-4 were also arranged at the four corners of the shot. A schematic diagram of the pattern transferred onto the substrate at the shot corner is shown in FIG. The shot arrangement shown in FIG. 1 will be described as an example. Overlay displacement inspection patterns 24-1 to 24-4 are transferred to corner portions of shots where chips A, B, C, and D are in contact. Here, 24-1 is arranged at the lower left corner of chip B, 24-2 is arranged at the upper left corner of chip D, 24-3 is arranged at the upper right corner of chip C, and 24-4 is arranged at the lower right corner of chip A. . The center lines 21-3 and 19-8 at the boundary between the chips coincide with the center line of the scribe area on the four sides of the shot. In the example shown in FIG. 10, since the pattern density in the chip is substantially symmetric with respect to the vertical and horizontal directions, the peripheral pattern density with respect to the four corner positions of the shot is substantially symmetric. Therefore, the inspection patterns 24-1 to 24-4 are polished symmetrically in the substrate flattening process.
[0027]
In the example shown in FIG. 10, the mark patterns 25 and 27 have a cross-sectional structure in which the silicon oxide film laminated on the mark pattern is polished in the substrate planarization process. That is, the mark pattern detection error is suppressed by making the silicon oxide film thickness on the mark pattern after the substrate flattening step uniform.
[0028]
(Example 2)
Next, for the manufacturing process of a large-scale integrated circuit device in which both a 64 megabit DRAM (dynamic random access memory) grade semiconductor memory device with a minimum design size of 0.2 μm and a semiconductor logic device with a gate size of 0.25 μm are integrated on the same chip. The mask pattern of the mask will be described as an example. The pattern arrangement is schematically shown in FIG. A scribe area 11, a memory element area 41, and a logic element area 40 are arranged in the exposure shot 3. Here, the pattern density of the pattern formed on the substrate and planarized and polished during the substrate planarization process is different between the memory element region 41 and the logic element region 40. Further, the pattern arrangement density in each region was substantially uniform, and the change in the pattern density in each region was such that the change in the polishing rate of the substrate flattening polishing was within a sufficiently small range.
[0029]
The center of the X mark pattern 30 is the center line 44 in the X direction of the chip so that the center of the Y mark pattern 29 used for the overlay exposure by the exposure apparatus overlaps the center line 42 in the Y direction of the memory element region 41. It arranged so that it might overlap. The overlay displacement inspection patterns 16-1 to 16-4 are arranged above and below the center line 42 and the center line 43. Here, since the Y mark pattern 29 is preferentially arranged on the center line 42, the amount of misalignment between the circuit pattern formed on the substrate and the circuit pattern transferred by detecting and positioning the Y mark pattern 29 is determined. The overlay displacement inspection patterns 16-1 and 16-2 for measuring the above are arranged above and below the Y mark pattern 29. The mark patterns 29 and 30 have a pattern cross-sectional structure polished by a CMP process which is a substrate flattening process. Similarly, the reference side patterns of the overlay inspection patterns 16-1 to 16-4 have a cross-sectional structure polished in the CMP process.
[0030]
The positions where the mark patterns and the overlay inspection pattern are arranged are the positions near the symmetry axis of the pattern density distribution of the patterns arranged in the periphery.
[0031]
(Example 3)
FIG. 17 is a diagram schematically showing a pattern arrangement of another memory / logic mixed semiconductor device in which a memory element and a logic element are formed on the same chip. A logic element area 40 and memory element areas 41-1 and 41-2 are arranged in the chip 3. The density of the pattern polished and planarized in the substrate planarization process was different between the logic element region 40 and the memory element regions 41-1 and 41-2. Further, the pattern density of the patterns of the other layers was also different between the logic element region 40 and the memory element regions 40-1 and 40-2.
[0032]
In this example, the Y mark pattern 29 is arranged on the center line 43 of the logic element region and on the center line 21-1 of the scribe region. Similarly, the X mark pattern 30 was arranged on the chip center line 44 and on the center line 21-4 of the scribe area. The overlay displacement inspection patterns 24-1 to 24-4 were arranged at the four corner positions of the chip. Also in this case, the mark pattern and overlay inspection pattern arrangement positions are positions where the peripheral pattern arrangement is substantially symmetric.
[0033]
In the state where the pattern is transferred onto the substrate, the center line 21-1 and the center line 21-2 of the scribe area of the shots adjacent to the left and right are transferred in an overlapping manner. Similarly, the center line 21-3 and the center line 21-4 of the scribing area of shots adjacent to each other in the vertical direction overlap and are transferred. The target patterns 29 and 30 and the overlay displacement inspection patterns 24-1 to 24-4 have a pattern cross-sectional structure that is flattened and polished in the substrate flattening process. In addition, the overlay displacement inspection patterns 16-9 and 16-10 are polished in the substrate surface flattening step by the silicon oxide film laminated on the pattern formed by the overlay layers of the inspection patterns 16-9 and 16-10. The cross-sectional structure was as follows. The overlay misregistration inspection patterns 24-1 to 24-4, 16-1, and 16-2 all detect the mark patterns 29 and 30 and are positioned and overlapped with respect to the overlay layer pattern formed on the substrate. This is used when measuring the overlay accuracy of the overlay layer pattern subjected to the alignment exposure and the overlay layer pattern.
[0034]
As described above, when a mark pattern is arranged, if there are a plurality of mark patterns to be arranged, the mark pattern is symmetrically polished or at a position where the asymmetric polishing amount is sufficiently small in the vicinity thereof. It cannot always be arranged. In such a case, for example, as schematically shown in FIG. 18, a dummy pattern 37 may be arranged around the mark pattern 36 to improve the polishing symmetry of the mark pattern 36. In this case, the arrangement of the dummy pattern is desirably set to a pattern shape, a pattern density, and an arrangement region size that can sufficiently suppress the asymmetric shaving of the mark pattern due to polishing.
[0035]
(Example 3)
FIG. 19 shows an example of the configuration of an exposure apparatus that realizes a mask pattern exposure method using a mask manufactured using the mask pattern layout method of the present invention. The light emitted from the light source 71 illuminates the mask 77 via the fly-eye lens 72, the aperture 70, the condenser lenses 73 and 75, and the mirror 74. Of the optical conditions, the coherency was adjusted by changing the size of the opening of the aperture 76.
[0036]
A pellicle 78 is provided on the mask 77 to prevent pattern transfer failure due to foreign matter adhesion. The mask pattern drawn on the mask 77 is projected onto a wafer 81 that is a sample substrate via a projection lens 80. The mask 77 is placed on the mask stage 79 controlled by the mask position control means 91, and the center of the mask 77 and the optical axis of the projection lens 80 are accurately aligned.
[0037]
The wafer 81 is vacuum-sucked on the sample stage 82. The sample stage 82 is mounted on a Z stage 83 that can move in the optical axis direction of the projection lens 80, that is, the Z direction, and is further mounted on the XY stage 84. Since the Z stage 83 and the XY stage 84 are driven by the respective driving means 87 and 88 in accordance with a control command from the main control system 89, they can be moved to a desired exposure position. The position is accurately monitored by the laser length measuring machine 85 as the position of the mirror 86 fixed to the Z stage 83. In addition, the surface position of the wafer 81 is measured by a focus position detection unit included in a normal exposure apparatus. By driving the Z stage 83 according to the measurement result, the surface of the wafer 81 can always coincide with the image plane of the projection lens 80.
[0038]
When the circuit pattern on the mask 77 is superimposed and exposed on the circuit pattern formed on the wafer 81, the position of the mark pattern formed on the wafer 81 is detected using the alignment detection optical system 93, and the detection result Then, the wafer 81 is positioned and superimposed and transferred.
[0039]
The main control system 89 is connected to the network device 94 and can remotely monitor the exposure apparatus status.
[0040]
(Example 4)
FIG. 20 is a schematic cross-sectional view showing a part of the semiconductor integrated circuit device manufactured in this example. The figure shows a cross section in the step of laminating an insulating film after forming the storage electrode. A P-type Si semiconductor 101 is used as a substrate, and a buried element isolation region 102 is formed on the surface using a known element isolation technique. Next, for example, a word line 105 having a structure in which polycrystalline silicon having a thickness of 150 nm and silicon oxide having a thickness of 200 nm is stacked is formed. A data line contact pattern 108 for connecting the element region 100 and the data line 109 is formed through a normal process, and further, a data line 109 made of polycrystalline silicon, refractory metal silicide, or a laminated film thereof is formed. A storage electrode 114 made of polycrystalline silicon is formed. Thereafter, tantalum pentoxide is deposited to form a capacitor insulating film 115. As the capacitor insulating film, in addition to tantalum pentoxide, silicon nitride, silicon oxide, ferroelectric, or a composite film thereof can be used. Subsequently, a plate electrode 116 is formed by depositing a low-resistance conductor such as polycrystalline silicon, refractory metal, refractory metal silicide, or Al or Cu. Here, only a typical manufacturing process has been described, but a normal element manufacturing process is used except for this.
[0041]
In the example shown here, for example, in order to form the data line contact pattern 108, a contact hole is formed using a resist pattern as a mask, and then a tungsten film is laminated. Then, the substrate surface is polished by CMP and only in the contact hole. A tungsten film was left. In the resist pattern transfer process for forming the data line 109, the mark pattern formed simultaneously with the formation of the data line contact pattern 108 was used, so that the cross-sectional structure was polished in the substrate planarization process. Therefore, the mark pattern and overlay inspection pattern used at this time are arranged at positions where the pattern densities of the peripheral patterns are symmetric as described above.
[0042]
Next, the pattern formed in the lithography process for manufacturing the above-described semiconductor integrated circuit device will be described. FIG. 21 shows a pattern arrangement of a memory part of a typical pattern constituting the manufactured semiconductor integrated circuit element. The patterns of the word line 122, the data line 124, the active region 121, the data line contact hole 123, the storage electrode 126, and the electrode extraction hole 125 are arranged. In this embodiment, a halftone phase shift mask is used for pattern transfer of the word line 122 and the data line 124, and a Levenson type phase shift mask is used for pattern transfer of the storage electrode 126. A halftone phase shift mask was also used for pattern transfer of the data line contact hole 123 and the electrode extraction hole 125.
[0043]
Since the mark pattern and overlay inspection pattern transferred simultaneously with the data line contact hole 123 are used when transferring the pattern of the data line 126, these patterns are arranged at positions where the pattern densities of the peripheral patterns are symmetric as described above. did.
[0044]
By using the mask manufactured as described above, it is possible to suppress asymmetric polishing of the mark pattern and the overlay inspection pattern in the substrate flattening process. it can. Thereby, the overlay accuracy is improved, and as a result, the large-scale integrated circuit element can be manufactured with a high yield.
[0045]
Needless to say, the exposure means is not limited to an excimer laser such as KrF or ArF, but EB or EUB may be used.
[0046]
【The invention's effect】
As described above, according to the present invention, it is possible to suppress the asymmetric polishing of the mark pattern and the overlay inspection pattern in the substrate flattening step, so that it is possible to suppress the mark pattern detection error and realize highly accurate overlay. Furthermore, this makes it possible to manufacture solid elements with a high yield.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing an example of an exposure shot arrangement on a substrate.
FIG. 2 is a schematic diagram showing an embodiment of the present invention.
FIG. 3 is a schematic diagram showing an example of a pattern arrangement according to the present invention.
FIG. 4 is a schematic diagram showing an example of a pattern arrangement according to the present invention.
FIG. 5 is a schematic diagram showing an example of a pattern arrangement according to the present invention.
FIG. 6 is a schematic diagram showing an example of a pattern arrangement according to the present invention.
FIG. 7 is a schematic diagram showing an example of a pattern arrangement according to the present invention.
FIG. 8 is a schematic diagram showing an example of a pattern arrangement according to the present invention.
FIG. 9 is a schematic diagram showing an example of a pattern arrangement according to the present invention.
FIG. 10 is a schematic diagram showing an example of a pattern arrangement according to the present invention.
FIG. 11 is a schematic diagram showing an example of a pattern arrangement according to the present invention.
FIG. 12 is a schematic diagram showing an example of a registration error inspection pattern.
FIG. 13 is a schematic diagram showing an example of a target pattern for overlay exposure.
FIG. 14 is a schematic diagram showing an example of an X-direction target pattern for overlay exposure.
FIG. 15 is a schematic diagram showing an example of a Y-direction target pattern for overlay exposure.
FIG. 16 is a schematic diagram showing an example of a pattern arrangement according to the present invention.
FIG. 17 is a schematic diagram showing an example of a pattern arrangement according to the present invention.
FIG. 18 is a schematic diagram showing an example of a target pattern according to the present invention.
FIG. 19 is a schematic diagram showing the configuration of an exposure apparatus.
FIG. 20 is a schematic view showing a part of a cross section of a semiconductor device manufactured in an example.
FIG. 21 is a pattern diagram schematically showing a semiconductor device manufactured in an example.
[Explanation of symbols]
1: substrate, 2: exposure shot, 3: chip pattern area, 4: scribe area, 10-1, 10-2: chip, 11: scribe area, 12, 12 ′, 12 ″: first pattern area, 13 , 13 ′, 13 ″: second pattern area, 14: X mark pattern, 15, 15 ′, 15-1 to 15-4, 15-1 ′ to 15-4 ′: Y mark pattern, 16-1 to 16-10: Overlay displacement inspection pattern, 17: Chip boundary center line, 18-1: Center line between second pattern areas, 19-1 to 19-10: Center line of second pattern area, 20- 1-20-6: Overlay displacement inspection pattern, 21-1 to 21-3: Center line of chip boundary, 24-1-24-4: Overlay displacement inspection pattern, 25, 26, 29: Y mark pattern, 27, 28, 30: X mark pattern, 31: Overlaid Pattern, 32: Superposed layer pattern, 33, 34, 35: Mark pattern, 36: Mark pattern, 37: Dummy pattern, 40: Logic element circuit area, 41: Memory element circuit area, 42: Center in Y direction of memory element area Line: 43: Y direction center line of logic element region, 44: X direction center line of chip, 70: Aperture, 71: Light source, 72: Fly eye lens, 73, 75: Condenser lens, 74: Mirror, 77: Mask 76: Aperture, 78: Pellicle, 80: Projection lens, 81: Wafer 91: Mask position control means, 79: Mask stage, 82: Sample stage, 83: Z stage, 84: XY stage, 89: Main control system, 87, 88: Driving means, 86: Mirror, 85: Laser length measuring machine, 93: Alignment detection optical system, 94: Network device, 101: Half Conductor substrate, 102: buried element isolation region, 105: word line, 108: data line, 114: storage electrode, 115: capacitor insulating film, 116: plate electrode, 122: word line, 124: data line, 121: Active region, 123: data line contact hole, 126: storage electrode, 125: electrode extraction hole.

Claims (4)

Applying a resist film on the substrate;
Exposing with a mask and patterning the resist film;
And then flattening the substrate,
The mask includes a rectangular chip region including a first element region and a second element region, a scribe line region disposed around the chip region, and a positioning chip disposed in the scribe line region. And the positioning mark pattern is disposed in the scribe line region so as to be an intermediate position between the first element region and the second element region, and the first element The positioning mark pattern is arranged at a position where the pattern arrangement density of the region and the pattern arrangement density of the second element region are symmetric with respect to the positioning mark pattern. A method for manufacturing a semiconductor device. It said step of planarization method according to claim 1, wherein the by chemical mechanical polishing method or chemical mechanical lapping. Applying a resist film on the substrate;
Exposing with a mask and patterning the resist film;
And then flattening the substrate by polishing,
The mask includes a first chip region and a second chip region including a plurality of rectangular element regions, a scribe line region disposed so as to surround the first chip region and the second chip region, A positioning mark pattern disposed in the scribe line area, the positioning mark pattern in the scribe line area being an intermediate position between the first chip area and the second chip area. And the pattern arrangement density of the first element region disposed in the vicinity of the positioning mark pattern in the first chip region, and in the vicinity of the positioning mark pattern in the second chip region. the second and the pattern arrangement density of the device region, the mark pattern for the positioning to a position so as to be symmetrical with respect to the mark pattern for the positioning arranged The method of manufacturing a semiconductor device characterized by being arranged. Applying a resist film on the substrate;
Exposing with a mask and patterning the resist film;
And then flattening the substrate by polishing,
The mask includes a rectangular chip region including a first element region and a second element region, a scribe line region disposed around the chip region, and a positioning chip disposed in the scribe line region. A pattern arrangement density in the first element region is substantially uniform, and the positioning mark pattern is an intermediate position between sides facing each other in the first element region. The method for manufacturing a semiconductor device is characterized in that the semiconductor device is disposed in the scribe line region so that

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