JP3662438B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and is effectively used for, for example, a device including an amplifier circuit that receives a small-amplitude high-frequency signal formed by an oscillation circuit and forms a clock signal with a duty of approximately 50%. Technology.
[0002]
[Prior art]
In a digital integrated circuit, a small amplitude signal formed by an oscillation circuit is amplified and converted into a binary signal having a first level corresponding to the power supply voltage and a second level corresponding to the ground potential of the circuit. Some of them generate a clock signal necessary for the operation. As the amplifier circuit, a simple circuit such as a single-ended differential amplifier whose gain can be set relatively large can be used when the oscillation frequency is relatively low.
[0003]
[Problems to be solved by the invention]
When a high-speed clock signal exceeding 500 MHz, for example, is formed as the digital integrated circuit speeds up, it is generally necessary to use a single-ended differential amplifier as described above, because gain cannot be increased when the amplifier band is increased. A large gain cannot be secured. Therefore, the inventors of the present application considered that two differential amplifiers are connected in cascade as shown in FIG. 2 to ensure a high bandwidth and a necessary gain. In this case, a fully differential differential amplifier is used to connect the differential amplifiers in series. When amplifying the small-amplitude signal as described above, in order to operate the differential MOSFETs M16 and M17 in the next stage in the saturation region, MOSFETs M3 and D3 connected in parallel with the load MOSFETs M2 and M4 of the constant current source of the first-stage amplifier are used. M5 is connected to determine the output operating point.
[0004]
In this way, the load circuits provided at the drains of the amplification MOSFETs M14 and M15 are the constant-current MOSFET M2 connected in parallel, the diode-connected MOSFET M3, the constant-current MOSFET M4, and the diode-connected MOSFET M5, respectively. The gain is smaller than that of the end-type differential amplifier, and a sufficient gain cannot be obtained even when connected in a two-stage series configuration as shown in FIG. In addition, the differential amplifier at the output stage requires a dummy inverter circuit to balance the output, which complicates the circuit and increases the current consumption accordingly. As will be described later, the output pulse rise time tr and The inventors of the present application have found that the fall time td is poorly balanced and the pulse duty deviates from 50%.
[0005]
An object of the present invention is to provide a semiconductor integrated circuit device including an amplifier circuit that realizes high speed and high gain. An object of the present invention is to provide a semiconductor integrated circuit device including an amplifier circuit that forms a high-frequency clock signal with a simple configuration. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0006]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. A first conductivity type first and second amplification MOSFET having a differential configuration; a second conductivity type first MOSFET having a gate and a drain connected to a drain of the first amplification MOSFET; and the first MOSFET A first single-ended differential amplifier including a second conductivity type second MOSFET having a gate and a source connected to form a current mirror and having a drain connected to the drain of the second amplification MOSFET; A third conductivity type third and fourth amplification MOSFETs, a second conductivity type third MOSFET having a gate and a drain connected to a drain of the third amplification MOSFET, the third MOSFET, a gate and a source; Connected to form a current mirror, the drain of which is connected to the drain of the fourth amplification MOSFET. A second single-ended differential amplifier including 4 MOSFETs, and a small-amplitude input signal having a phase opposite to each other is supplied to the gates of the first and second amplifying MOSFETs. The drain output signal of the second amplification MOSFET is input to the gate of the third amplification MOSFET of the amplifier, and the drain output signal of the first amplification MOSFET is input to the gate of the fourth amplification MOSFET. The output signal is obtained from the drain of the 4 amplification MOSFET.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit diagram showing one embodiment of an amplifier circuit provided in a semiconductor integrated circuit device according to the present invention. In this embodiment, two single-ended differential amplifiers are used to realize a high gain. The input signals INY and INX supplied to the amplifier circuit including the two single-ended differential amplifiers are formed by an oscillation circuit (not shown), for example, and have a small signal amplitude (for example, about 0.5 V) with respect to the power supply voltage VDD. ) And are in opposite phase to each other. The oscillation circuit is, for example, an oscillation circuit using a crystal resonator. The amplifier circuit amplifies the oscillation signal with the small amplitude, converts the amplified signal into a pulse signal corresponding to the ground potential GND (0 V) of the circuit of the power supply voltage VDD (for example, about 3 V), and forms it as a clock pulse in the semiconductor integrated circuit device. Supplied to the internal circuit.
[0008]
Among the two single-ended differential amplifiers, the differential amplifier on the input (previous stage) side includes differential P-channel amplification MOSFETs M1 and M2, a source connected in common, and a power supply voltage VDD. And a constant current source I1 provided between the drains of the amplification MOSFETs M1 and M2 and the ground potential GND of the circuit, and P-channel load MOSFETs M3 and M4 in the form of a current mirror. The One input signal INX of the differential inputs is supplied to the gate of the amplification MOSFET M1, and the gate of the differential input that is in the opposite phase to the one input signal INX is supplied to the gate of the amplification MOSFET M2. The other input signal INY is supplied. Although not particularly limited, a constant current 2Ids flows through the constant current source I1.
[0009]
Among the two single-ended differential amplifiers, the differential amplifier on the output (rear stage) side includes differential P-channel amplification MOSFETs M5 and M6, their commonly connected source, and power supply voltage VDD. A constant current source I2 provided between the drains of the amplification MOSFETs M5 and M6 and the ground potential GND of the circuit, and P-channel type load MOSFETs M7 and M8 in the form of a current mirror. The In this embodiment, in order to prevent the deterioration of the pulse duty, in other words, in order to ensure the duty of approximately 50% by equalizing the rising tr and falling td of the pulse, the gate of the amplification MOSFET M5 is connected to the input stage. The drain output of the amplification MOSFET M2 is supplied, and the drain output of the amplification MOSFET M1 in the input stage is supplied to the gate of the amplification MOSFET M6. The constant current source I2 is supplied with the same constant current 2Ids as the current source I1.
[0010]
In this embodiment, in order to prevent the pulse duty from deviating from 50% as described above, the connection of two single-ended differential amplifiers is devised. That is, out of the two load MOSFETs M3 and M4 of the current mirror circuit constituting the input side differential amplifier, the drain output of the amplification MOSFET M1 corresponding to the diode-connected input side load MOSFET M3 is opposite to the output side. Of the two load MOSFETs M7 and M8 of the current mirror circuit constituting the differential amplifier, the voltage is supplied to the gate of the amplification MOSFET M6 corresponding to the load MOSFET M8 on the output side that is not diode-connected. Of the two load MOSFETs M3 and M4 of the current mirror circuit constituting the input-side differential amplifier, the drain output of the amplification MOSFET M2 corresponding to the output-side load MOSFET M4 that is not diode-connected is reversed to the difference on the output side. Among the two load MOSFETs M7 and M8 of the current mirror circuit constituting the dynamic amplifier, the voltage is supplied to the gate of the amplification MOSFET M5 corresponding to the load MOSFET M7 on the input side which is diode-connected.
[0011]
In this way, when two single-ended differential amplifiers are connected in series, the relationship between the input and output is crossed and connected as described above. This is because, when viewed from the differential amplifier on the input side, the current flowing through the source of the amplification MOSFET M1 includes the current that drives the gate capacitances of the load MOSFETs M3 and M4. Then, it becomes imbalance like M1: M2 = 49: 51. Similarly, if the input signal is the same, the differential amplifier on the output side also has an unbalance such as M5: M6 = 49: 51. Therefore, by making the connection as shown in the figure, the imbalance of the output signal generated by the input-side differential amplifier can be corrected by the imbalance of the signal transfer characteristics of the output-side differential amplifier.
[0012]
In order to accurately correct the unbalance of the signal transmission characteristics as described above, the element constants of the differential amplification MOSFETs M1 and M2 on the input side and the corresponding amplification MOSFET M5 on the output side are the same, in other words, the same. It is formed in the element size. Similarly to the above, the input side load MOSFETs M3 and M4 in the form of current mirrors, the corresponding output side load MOSFETs M7 and M8, and the constant current sources I1 and I2 also correspond to each other in the same manner as described above. The size is assumed to be the same.
[0013]
In this embodiment, the output signal of the differential amplifier on the output side is transmitted to a constant current inverter amplifier including an N channel type MOSFET M9 and a constant current source I4. An even number of such inverter amplifiers are connected in series to form a clock pulse supplied to a digital circuit or the like. In the figure, there are two inverter amplifiers composed of MOSFET M9 and constant current source I3, MOSFET M10 and constant current source I4, and a total of six inverter amplifiers INV1 to INV4.
[0014]
These inverter amplifiers have their current drive capability sequentially increased to have a necessary current drive capability in the final stage. In this case, a constant current load is used so that the currents flowing in the power supply lines VDD and GND are constant, the inverter amplifiers are even numbers, and two are paired so that a constant current always flows regardless of the signal change. To be. By making the current flowing through the power supply line constant in this way, it is possible to suppress the generation of unwanted noise due to the parasitic inductance component of the bonding wire for power supply.
[0015]
Since the amplifier circuit of this embodiment has a high bandwidth and a large gain as described above, noise generated in the power supply lines VDD and GND cannot be ignored, but an inverter amplifier as described above is used. Thus, a stable amplification operation can be performed.
[0016]
FIG. 3 is a waveform diagram for explaining the present invention. This figure shows the drain output waveform of the constant current inverter amplifier M9 shown in FIG. 1 and the output waveform of the same inverter amplifier when the fully differential amplifier shown in FIG. 2 is used. This output waveform is formed by computer simulation. The solid line in the figure is the waveform diagram shown in FIG. 1 according to the present invention. As shown in (a), the rising tr and the falling td are almost the same, and a pulse duty of about 50% is realized. doing. In contrast, in the circuit shown in FIG. 2, the overall gain is insufficient as shown by the dotted line, and the fall td becomes slower than the rise tr, resulting in a pulse duty of 50% or less. It has been. When this duty variation is quantitatively calculated, it is ± 3.5% in the case of FIG. 1, but also reaches ± 8% in the case of FIG.
[0017]
FIG. 4 is a schematic block diagram showing an embodiment of a magnetic disk memory device to which the present invention is applied. A magnetic disk memory device exchanges a read / write signal between a plurality of disks having a magnetic recording surface, a drive device that rotates the disk, a head that performs recording and reproduction on the disk surface, and the head. It comprises a read / write (R / W) LSI (integrated circuit) and a signal processing LSI and controller for transferring signals to and from the R / W LSI.
[0018]
The amplifier circuit of this embodiment is provided in a signal processing LSI. The AGC circuit of the signal processing LSI detects the signal amplitude for each channel corresponding to each head, performs automatic gain control so that the signal amplitude becomes constant, and supplies the signal to the servo circuit through the active filter AF. The cut-off frequency of the active filter AF controls an ADC (analog / digital comparator) by a register, and is set to a frequency corresponding to the output current of the DAC.
[0019]
The ADC includes a chopper type comparator operated by a clock pulse, and the clock pulse is set to a high frequency as described above for high accuracy and high speed. Although not particularly limited, the high-frequency signal having a small amplitude of about 500 MHz is formed by the oscillation circuit included in the VCO in synchronization with the clock signal component included in the read signal. It amplifies and generates a clock pulse, which is supplied to the ADC or digital circuit.
[0020]
The effects obtained from the above embodiment are as follows. That is,
(1) A second conductivity type first MOSFET having a gate and a drain connected to the drain of the first conductivity type first amplifying MOSFET is connected, and the drain of the second MOSFET in the form of a current mirror is connected to the first MOSFET. Two single-ended differential amplifiers connected to the drain of the first amplification MOSFET and the second amplification MOSFET in the differential form are connected in series, and a small-amplitude input signal having a phase opposite to each other is connected to the differential amplifier in the previous stage. The drain output signal of the second amplifying MOSFET is input to the gate of the MOSFET corresponding to the first amplifying MOSFET of the single-ended differential amplifier in the subsequent stage, and the MOSFET corresponding to the second amplifying MOSFET is input. Corresponding to the second amplification MOSFET by inputting the drain output signal of the first amplification MOSFET to the gate By obtaining an output signal from the drain of the MOSFET, the imbalance of the high-gain single-ended differential amplifier is corrected, and an effect of achieving high speed and high gain can be obtained.
[0021]
(2) The first and second single-ended differential amplifiers correct the output imbalance of the single-ended differential amplifier with high accuracy by forming corresponding elements in the same element size. The effect of being able to be obtained.
[0022]
(3) The first and second input signals that are out of phase with each other are formed by an oscillation circuit, the signal amplitude is small with respect to the power supply voltage, and the output signal is a large amplitude signal corresponding to the power supply voltage. As a result, an effect that a high-frequency clock pulse can be formed is obtained.
[0023]
(4) By providing an even number of inverter circuits composed of an amplifying MOSFET and a constant current load for amplifying the output signal of the amplifying circuit, the current flowing through the power supply line can be made constant while ensuring the necessary driving capability. Noise generated in the power supply line can be reduced, and an effect that a stable amplification operation can be performed is obtained.
[0024]
The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, the amplification MOSFET may be an N-channel MOSFET, and the load MOSFET in the current mirror form may be a P-channel MOSFET. The constant current inverter amplifier can be omitted if the input capacity of the load circuit to which the output pulse is supplied is small and the current driving capability may be small. The constant current inverter amplifier may be composed of a P channel type amplification MOSFET and an N channel type constant current source MOSFET. The present invention can be widely used for a semiconductor integrated circuit device having an amplifier circuit with a high frequency and a high gain.
[0025]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. In other words, the first conductivity type first amplification MOSFET is connected to the drain of the second conductivity type first MOSFET whose gate and drain are connected, and the drain of the second MOSFET in the form of a current mirror is connected to the first MOSFET. Two single-ended differential amplifiers connected in series to the amplification MOSFET and the drain of the second amplification MOSFET in differential form are connected in series, and a small-amplitude input signal having opposite phases is supplied to the differential amplifier in the previous stage. The drain output signal of the second amplification MOSFET is input to the gate of the MOSFET corresponding to the first amplification MOSFET of the single-ended differential amplifier in the subsequent stage, and the gate of the MOSFET corresponding to the second amplification MOSFET is input. Input the drain output signal of the first amplification MOSFET to the second amplification MOSFET. By the drain of response was MOSFET to obtain an output signal, it can be unbalanced single-ended differential amplifier a high gain is corrected to realize high speed and high gain.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of an amplifier circuit provided in a semiconductor integrated circuit device according to the present invention.
FIG. 2 is a circuit diagram showing an example of an amplifier circuit studied prior to the present invention.
FIG. 3 is a waveform diagram for explaining the present invention.
FIG. 4 is a schematic block diagram showing an embodiment of a magnetic disk memory device to which the present invention is applied.
[Explanation of symbols]
M1 to M17 MOSFETs, I1 to I4 constant current sources, INV0 to INV4 constant current inverter amplifiers.

Claims (2)

A first conductivity type first amplification MOSFET and a second amplification MOSFET in a differential configuration; a second conductivity type first MOSFET in which a gate and a drain are connected to a drain of the first amplification MOSFET; and A first single-ended differential amplifier including a second MOSFET of a second conductivity type in which a gate and a source are connected to form a current mirror, and a drain thereof is connected to a drain of the second amplification MOSFET;
A first amplification type third amplification MOSFET and a fourth amplification MOSFET in a differential configuration; a second conduction type third MOSFET having a gate and a drain connected to the drain of the third amplification MOSFET; and the third MOSFET, A second single-ended differential amplifier including a gate and a source connected to form a current mirror, and a drain of the second conductivity type connected to the drain of the fourth amplifying MOSFET ;
An amplification MOSFET for amplifying the output signal of the second single-ended differential amplifier and an even number of inverter circuits composed of constant current loads;
The gates of the first and second amplification MOSFETs of the first single-ended differential amplifier are supplied with input signals which are formed by an oscillation circuit and have opposite signal phases with a small signal amplitude with respect to the power supply voltage. ,
The drain output signal of the second amplification MOSFET is supplied to the gate of the third amplification MOSFET of the second single-ended differential amplifier, and the drain output of the first amplification MOSFET is supplied to the gate of the fourth amplification MOSFET. signal is supplied, an amplification circuit to obtain an output signal from the drain of the fourth amplifier MOSFET,
In the first and second single-ended differential amplifiers, corresponding elements are formed to have the same element size,
A semiconductor integrated circuit device characterized in that the output signal that has passed through the even number of inverter circuits is a large amplitude signal substantially corresponding to the power supply voltage . In claim 1,
The even number of inverter circuits is composed of a plurality of pairs,
In the semiconductor integrated circuit device, the plurality of pairs of inverter circuits are configured such that the current driving capability is set in order from the first stage side.

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