JP3662881B2 - Thin film transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a structure of a thin film transistor (TFT) and a manufacturing method thereof. The thin film transistor manufactured by the present invention is formed on either an insulating substrate such as glass or a semiconductor substrate such as single crystal silicon.
[0002]
[Prior art]
Conventionally, a thin film transistor is formed by patterning a thin film semiconductor region (active layer) into an island shape, and then forming an insulating film as a gate insulating film by a CVD method or a sputtering method, and forming a gate electrode thereon.
[0003]
[Problems to be solved by the invention]
Insulating films formed by CVD or sputtering have poor step coverage (step coverage), and have adverse effects on reliability, yield, and characteristics. FIG. 3 shows a top view of a typical conventional TFT and a cross-sectional view taken along the lines AA ′ and BB ′ of the drawing. The TFT is formed on the substrate 31, and the thin film semiconductor region is located under the impurity region (source / drain region, here indicating N-type conductivity type) 33 and the gate electrode 37, and is a substantially intrinsic channel formation region. A gate insulating film 35 is provided so as to cover the semiconductor region. In the impurity region 33, a contact hole is opened through an interlayer insulator 39 and an electrode / wiring 38 is provided.
[0004]
As can be seen from the figure, the coverage of the end portion of the semiconductor region of the gate insulating film 35 is extremely poor, and typically only half the thickness of the flat portion is present. In general, it is significant when the island-like semiconductor region is thick. In particular, from the AA ′ cross section along the gate electrode, it can be seen that such a deterioration in the covering property adversely affects the TFT characteristics, reliability, and yield. That is, when attention is paid to the region 36 indicated by the dotted circle in the AA ′ cross-sectional view of FIG. 5, the electric field of the gate electrode 37 is concentratedly applied to the end portion of the thin film semiconductor region. That is, in this portion, the thickness of the gate insulating film is half that of the flat portion, so that the electric field strength is doubled.
[0005]
As a result, the gate insulating film in this region 36 is easily destroyed by applying a high voltage for a long time. If the signal applied to the gate electrode is positive, the semiconductor in this region 36 is also N-type, so that the gate electrode 37 and the impurity region 38 (especially the drain region) become conductive, causing a decrease in reliability. Become.
[0006]
Further, when the gate insulating film is destroyed, some kind of charge is trapped. For example, if a negative charge is trapped, the semiconductor in the region 36 is almost independent of the voltage applied to the gate electrode. Exhibits N-type, and the two impurity regions 38 are brought into conduction, deteriorating the characteristics. In addition, in order to use a TFT without causing the above-described deterioration, only half the voltage of an ideal case can be applied, and the performance cannot be fully utilized.
[0007]
In addition, the presence of such a weak portion in a part of the TFT means that the TFT is easily destroyed by charging or the like in the manufacturing process, which is a major factor in yield reduction. An object of the present invention is to solve such a problem.
[0008]
[Means for Solving the Invention]
In the present invention, the semiconductor in the electrically weak region is compensated by making it an intrinsic semiconductor having high resistance or the same conductivity type as that of the channel formation region. A typical structure of the present invention is shown in FIG. As shown in FIG. 1A, in the present invention, in the vicinity of the portion where the gate electrode 11 crosses at the end portion of the island-shaped semiconductor region, the portion that has been an impurity region (source, drain) in the conventional TFT is formed. A region 14 having the same conductivity type as the intrinsic region or the channel formation region was provided. That is, in the TFT of the present invention, a substantially intrinsic region or channel formation region other than the impurity region (source / drain) 13 doped with impurities in the island-shaped semiconductor region that is not covered with the gate electrode. There is a region 14 of the same conductivity type.
[0009]
FIG. 1B shows another example of the present invention, but the substantial structure is the same as FIG. 1A except that the shape of the island-shaped semiconductor region is different. In the figure, reference numeral 16 denotes an electrode connected to the source and drain.
[0010]
Thus, the effect of providing the intrinsic region 14 or the region having the same conductivity type as that of the channel formation region will be described with reference to FIG. FIG. 4A shows a structure and an equivalent circuit of a conventional TFT. In the figure, X and Y are portions where the gate electrode crosses the island-shaped semiconductor region, and the gate insulating film in this portion is thinner than the flat portion as described above. Therefore, as shown in the equivalent circuit, a parasitic TFT having a threshold value and a withstand voltage lower than those of the original TFT is formed.
[0011]
If an excessive voltage is applied to the gate, the parasitic TFT is destroyed before the original TFT is destroyed, and the parasitic TFT becomes a mere conductor and leaks between the source and drain or between the source and gate. The current increases.
[0012]
On the other hand, the present invention has a structure and an equivalent circuit as shown in FIG. In the present invention, the parasitic TFTs X, Y are formed as in the conventional case. However, in the present invention, a part of the island-like semiconductor region becomes an intrinsic semiconductor region, so that the resistance is high. This resistor R is inserted in series with the parasitic TFT, and the source and drain voltages are not directly applied to the parasitic TFT. It becomes a structure. In addition, when a region having the same conductivity type as that of the channel formation region is provided, the conductivity type is opposite to that of the source and drain, and thus a barrier equivalent to the resistance is formed by the PN junction.
[0013]
Therefore, even when an excessive voltage is applied to the gate electrode, the voltage is reduced by the resistance inserted in series with the source and drain of the parasitic resistance, and the parasitic TFT is not destroyed. As a result, the reduction in reliability, the yield, and the deterioration of characteristics, which are problems in the conventional TFT, are solved.
[0014]
A process for carrying out the present invention will be briefly described with reference to FIGS. First, the island-shaped semiconductor region 10 is formed on the substrate. Usually, this semiconductor region is substantially intrinsic, but may be weak N-type or P-type. (Figure 1 (C))
[0015]
Then, after forming a gate insulating film, a gate electrode 11 is provided as shown in FIG. Thereafter, impurities are implanted as indicated by 12 in FIG. As a result, as shown in FIG. 1F, the impurity region 13 and the region 14 sandwiched between the impurity region and the gate electrode are formed. The region 14 is preferably a region indicated by a dimension of 2 to 5 μm. The conductivity type of this region is the same as that of the island-shaped semiconductor. If the island-shaped semiconductor is intrinsic, this region 14 is also intrinsic, and the typical resistivity is 10 ⁶ Ωcm or more.
[0016]
FIG. 1G shows a state where the gate electrode of the TFT shown in FIG. 1F is removed. As is apparent from this figure, the conductivity types of the channel formation region 15 and the region 14 shown in FIG. 1 (F) are the same. Finally, an electrode 16 is formed on the source and drain to complete the TFT. (Fig. 1 (H))
[0017]
In the present invention, for example, when only one of N-channel type and P-channel type TFTs is formed on a substrate, the number of photolithography steps is increased by one, which is obtained by the present invention. Considering improvement in characteristics, reliability, and yield, there is no obstacle.
[0018]
Further, when the present invention is applied to a complementary circuit (CMOS circuit) in which N-channel and P-channel TFTs are mixed, the effect becomes clearer. In the CMOS circuit, the simplest manufacturing method is to introduce N-type or P-type impurities first on the entire surface of the substrate, and then mask the necessary portions to reverse the previously introduced impurities. Conductive impurities are introduced. This method is temporarily referred to as a first method. However, in this first method, for example, the N type region has a dose amount of 1 × 10 ¹⁵ cm ⁻² , while the P type region requires a dose amount of 5 × 10 ¹⁵ cm ⁻² , In some cases, the N-channel TFT and the P-channel TFT cannot be balanced in terms of threshold values.
[0019]
However, a reliable method is a method in which masking is first performed to introduce N-type or P-type impurities, and then masking is performed again to introduce impurities of a conductivity type opposite to the previous impurities. This method is referred to as a second method. In this case, since the concentrations of the N-type impurity and the P-type impurity can be set completely independently, ideal characteristics can be expected as a CMOS circuit. However, in this case, one photolithography process is added as compared with the first method.
[0020]
If the present invention is applied to both N-type and P-type TFTs in a CMOS circuit, N-type impurities and P-type impurities must be separately masked and introduced. Therefore, the second method of the above two methods is adopted. As described above, the second method has a complicated manufacturing process but has excellent characteristics. And since the effect of this invention is acquired in addition to the effect, the demerit of adding one photolithography process will be negated completely. In the following, an embodiment will be described in the case where the present invention is implemented particularly when a CMOS circuit is manufactured.
[0021]
【Example】
FIG. 2 shows a cross-sectional view of the manufacturing process of this embodiment. A silicon oxide base film 21 having a thickness of 200 nm was formed on a substrate (Corning 7059) 20 by sputtering. Furthermore, an amorphous silicon film having a thickness of 50 to 150 nm, for example, 150 nm was deposited by plasma CVD. Subsequently, a silicon oxide film having a thickness of 20 nm was deposited as a protective film by sputtering. Then, it was crystallized by annealing at 600 ° C. for 48 hours in a reducing atmosphere. The crystallization process may be a method using strong light such as a laser. Then, the obtained crystalline silicon film was patterned to form island-like silicon regions 22P and 22N.
[0022]
Next, a silicon oxide film 23 having a thickness of 100 nm is deposited as a gate insulating film by a sputtering method, and subsequently, a silicon film having a thickness of 600 to 800 nm, for example 600 nm (0.01 to 2% phosphorous) is formed by a low pressure CVD method. Deposited). It is desirable that the silicon oxide and silicon film forming steps be performed continuously. Then, the silicon film was patterned to form gate electrodes 24P and 24N. (Fig. 2 (A))
[0023]
Next, the semiconductor region 22P was masked with a photoresist 25N, and an impurity (phosphorus) was implanted into the silicon region 22N using the wiring 24N as a mask by plasma doping. As the material for the mask 25, metal materials such as chromium, titanium, titanium nitride, and aluminum, and metal nitride materials can also be used. The doping pattern has a shape as shown in FIG. As the doping gas, phosphine (PH ₃ ) was used, and the acceleration voltage was set to 60 to 90 kV, for example, 80 kV. The dose amount was 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 1 × 10 ¹⁵ cm ⁻² . As a result, an N-type impurity region 26N was formed. After the doping, the resist mask 25N was removed by an ashing (ashing) process in an oxygen atmosphere. Typical ashing conditions were 1 Torr and RF power 300W.
[0024]
Further, when activation is performed later by laser, the silicon oxide 23 on the silicon region 22N may be selectively removed by hydrofluoric acid before removing the resist mask. This is effective in preventing the surface from being uneven due to the reaction between the silicon oxide 23 and the silicon region 22N during laser irradiation. (Fig. 2 (B))
[0025]
Further, this time, the semiconductor region 22N is masked with the photoresist 25P, and an impurity (boron) is implanted into the silicon region 22P by the plasma doping method using the wiring 24P as a mask. Also in this case, the doping pattern has a shape as shown in FIG. Diborane (B ₂ H ₆ ) was used as a doping gas, and the acceleration voltage was set to 20 to 70 kV, for example, 65 kV. The dose amount was 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 1 × 10 ¹⁵ cm ⁻² . As a result, a P-type impurity region 26P was formed. After doping, the resist mask 25P was removed by an ashing process. (Fig. 2 (C))
[0026]
Thereafter, the impurities were activated by annealing at 600 ° C. for 48 hours in a reducing atmosphere. This step may be performed by laser annealing. In that case, a KrF excimer laser (wavelength 248 nm), a XeF excimer laser (wavelength 353 nm), a XeCl excimer laser (wavelength 308 nm), an ArF excimer laser (wavelength 193 nm) or the like is used as the laser, and the energy density of the laser is 200 ˜350 mJ / cm ² , for example, 250 mJ / cm ^2, and ² to 10 shots, for example, 2 shots may be irradiated at one place. You may heat a board | substrate to about 200-450 degreeC at the time of laser irradiation. Note that the optimum laser energy density changes when the substrate is heated.
[0027]
After the activation of the impurities, subsequently, a silicon oxide film 27 having a thickness of 300 to 1000 nm, for example 600 nm, is formed as an interlayer insulator by a plasma CVD method, a contact hole is formed in this, and a metal material such as titanium nitride is formed. Wirings 28P and 28N were formed of a multilayer film of aluminum. A CMOS semiconductor circuit was completed through the above steps. (Fig. 2 (D))
[0028]
【The invention's effect】
According to the present invention, it is possible to improve the yield of the TFT, enhance its reliability, and bring out the maximum characteristics. Moreover, in obtaining such a great effect, the merit of being able to be carried out without particularly large process change, investment, and technological development is great. Although the present invention has been described by taking the TFT on the insulating substrate as an example, it goes without saying that the present invention can also be applied to a TFT formed on a single crystal semiconductor substrate. Thus, the present invention is an industrially useful invention.
[Brief description of the drawings]
FIG. 1 shows a conceptual diagram of a structure and a manufacturing method of a TFT of the present invention.
FIG. 2 is a cross-sectional view illustrating a manufacturing process of a TFT of an example.
FIG. 3 shows a configuration example of a conventional TFT.
FIG. 4 illustrates electrical characteristics of the present invention and a conventional TFT.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Island-like semiconductor region 11 ... Gate electrode 12 ... Impurity introduction region 13 ... Impurity region (source, drain)
14... Region 15 in which no impurity is introduced 15... Channel forming region 16... Source electrode and drain electrode

Claims (2)

An island-shaped semiconductor region, a gate insulating film on the island-shaped semiconductor region, and a gate electrode on the gate insulating film and crossing the island-shaped semiconductor region,
The island-shaped semiconductor region is
A channel formation region located in a region traversed by the gate electrode, an impurity region forming a source or drain region,
A region not covered with the gate electrode, including one side end portion of the island-shaped semiconductor region on one side and a region surrounded by the channel formation region and the impurity region on the other side end portion. And a high resistance region having the same conductivity type as that of the channel forming region, the upper surface portion being in contact with the gate insulating film . An island-shaped semiconductor region, a gate insulating film on the island-shaped semiconductor region, and a gate electrode on the gate insulating film and crossing the island-shaped semiconductor region,
The island-shaped semiconductor region is
A channel formation region located in a region traversed by the gate electrode, an impurity region forming a source or drain region,
A region not covered with the gate electrode, including one side end portion of the island-shaped semiconductor region on one side and a region surrounded by the channel formation region and the impurity region on the other side end portion. A thin film transistor having a conductivity type region opposite to the source and drain regions so that the upper surface portion is in contact with the gate insulating film and forms a PN junction with the impurity region .

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