JP3685982B2 - Synchronous clock signal generator and ATM device using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a synchronous clock signal generator for generating a clock signal synchronized with a reference clock signal, and an ATM (Asynchronous Transfer Mode) apparatus using the same.
[0002]
[Prior art]
Conventionally, a synchronous clock signal generator for generating a synchronous clock signal synchronized with a reference clock signal has been used in various electronic devices including an ATM device such as a router device which is a device for connecting to an ATM network. .
[0003]
For example, in an ATM device, a synchronous clock signal generator is used when determining an ATM cell transmission rate to an ATM network. As a method for generating a synchronous clock signal, a method using a free-running clock signal in the ATM device is used. Alternatively, there is a method using hardware logic for synchronizing with a network clock signal.
[0004]
As another synchronous clock signal generator, there is a method of dividing a reference clock signal by a frequency dividing circuit.
[0005]
[Problems to be solved by the invention]
In the method using the free-running clock signal in the ATM device, an error from the network clock signal is accumulated over time regardless of the accuracy of the free-running clock signal, and data overrun or underrun called slip occurs. There was a problem of doing.
[0006]
In addition, in the method using hardware logic for synchronizing with the network clock signal, the setting range of the transmission rate is fixed, a high-precision PLL (Phase Locked Loop) circuit and complicated logic are required, which increases the cost. It was a factor.
[0007]
In addition, in the method using the frequency dividing circuit, only a clock signal having a specific frequency such as 1 / integer of the reference clock signal can be obtained, and if a gap occurs in the reference clock signal, the frequency of the obtained synchronous clock signal is shifted. There was a problem that occurred.
[0008]
Therefore, the ATM device using these synchronous clock signal generators has a problem that the operation becomes unstable or expensive.
[0009]
An object of the present invention is to provide a low-cost and high-accuracy synchronous clock signal generator that can generate a synchronous clock signal.
[0010]
Another object of the present invention is to provide an ATM device that is inexpensive and capable of stable operation.
[0011]
[Means for Solving the Problems]
According to the present invention, a first clock signal generating means for generating a first clock signal, a first clock signal counting means for counting the first clock signal, and the first clock signal in response to a reference clock signal. Storage means for storing the count value of one clock signal counting means, the difference between the count values stored in the storage means at the first and second times, the frequency of the first clock signal, and the reference clock Reference clock signal number calculating means for calculating the number of reference clock signals received between the first and second times based on the frequency of the signal;
Synchronous clock signal number calculating means for calculating the number of synchronous clock signals to be generated while the calculated reference clock signal number is generated;
Second clock signal generating means for generating a second clock signal;
Variable frequency dividing means for dividing the second clock signal and outputting a synchronous clock signal;
Second clock signal counting means for counting the synchronous clock signal;
Synchronous clock signal number difference calculating means for calculating a difference between the numbers of synchronous clock signals counted by the second clock signal counting means at the first and second times;
Controls the division ratio of the variable frequency dividing means so that the difference between the number of synchronous clock signals calculated by the synchronous clock signal number calculating means and the number of synchronous clock signals calculated by the synchronous clock signal number difference calculating means becomes small. And a control means for providing a synchronous clock signal generator.
[0012]
The reference clock signal number calculation means is configured to calculate the first, second, and second clocks based on the difference between the count values stored in the storage means, the frequency of the first clock signal, and the frequency of the reference clock signal. The number of reference clock signals received during the second time is calculated. The synchronous clock signal number calculating means calculates the number of synchronous clock signals to be generated while the calculated reference clock signal number is generated. The synchronous clock signal number difference calculating means calculates the number of synchronous clock signals counted by the second clock signal counting means at the first and second times. The control means divides the variable frequency dividing means so that the difference between the number of synchronous clock signals calculated by the synchronous clock signal number calculating means and the number of synchronous clock signals calculated by the synchronous clock signal number difference calculating means becomes small. Control the ratio.
[0013]
According to the present invention, the first clock signal generating means for generating the first clock signal, the first clock signal counting means for counting the first clock signal, and in response to the reference clock signal Storage means for storing the count value of the first clock counting means; second clock signal generating means for generating a second clock signal; and outputting a synchronous clock signal by dividing the second clock signal Variable frequency dividing means, second clock signal counting means for counting the synchronous clock signal output from the variable frequency dividing means, and control means for controlling the frequency division ratio of the variable frequency dividing means, The control means
The count value of the storage means at the first time t1 is Ct1, the count value of the first clock signal counting means is Vt1, the count value of the second clock signal counting means is Bt1, and the count value of the second clock signal counting means is the second time t2. The count value of the storage means is Ct2, the count value of the first clock signal count means is Vt2, the count value of the second clock signal count means is Bt2,
The number of reference clock signals generated between the first time t1 and the second time t2 is N, the number of synchronous clock signals to be generated between the first time t1 and the second time t2 is B,
The count value of the second clock signal counting means at the time of input of the reference clock signal just before the first time t1 is B0, and the second clock signal counting means at the time of input of the reference clock signal just before the second time t2. Let B1 be the count value of
B = ([frequency of synchronous clock signal] / [frequency of reference clock signal]) · N
B0 = Bt1- (Vt1-Ct1). [Frequency of synchronous clock signal] / [frequency of first clock signal]
B1 = Bt2- (Vt2-Ct2). [Frequency of synchronous clock signal] / [frequency of first clock signal]
BN = B1-B0
BN is obtained based on the following relational expression, and the division ratio of the variable frequency dividing means is controlled so that the value of (B−BN) becomes small.
[0014]
The control means controls the variable frequency dividing means so that the value of (B−BN) becomes small based on the above equations.
[0015]
Here, the variable frequency dividing means may be constituted by a baud rate generator.
[0016]
The reference clock signal may be a signal obtained from an ATM network.
[0017]
According to the present invention, there is provided an ATM device comprising the synchronous clock signal generator.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
A synchronous clock signal generator and an ATM device using the same according to embodiments of the present invention will be described below with reference to the accompanying drawings.
[0019]
FIG. 1 shows an example of an ATM device using a synchronous clock signal generator according to an embodiment of the present invention.
[0020]
In FIG. 1, an ATM device 100 which is a device used for ATM such as a router device is provided with a synchronous clock signal generator 101, an ATM cell transmission scheduler 107, and an ATM interface (ATM-PHY chip) 108. To the ATM network 109 outside the apparatus. The interface 108 extracts a network clock signal (frequency is 8 kHz in this embodiment) M as a reference clock signal from the signal supplied from the ATM network 109.
[0021]
The synchronous clock signal generator 101 counts a first clock signal (in this embodiment, an internal clock signal having a frequency of 1 MHz) K from a first clock signal generator (not shown). A counter 102 as a counting means and a capture as a storing means for capturing and storing the count value of the counter 102 each time a reference clock signal (network clock signal M obtained from the ATM network 109 in this embodiment) M is input. A second clock signal (in this embodiment, an internal clock signal having a frequency of 50 MHz) L from the circuit 104, the central processing unit (CPU) 104, and second clock signal generation means (not shown) is sent from the CPU 104. Baud rate generator 105 as variable frequency dividing means for dividing by a frequency dividing ratio according to a control signal, baud rate generator And a counter 106 as the second clock signal counting means for counting the synchronizing clock signal B outputted from the 05.
[0022]
The counter 102 is a timer counter that operates based on the internal clock signal K. When the network clock signal M is input, the count value V of the counter 102 at that time is stored in the capture circuit 103. The counter 102 continues counting operation thereafter.
[0023]
The CPU 104 sets a division ratio calculated from the ATM cell transmission rate (calculated based on equations (1) to (5) described later) in the baud rate generator 105, and divides the internal clock signal L by the division ratio. Then, the output of the synchronous clock signal B is started.
[0024]
The cell transmission scheduler 107 transmits ATM cells at a timing according to the synchronous clock signal B.
[0025]
The CPU 104 reads out the count value stored in the capture circuit 103 and the count value of the counter 106 at a predetermined cycle and stores them in a storage means (not shown). The number N of network clock signals generated during this period is calculated from the previous (first time) count value and the current (second time) count value stored in the capture circuit 103. The number B of synchronous clock signals to be generated while N network clock signals are generated is calculated. From the previous and current count values of the counter 106, the number of synchronous clocks BN within this period is obtained. Next, based on the difference between BN and B, the frequency division ratio of the baud rate generator 105 is controlled so that the difference becomes small.
[0026]
Here, the CPU 104 determines between the first and second times based on the difference between the count values stored in the capture 103 at the first and second times, the frequency of the internal clock signal K, and the frequency of the reference clock signal M. A reference clock signal number calculating means for calculating the number of reference clock signals to be received; a synchronous clock signal number calculating means for calculating the number of synchronous clock signals to be generated while the calculated reference clock signal number is generated; Synchronous clock signal number difference calculating means for calculating the difference in the number of synchronous clock signals counted by the counter 106 at the second time, the synchronous clock signal number calculated by the synchronous clock signal number calculating means, and the synchronous clock signal number difference Control for controlling the frequency division ratio of the baud rate generator 105 so that the difference from the number of synchronous clock signals calculated by the calculation means becomes small. Constitute the stage.
[0027]
The first internal clock signal K and the second internal clock signal L may be obtained from a common clock signal generation source. For example, the clock signal generation circuit that generates the second internal clock signal, and the frequency division circuit that divides the second internal clock signal to generate the first internal clock signal. Various changes are possible. In this case, the clock signal generating circuit constitutes a second clock signal generating means, and the clock signal generating circuit and the frequency dividing circuit constitute a first clock signal generating means.
[0028]
FIG. 2 is a timing chart for explaining the operation of the synchronous clock signal generator according to the present embodiment.
[0029]
Hereinafter, the operation of the present embodiment will be described in detail with reference to FIGS. It should be noted that arithmetic processing of formulas (1) to (5) described later and generation of a control signal based on the arithmetic processing are performed by the CPU 104.
[0030]
First, the measurement of the reference clock signal M will be described. To measure the reference clock signal M (8 kHz), the first internal clock signal K (1 MHz) is used. The counter 102 counts the internal clock signal K, and the capture circuit 103 stores the count value of the counter 102 in the capture circuit 103 as a capture value in response to the input of the reference clock signal M. .
[0031]
If the capture values of the capture circuit 103 at the first time t1 and the second time t2 are Ct1 and Ct2, the number N (positive integer) of reference clock signals (network clock signals) input between the times t1 and t2 is It is obtained by the following formula (1). Here, K is the frequency (1 MHz) of the first internal clock signal, and M is the frequency (8 kHz) of the reference clock signal.
[0032]
N≈ (Ct1-Ct2) / (K / M) = (Ct1-Ct2) / 125 (1)
However, when a fraction occurs on the right side of Equation (1), the nearest integer is N. As a result, even when a gap occurs in the reference clock signal, an appropriate N can be obtained, and a shift in the frequency of the synchronous clock signal can be prevented.
[0033]
Next, the generation of the synchronous clock signal and the synchronous operation with the reference clock signal will be described. The capture value Ct1 of the capture circuit 103, the count value Vt1 of the counter 102, and the count value Bt1 of the counter 106 at a certain time t1 are stored in storage means (not shown). Next, the capture value Ct2 of the capture circuit 103 at time t2, the count value Vt2 of the counter 102, and the count value Bt2 of the counter 106 are stored in the storage means.
[0034]
From the above equation (1), the reference clock number N between times t1 and t2 can be obtained from the capture values Ct1 and Ct2. In the example of FIG. 2, N = 4.
[0035]
On the other hand, the number B of synchronous clock signals B to be generated while N reference clock signals M are generated can be obtained by the following equation (2).
[0036]
B = ([frequency of synchronous clock signal B] / [frequency of reference clock signal M]) · N (2)
Further, from the count value of the counter 106, the count value B0 of the counter 106 at the time of input of the reference clock signal immediately before the time t1 (the zero point in FIG. 2) is expressed by the following equation (3). Similarly, the count value B1 of the counter 106 when the reference clock signal M is input immediately before time t2 (point 4 in FIG. 2) is obtained by the following equation (4).
B0 = Bt1- (Vt1-Ct1). [Frequency of synchronous clock signal B] / [frequency of internal clock signal K] (3)
B1 = Bt2- (Vt2-Ct2). [Frequency of synchronous clock signal B] / [frequency of internal clock signal K] (4)
The number of synchronized clock signals BN between time t1 and time t2 is obtained by the following equation (5).
[0037]
BN = B1-B0 (5)
The difference between the synchronous clock signal and the reference clock signal can be calculated from the difference between the synchronous clock number BN obtained from the equation (5) and the synchronous clock number B obtained from the equation (2). The CPU 104 outputs a control signal for controlling the frequency division ratio so that the difference becomes small. In the baud rate generator 105, the frequency division ratio changes in response to the control signal, and the synchronous clock signal B is corrected. As described above, the division ratio R is dynamically adjusted by the baud rate generator 105, and the synchronous clock signal B is synchronized with the reference clock signal M.
[0038]
As described above, according to the synchronous clock signal generation device of the present embodiment, the CPU 104 is used to obtain the synchronous clock signal, and the frequency division ratio of the baud rate generator 105 is controlled by software. That is, a clock signal generated using the baud rate generator 105 is compared with a reference clock signal (network clock signal), and a difference generated by an error or fluctuation of the clock signal is adjusted to a frequency dividing ratio of the baud rate generator 105. Thus, a synchronous clock signal that follows the reference clock signal is obtained.
[0039]
Therefore, the cost for generating a clock signal synchronized with the reference clock signal can be reduced, and a highly accurate synchronous clock signal can be generated. Further, it is possible to arbitrarily set the transmission rate without causing slip, and it is possible to provide an inexpensive and stable ATM device.
[0040]
【The invention's effect】
As described above, according to the synchronous clock signal generator of the present invention, it is possible to generate an inexpensive and highly accurate synchronous clock signal.
[0041]
Further, the ATM device of the present invention is inexpensive and can operate stably.
[Brief description of the drawings]
FIG. 1 is a block diagram of an ATM device using a synchronous clock signal generator according to an embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of the synchronous clock signal generator according to the embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100 ... ATM apparatus 101 ... Synchronous clock signal generator 102 ... Counter 103 as 1st clock signal counting means ... Capture circuit 104 as memory | storage means ... CPU which comprises control means
105 ... Baud rate generator 106 as variable frequency dividing means ... Counter 107 as second clock signal counting means ... Cell transmission scheduler 108 ... ATM-PHY chip 109 as interface ... ATM network

Claims (5)

A first clock signal generating means for generating a first clock signal; a first clock signal counting means for counting the first clock signal; and the first clock signal counting means in response to a reference clock signal. Based on the difference between the count values stored in the storage means at the first and second times, the frequency of the first clock signal, and the frequency of the reference clock signal. , A reference clock signal number calculating means for calculating the reference clock signal number received between the first and second times;
Synchronous clock signal number calculating means for calculating the number of synchronous clock signals to be generated while the calculated reference clock signal number is generated;
Second clock signal generating means for generating a second clock signal;
Variable frequency dividing means for dividing the second clock signal and outputting a synchronous clock signal;
Second clock signal counting means for counting the synchronous clock signal;
Synchronous clock signal number difference calculating means for calculating a difference between the numbers of synchronous clock signals counted by the second clock signal counting means at the first and second times;
Controls the frequency division ratio of the variable frequency dividing means so that the difference between the number of synchronous clock signals calculated by the synchronous clock signal number calculating means and the number of synchronous clock signals calculated by the synchronous clock signal number difference calculating means becomes small. And a control means for controlling the synchronous clock signal. A first clock signal generating means for generating a first clock signal; a first clock signal counting means for counting the first clock signal; and the first clock signal counting means in response to a reference clock signal. Storage means for storing the count value, second clock signal generating means for generating a second clock signal, variable frequency dividing means for dividing the second clock signal and outputting a synchronous clock signal, A second clock signal counting unit configured to count the synchronous clock signal output from the variable frequency dividing unit; and a control unit configured to control a frequency dividing ratio of the variable frequency dividing unit.
The count value of the storage means at the first time t1 is Ct1, the count value of the first clock signal counting means is Vt1, the count value of the second clock signal counting means is Bt1, and the count value of the second clock signal counting means is the second time t2. The count value of the storage means is Ct2, the count value of the first clock signal count means is Vt2, the count value of the second clock signal count means is Bt2,
The number of reference clock signals generated between the first time t1 and the second time t2 is N, the number of synchronous clock signals to be generated between the first time t1 and the second time t2 is B,
The count value of the second clock signal counting means at the time of input of the reference clock signal just before the first time t1 is B0, and the second clock signal counting means at the time of input of the reference clock signal just before the second time t2. Let B1 be the count value of
B = ([frequency of synchronous clock signal] / [frequency of reference clock signal]) · N
B0 = Bt1- (Vt1-Ct1). [Frequency of synchronous clock signal] / [frequency of first clock signal]
B1 = Bt2- (Vt2-Ct2). [Frequency of synchronous clock signal] / [frequency of first clock signal]
BN = B1-B0
BN is obtained based on the following relational expression, and the division ratio of the variable frequency dividing means is controlled so that the value of (B−BN) becomes small. 3. A synchronous clock signal generator according to claim 1, wherein said variable frequency dividing means is constituted by a baud rate generator. 4. The synchronous clock signal generator according to claim 1, wherein the reference clock signal is a signal obtained from an ATM network. An ATM device comprising the synchronous clock signal generator according to any one of claims 1 to 4.

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