JP3687653B2 - Stabilized power circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a stabilized power supply circuit, and more particularly to a technique for performing phase compensation.
[0002]
[Prior art]
Examples of the stabilized power supply circuit that performs phase compensation include those described in Patent Document 1 and Patent Document 2.
[0003]
[Patent Document 1]
JP 2000-47738 A (FIG. 5 and paragraph 0002)
[Patent Document 2]
JP 2001-195138 A (FIGS. 5 to 8)
[0004]
A conventional stabilized power supply circuit (hereinafter referred to as a series regulator) is shown in FIG.
The conventional series regulator 50 includes a voltage output unit 51, an output voltage detection unit 52, an error amplification unit 53, and a reference voltage unit 54.
[0005]
The reference voltage unit 54 is connected to the error amplification unit 53 in order to supply a reference voltage to the error amplification unit 53. The error amplifying unit 53 supplies a control signal to the voltage output unit 51 such that the error voltage between the output voltage Vout detected by the output voltage detecting unit 52 and the reference voltage supplied from the reference voltage unit 54 becomes zero. It is. The error amplifying unit 53 includes a differential amplifier 55, an amplifier 56, and a phase compensation circuit 57.
[0006]
The phase compensation circuit 57 is a circuit that performs phase compensation to stabilize the operation of the series regulator 50, and is configured by a circuit in which a resistor R51 and a capacitor C52 are connected in series.
[0007]
In such a conventional series regulator 50, the voltage output unit 51 generates the output voltage Vout from the supply voltage Vin supplied from the input terminal Pin based on the control signal supplied from the error amplifier 53, and outputs the output terminal Pout. Output to.
[0008]
The output voltage detection unit 52 detects the output voltage Vout output from the voltage output unit 51. The differential amplifier 55 amplifies an error voltage between the detected output voltage Vout and the reference voltage supplied from the reference voltage unit 54, and the amplifier 56 further amplifies the amplified error voltage to generate a control signal. To the voltage output unit 51.
[0009]
In this manner, in the series regulator 50, the output voltage Vout is stabilized by feeding back the control signal corresponding to the error voltage to the voltage output unit 51.
An output capacitor C51 is generally connected to the output terminal Pout of the series regulator 50. This capacitor C51 is for improving the transient response when the load changes suddenly.
[0010]
Some series regulators 50 are formed of a semiconductor integrated circuit (IC). In this case, the capacitor C51 is externally attached to the integrated series regulator 50.
[0011]
Conventionally, an aluminum electrolytic capacitor has been used as the capacitor C51. However, multilayer ceramic capacitors having a smaller equivalent series resistance (ESR) than aluminum electrolytic capacitors are being used in response to demands for ripple voltage reduction, high frequency characteristics, and mounting area reduction.
[0012]
[Problems to be solved by the invention]
When an aluminum electric field capacitor is used as the capacitor C51, since the ESR is large to some extent, the ESR acts as a feedback resistor, and a phase margin can be secured. On the other hand, since the ESR is small and the phase return is small in the multilayer ceramic capacitor, it is difficult to ensure the phase margin. This phase margin is obtained by adding 360 ° to the phase at the frequency at which the voltage gain is 1 in the frequency characteristics of the voltage gain and phase of the inverting amplifier (negative feedback) shown in FIGS. 10 (a) and 10 (b). Value (φ11).
[0013]
This operation is shown in FIG.
10A shows the frequency characteristic of the voltage gain G, and FIG. 10B shows the frequency characteristic of the phase angle φ.
As shown in FIG. 10A, the mirror capacitance and current I formed by the capacitor C52 and the amplifier 56 of the phase compensation circuit 57.₁Thus, the cutoff frequency f1 is determined. If the frequency f is equal to or lower than the cut-off frequency f1 (f <f1), the voltage gain G is equal to or higher than 1.
[0014]
When the frequency f increases and becomes a frequency band of f1 <f <f11, the voltage gain G attenuates. Here, the resistor R51 is a feedback resistor inserted in order to eliminate the phase lag when the voltage gain G is near 1, and the phase lag decreases near the point A shown in FIG.
[0015]
However, when the frequency f further increases and f11 <f, the voltage gain G increases due to the influence of the resistor R51. The voltage gain G exceeds the voltage gain 1. At this time, if there is a phase lag of the error voltage of the internal elements such as the differential amplifier 55, the phase margin φ11 becomes small at f = f12 as shown in FIG.
If the phase margin is small, the operation of the series regulator 50 becomes unstable and oscillation or the like may occur.
[0016]
The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a stabilized power supply circuit that can operate stably.
[0017]
[Means for Solving the Problems]
  In order to achieve the above object, a stabilized power supply circuit according to an aspect of the present invention includes:
  A voltage output unit that is supplied with a DC voltage and outputs a DC output voltage based on a control signal;
  A differential amplifier that generates an error voltage between an output voltage output from the voltage output unit and a reference voltage;
An amplifier that amplifies the error voltage and outputs the amplified error voltage to the voltage output unit as the control signal;
A resistor and a first capacitor are connected in series between the error voltage input terminal and the control signal output terminal of the amplifier, and the control signal is fed back to the error voltage for phase compensation. To the frequency characteristics of the control signal,The first cut-off frequency is set in a frequency band in which the gain when amplifying the error voltage exceeds 1.A first phase compensation circuit that sets and holds a phase margin at a frequency higher than the first cutoff frequency in a range of 30 ° to 90 °;
A second capacitor connected in parallel to the resistor of the first phase compensation circuit; and the frequency characteristic of the control signal in the frequency characteristicThe second cutoff frequency is set to a frequency band higher than the first cutoff frequency and having a gain of 1 or less.Set,Higher than the second cutoff frequencyA second phase compensation circuit for reducing the gain at less than 1;It is characterized by comprising.
  According to such a configuration, the stabilized power supply circuit operates stably.
[0020]
  still,The voltage output unit includes a first main electrode, a second main electrode, a first control electrode for controlling a conduction state between the first main electrode and the second main electrode, and the amplification.VesselThe first control electrode is connected to a terminal that outputs the control signal, the first main electrode is connected to a terminal to which the DC voltage is supplied, and the second main electrode is connected to a terminal that outputs the output voltage. Constituted by a first transistor to which a main electrode is connected;
  Said amplificationThe vessel is in frontA constant current circuit connected between the first main electrode and the first control electrode, a third main electrode, a fourth main electrode, the third main electrode, and the fourth main electrode A second control electrode for controlling a conduction state between the second control electrode and the second control electrodeConfigure a terminal to input the error voltageThe third main electrode is connected to the output terminal of the differential amplifier.Configure a terminal to output the control signalFormed by a second transistor connected to the first control electrode, the fourth main electrode being grounded.May be.
  In this case, the first transistor may be any one of an NPN bipolar transistor, a PNP bipolar transistor, an N-channel field effect transistor, or a P-channel field effect transistor. The second transistor may be any one of an NPN bipolar transistor, a PNP bipolar transistor, an N-channel field effect transistor, or a P-channel field effect transistor.
[0021]
  The voltage output unit includes a first main electrode, a second main electrode, and a first control electrode for controlling a conduction state between the first main electrode and the second main electrode. And a plurality of stages of transistors connected in a Darlington connection.VesselThe first control electrode of the first stage transistor of the plurality of stages of transistors is connected to the terminal that outputs the control signal, and the terminal of the last stage of the plurality of transistors is connected to the terminal to which the DC voltage is supplied. And the second main electrode of the final stage transistor may be connected to a terminal from which the output voltage is output.
[0022]
  or,The voltage output unit includes a first main electrode connected to a terminal to which the DC voltage is supplied, a second main electrode connected to a terminal to which the output voltage is output, and the first and second main electrodes. A first control electrode for controlling a conduction state between the electrodes,
The amplifier is
  A constant current circuit connected between the first main electrode and the first control electrode;
  The third main electrode, the fourth main electrode, the third main electrode, and the second control electrode for controlling the conduction state between the fourth main electrode, and a plurality of stages connected in Darlington connection By transistor andFormed,
  The second control electrode of the first stage transistor among the plurality of stages of transistors isConfigure a terminal to input the error voltageA third main electrode of the last stage transistor of the plurality of stages is connected to the output terminal of the differential amplifier.Configure a terminal to output the control signalThe fourth main electrode of the final stage transistor connected to the first control electrode may be grounded.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a stabilized power supply circuit according to an embodiment of the present invention will be described with reference to the drawings.
In this embodiment, the stabilized power supply circuit is described as a series regulator.
[0024]
[First Embodiment]
FIG. 1 is a configuration diagram showing a series regulator according to the first embodiment of the present invention.
The series regulator 1 according to the present embodiment includes a voltage output unit 11, an output voltage detection unit 12, an error amplification unit 13, and a reference voltage unit 14.
The voltage output unit 11 generates the output voltage Vout from the supply voltage Vin supplied from the input terminal Pin based on the control signal supplied from the error amplification unit 13, and outputs the output voltage Vout to the output terminal Pout. . The voltage output unit 11 includes, for example, an NPN bipolar transistor Q1.
[0025]
A capacitor C1 is connected between the output terminal Pout and the ground to improve the transient response when the load suddenly changes.
The output voltage detection unit 12 detects an output voltage and includes resistors R1 and R2. The resistors R1 and R2 are connected in series between the output terminal Pout and the ground to form a voltage dividing circuit.
[0026]
The reference voltage unit 14 is connected to the error amplification unit 13 and supplies the reference voltage Vref to the error amplification unit 13.
The error amplifying unit 13 amplifies the error voltage between the detection voltage supplied from the output voltage detection unit 12 and the reference voltage Vref of the reference voltage unit 14, and outputs the amplified error voltage to the transistor Q1 as a control signal. It is. The error amplifier 13 includes a differential amplifier 21, a constant current circuit 22, an amplifier 23, and a phase compensation circuit 24. The differential amplifier 21 differentially amplifies an error voltage between the detection voltage supplied from the output voltage detection unit 12 and the reference voltage Vref supplied from the reference voltage unit 14, and includes a constant current circuit 25 and a transistor Q3. To Q6.
[0027]
The constant current circuit 25 is a circuit that supplies a constant current to the transistors Q3 to Q6, and is connected to the input terminal Pin.
Transistors Q3 and Q4 are PNP bipolar transistors, and transistors Q5 and Q6 are NPN bipolar transistors. Transistors Q3 to Q6 are transistors for differential amplification, and transistors Q5 and Q6 constitute a current mirror circuit.
[0028]
The emitter of the transistor Q3 and the emitter of the transistor Q4 are connected to the constant current circuit 25. The base of the transistor Q3 is connected to the reference voltage unit 14, and the base of the transistor Q4 is connected to a connection point between the resistor R1 and the resistor R2.
[0029]
The collector of the transistor Q5 is connected to the collector of the transistor Q3, and the emitter is grounded. The collector of the transistor Q6 is connected to the collector of the transistor Q4, and the emitter is grounded.
The bases of the transistors Q5 and Q6 are both connected to the collector of the transistor Q6. Note that the current mirror circuit including the transistors Q5 and Q6 has a relatively large mirror capacitance in the error amplifying unit 13.
[0030]
On the other hand, the constant current circuit 22 outputs a constant current to the transistor Q1, and is connected between the collector and base of the transistor Q1.
The amplifier 23 is a circuit that controls the amount of current supplied to the base of the transistor Q 1 based on the output signal output from the differential amplifier 21. The amplifier 23 is composed of, for example, an NPN bipolar transistor Q2. The base of the transistor Q2 is connected to the collector of the transistor Q5. The collector of the transistor Q2 is connected to the base of the transistor Q1, and the emitter of the transistor Q2 is grounded.
[0031]
The phase compensation circuit 24 is a circuit that performs phase compensation of the series regulator 1. The phase compensation circuit 24 includes a resistor R3 and capacitors C2 and C3. The capacitor C2 and the resistor R3 are connected in series. This series capacitor C2 and resistor R3 are connected between the collector and base of the transistor Q2. The capacitor C3 is connected in parallel to both ends of the resistor R3.
[0032]
The capacitor C2 and the resistor R3 connected in series are circuits for ensuring a phase margin in the unity gain (voltage gain 1). The capacitor C3 is a capacitor for performing phase compensation corresponding to the operation delay of the internal elements of the series regulator 1 in a frequency band equal to or higher than the unity gain frequency. The capacitance value of the capacitor C3 is set so that the phase compensation by the capacitor C3 is performed from a lower frequency band than the band where the influence of the operation delay of the internal elements of the series regulator 1 occurs.
[0033]
Next, the operation of the series regulator 1 according to this embodiment will be described.
The transistor Q1 outputs an output voltage Vout based on the base current supplied to the base from the supply voltage Vin supplied from the input terminal Pin.
The output voltage detector 12 divides the output voltage Vout and supplies the divided voltage to the differential amplifier 21.
[0034]
The differential amplifier 21 amplifies the error voltage between the divided voltage supplied from the output voltage detector 12 and the reference voltage Vref supplied from the reference voltage unit 14, and supplies the amplified error voltage to the base of the transistor Q2. . A base current corresponding to the amplified error voltage flows through the base of the transistor Q2.
[0035]
When the output voltage Vout decreases and the divided voltage supplied from the output voltage detection unit 12 becomes lower than the reference voltage Vref of the reference voltage unit 14, the base current flowing through the base of the transistor Q2 decreases. When the base current of the transistor Q2 decreases, the collector current of the transistor Q2 decreases and the base current of the transistor Q1 increases. For this reason, the equivalent resistance of the transistor Q1 is reduced and the collector current of the transistor Q1 is increased, so that the output voltage Vout is increased.
[0036]
On the other hand, when the output voltage Vout rises and the divided voltage supplied from the output voltage detection unit 12 becomes higher than the reference voltage Vref of the reference voltage unit 14, the base current of the transistor Q2 increases and the collector current increases. For this reason, the equivalent resistance of the transistor Q1 increases, and the collector current of the transistor Q1 decreases, so that the output voltage Vout decreases.
[0037]
In this way, the series regulator 1 that supplies the control signal obtained by inverting and amplifying the error voltage to the transistor Q1 stabilizes the output voltage Vout.
Next, the phase compensation operation of the series regulator 1 will be described with reference to FIG.
2A shows the frequency characteristic of the voltage gain G, and FIG. 2B shows the frequency characteristic of the phase angle φ.
[0038]
The frequency characteristic of the error amplifying unit 13 is a first cut determined by the capacitor C2, the mirror capacitance formed by the transistor Q2, and the current of the constant current circuit 22 in a frequency band where the voltage gain exceeds 1. It has an off frequency f1 and a phase margin near unity gain is secured.
[0039]
Further, the frequency characteristics of the error amplifying unit 13 include a mirror capacitance and a constant capacitance formed by the resistor R3, the capacitor C3, the capacitor C2, and the transistor Q2 in a frequency band higher than the unity gain frequency and in a frequency band in which the voltage gain is less than 1. It has a second cutoff frequency determined by the current of the current circuit 22.
[0040]
As shown in FIG. 2A, the voltage gain G is constant when the frequency f is f <f0. When the frequency f increases and f0 ≦ f <f1, the voltage gain G decreases as shown in FIG. This is an influence of the cut-off frequency f0 determined by the transistor Q1 and the capacitor C1. A straight line p shown in FIGS. 2A and 2B shows frequency characteristics determined by the impedance of the load connected to the capacitor C1.
[0041]
When the frequency f is f1 ≦ f <f3, the voltage gain G is determined by the cutoff frequency f1 determined by the capacitance of the capacitor C2, the current flowing through the constant current circuit 22 and the mirror capacitance formed by the transistor Q2. Further decrease.
In the vicinity of the unity gain frequency f2, as shown in FIG. 2 (b), the phase delay is reduced by the effect of the resistor R3, and the phase margin is ensured from 30 ° to 90 °. As described above, the phase margin is a value obtained by adding 360 ° to the phase at the frequency at which the voltage gain becomes 1 in the frequency characteristics of the voltage gain and phase of the inverting amplifier (negative feedback) shown in FIG. Say.
[0042]
When the frequency f becomes f3 ≦ f <f4, the voltage gain G increases again as shown in FIG. This is due to the action of the capacitor C2 and the resistor R3.
When the frequency f becomes f4 ≦ f, the voltage gain G decreases as shown in FIG. This is because the effect of the resistor R3 is suppressed by the capacitor C3. In addition, the voltage gain G is given by f> f3 due to the influence of the cutoff frequency determined by the capacitance of the capacitors C2 and C3 that are equivalently connected in series, the mirror capacitance of the transistor Q2, and the current of the constant current circuit 22. Becomes less than 1. Therefore, oscillation does not occur and operation is stabilized.
[0043]
As described above, according to the present embodiment, the frequency characteristics of the error amplifying unit 13 are the cutoff frequency f1 determined by the mirror capacitance formed by the capacitor C2 and the transistor Q2 and the current of the constant current circuit 22. , A mirror capacitance formed by the resistor R3, the capacitor C3, the capacitor C2, and the transistor Q2 and a cutoff frequency determined by the current of the constant current circuit 22. Thereby, a phase margin is secured at the unity gain frequency f2. In addition, in the higher frequency band than the unity gain frequency f2, phase compensation corresponding to the operation delay due to the internal element is performed, so that the operation can be stabilized even when the ESR of the output capacitor C1 is low and the phase return is small.
[0044]
Further, since it is possible to take measures against the phase delay of the IC internal elements, it is possible to adjust the phase compensation variation of the series regulator 1 due to the process variation.
Further, since the phase margin can be set only by a linear element of a capacitor and a resistor, the phase margin can be easily set.
In addition, the influence of the transition frequency (frequency at which the current amplification degree becomes 1) of the element can be reduced.
[0045]
[Second Embodiment]
FIG. 3 is a configuration diagram of a series regulator according to the second embodiment of the present invention. Elements common to those in FIG. 1 are denoted by common reference numerals.
[0046]
In the series regulator 1 of the first embodiment described above, the voltage output unit 11 is configured by the NPN bipolar transistor Q1, and the amplifier 23 is configured by the NPN bipolar transistor Q2. These transistors Q1 or Q2 can be changed to PNP type transistors.
[0047]
In the series regulator 2 of FIG. 3, the voltage output unit 11 is constituted by a transistor Q7 which is a PNP bipolar transistor. The amplifier 23 of the series regulator 2 in FIG. 3 includes a transistor Q8 which is a PNP bipolar transistor. Other configurations of the series regulator 2 are the same as those in FIG. The collector of the transistor Q7 is connected to the output terminal Pout, and the emitter of the transistor Q7 is connected to the input terminal Pin. The base of transistor Q7 is connected to the emitter of transistor Q8. The base of the transistor Q8 is connected to the collector of the transistor Q5. The collector of the transistor Q8 is grounded. A phase compensation circuit 24 is connected between the emitter and base of the transistor Q8.
[0048]
Next, the operation of the series regulator 2 will be described.
The transistor Q7 outputs an output voltage Vout based on the base current supplied to the base from the collector. The output voltage detector 12 divides the output voltage Vout and supplies the divided voltage to the differential amplifier 21. The differential amplifier 21 amplifies the error voltage between the divided voltage supplied from the output voltage detection unit 12 and the reference voltage Vref supplied from the reference voltage unit 14, and supplies the amplified error voltage to the base of the transistor Q8. . A base current corresponding to the amplified error voltage flows through the base of the transistor Q8.
[0049]
When the output voltage Vout decreases and the divided voltage supplied from the output voltage detection unit 12 becomes lower than the reference voltage Vref of the reference voltage unit 14, the base current flowing through the base of the transistor Q8 increases. When the base current of the transistor Q8 increases, the emitter current of the transistor Q8 increases and the base current of the transistor Q7 increases. For this reason, the equivalent resistance of the transistor Q7 is reduced and the collector current of the transistor Q7 is increased, so that the output voltage Vout is increased.
[0050]
On the other hand, when the output voltage Vout increases and the divided voltage supplied from the output voltage detection unit 12 becomes higher than the reference voltage Vref of the reference voltage unit 14, the base current of the transistor Q8 decreases and the emitter current of the transistor Q8 decreases. Decreases. For this reason, the equivalent resistance of the transistor Q7 increases, and the collector current of the transistor Q7 decreases, so the output voltage Vout decreases.
[0051]
As described above, in the series regulator 2 including the transistors Q7 and Q8, the transistors Q7 and Q8 operate in the same manner as the transistors Q1 and Q2 of the first embodiment. The phase compensation circuit 24 performs phase compensation of the control signal as in the first embodiment. Therefore, the series regulator 2 has the same effects as the series regulator 1 of the first embodiment.
[0052]
[Third Embodiment]
FIG. 4 is a configuration diagram of a series regulator according to the third embodiment of the present invention. Elements common to those in FIG. 1 are denoted by common reference numerals.
[0053]
In the series regulator 1 of the first embodiment described above, the voltage output unit 11 is configured by the NPN bipolar transistor Q1, and the amplifier 23 is configured by the NPN bipolar transistor Q2. These transistors Q1 and Q2 and the transistors Q3 to Q6 in the differential amplifier 21 can be changed to field effect transistors.
[0054]
In the series regulator 3 of FIG. 4, the voltage output unit 11 includes a transistor Q9 that is an N-channel field effect transistor. The amplifier 23 of the series regulator 3 includes a transistor Q10 that is an N-channel field effect transistor. The differential amplifier 21 of the series regulator 3 includes transistors Q11 and Q12 that are P-channel field effect transistors and transistors Q13 and Q14 that are N-channel field effect transistors. Other configurations of the series regulator 3 are the same as those in FIG.
[0055]
The source that is the second main electrode of the transistor Q9 is connected to the output terminal Pout, and the drain that is the first main electrode of the transistor Q9 is connected to the input terminal Pin. The gate of the transistor Q9, which is the first control electrode, is connected to the drain, which is the third main electrode of the transistor Q10. The gate of the transistor Q10 as the second control electrode is connected to the drain of the transistor Q13 in the differential amplifier 21. The source of the transistor Q10 that is the fourth main electrode is grounded. A phase compensation circuit 24 is connected between the drain and gate of the transistor Q10.
[0056]
The source of the transistor Q11 and the source of the transistor Q12 of the differential amplifier 21 are connected to the constant current circuit 25. The gate of the transistor Q11 is connected to the reference voltage unit 14, and the gate of the transistor Q12 is connected to a connection point between the resistor R1 and the resistor R2.
[0057]
The drain of the transistor Q13 is connected to the drain of the transistor Q11, and the source of the transistor Q13 is grounded. The drain of the transistor Q14 is connected to the drain of the transistor 12, and the source of the transistor Q14 is grounded.
[0058]
The gates of the transistors Q13 and Q14 are both connected to the drain of the transistor Q12.
Next, the operation of the series regulator 3 will be described.
The transistor Q9 outputs an output voltage Vout based on the voltage supplied to the gate from the source. The output voltage detector 12 divides the output voltage Vout and supplies the divided voltage to the differential amplifier 21. The differential amplifier 21 amplifies the error voltage between the divided voltage supplied from the output voltage detection unit 12 and the reference voltage Vref supplied from the reference voltage unit 14, and applies the amplified error voltage to the gate of the transistor Q10.
[0059]
When the output voltage Vout decreases and the divided voltage supplied from the output voltage detector 12 becomes lower than the reference voltage Vref of the reference voltage unit 14, the gate voltage of the transistor Q10 decreases. As a result, the gate-source voltage of the transistor Q10 decreases, and the drain current of the transistor Q10 decreases. Therefore, the gate voltage of the transistor Q9 becomes high. For this reason, the equivalent resistance of the transistor Q9 decreases, the current flowing through the transistor Q9 increases, and the output voltage Vout increases.
On the other hand, when the output voltage Vout increases and the divided voltage supplied from the output voltage detection unit 12 becomes higher than the reference voltage Vref of the reference voltage unit 14, the gate voltage of the transistor Q10 increases and the drain current of the transistor Q10 increases. Will increase. Therefore, the gate voltage of transistor Q9 decreases. For this reason, the equivalent resistance of the transistor Q9 increases, and the current flowing through the transistor Q9 decreases, so the output voltage Vout decreases.
[0060]
Thus, in the series regulator 3 including the field effect transistors Q9 and Q10, the transistors Q9 and Q10 function similarly to the transistors Q1 and Q2 of the first embodiment. The phase compensation circuit 24 performs phase compensation of the control signal as in the first embodiment. Therefore, the same effects as those of the series regulator 1 of the first embodiment are obtained. Since each of the transistors Q9 to Q14 is a voltage control type, the base current in the bipolar transistor can be reduced, and low power consumption is possible.
[0061]
[Fourth Embodiment]
FIG. 5 is a configuration diagram of a series regulator according to the fourth embodiment of the present invention. Elements common to those in FIG. 4 are denoted by common reference numerals.
[0062]
In the series regulator 3 of the third embodiment described above, the voltage output unit 11 is composed of an N-channel field effect transistor Q9, and the amplifier 23 is composed of an N-channel field effect transistor Q10. These transistors Q9 and Q10 can be changed to P-channel field effect transistors.
[0063]
In the series regulator 4 of FIG. 5, the voltage output unit 11 includes a transistor Q15 that is a P-channel field effect transistor. The amplifier 23 of the series regulator 4 is composed of a transistor Q16 which is a P-channel field effect transistor. Other configurations of the series regulator 4 are the same as those of the series regulator 3.
[0064]
The source as the first main electrode of the transistor Q15 is connected to the input terminal Pin, and the drain as the second main electrode of the transistor Q15 is connected to the output terminal Pout. The gate of the transistor Q15 that is the first control electrode is connected to the source that is the third main electrode of the transistor Q16. The gate of the transistor Q16, which is the second control electrode, is connected to the drain of the transistor Q13 in the differential amplifier 21. The drain of the transistor Q16, which is the fourth main electrode, is grounded. A phase compensation circuit 24 is connected between the source and gate of the transistor Q16.
[0065]
Next, the operation of the series regulator 4 will be described.
The transistor Q15 outputs an output voltage Vout based on the voltage applied to the gate from the drain. The output voltage detector 12 divides the output voltage Vout and supplies the divided voltage to the differential amplifier 21. The differential amplifier 21 amplifies the error voltage between the divided voltage supplied from the output voltage detection unit 12 and the reference voltage Vref supplied from the reference voltage unit 14, and supplies the amplified error voltage to the gate of the transistor Q16.
[0066]
When the output voltage Vout decreases and the divided voltage supplied from the output voltage detector 12 becomes lower than the reference voltage Vref of the reference voltage unit 14, the gate voltage of the transistor Q16 decreases. When the gate voltage of the transistor Q16 decreases, the gate-source voltage of the transistor Q16 increases. As a result, the current flowing through the transistor Q16 increases, and the gate voltage of the transistor Q15 decreases. For this reason, the equivalent resistance of the transistor Q15 decreases, and the current flowing through the transistor Q15 increases, so that the output voltage Vout increases.
[0067]
On the other hand, when the output voltage Vout rises and the divided voltage supplied from the output voltage detection unit 12 becomes higher than the reference voltage Vref of the reference voltage unit 14, the gate voltage of the transistor Q16 increases, The voltage between the sources drops. For this reason, the equivalent resistance of the transistor Q15 increases, and the current flowing through the transistor Q15 decreases, so that the output voltage Vout decreases.
[0068]
Thus, in the series regulator 4 including the transistors Q15 and Q16, the transistors Q15 and Q16 function in the same manner as the transistors Q9 and Q10 of the third embodiment. The phase compensation circuit 24 performs phase compensation of the control signal as in the third embodiment. Therefore, the series regulator 4 has the same operational effects as the series regulator 3 of the third embodiment.
[0069]
[Fifth Embodiment]
FIG. 6 is a configuration diagram of a series regulator according to the fifth embodiment of the present invention. Elements common to those in FIG. 1 are denoted by common reference numerals.
[0070]
In the series regulators 1 to 4 of the first to fourth embodiments so far, the voltage output unit 11 and the amplifier 23 are each composed of one transistor. However, the voltage output unit 11 or the amplifier 23 is A plurality of transistors may be used.
[0071]
The voltage output unit 11 of the series regulator 5 of FIG. 6 includes a transistor Q17 that is an NPN bipolar transistor and a transistor Q18 that is an NPN bipolar transistor. The amplifier 23 of the series regulator 5 includes a transistor Q19, which is an NPN bipolar transistor, and a transistor Q20, which is an NPN bipolar transistor. Other configurations of the series regulator 5 are the same as those of the series regulator 1, for example.
[0072]
The collectors which are the first main electrodes of the transistor Q17 and the transistor Q18 of the voltage output unit 11 are connected to the input terminal Pin. The emitter of the transistor Q17 is connected to the base of the transistor Q18. The emitter of the transistor Q18, which is the second main electrode, is connected to the output terminal Pout. That is, the transistors Q17 and Q18 are Darlington connected. The base that is the first control electrode of the transistor Q17 in the first stage is connected to the collector that is the third main electrode of the transistors Q19 and Q20 in the amplifier 23.
[0073]
The emitter of the transistor Q19 in the amplifier 23 is connected to the base of the transistor Q20. That is, the transistor Q19 and the transistor Q20 are Darlington connected. The base that is the second control electrode of the first-stage transistor Q19 is connected to the collector of the transistor Q5 of the differential amplifier 21. The emitter of the transistor Q20, which is the fourth main electrode, is grounded. A phase compensation circuit 24 is connected between the collectors of the transistors Q19 and Q20 and the base of the transistor Q19.
[0074]
In such a series regulator 5, the voltage output unit 11 configured by the transistors Q17 and Q18 operates in the same manner as the voltage output unit 11 of the series regulator 1 configured by the transistor Q1. The amplifier 23 composed of the transistors Q19 and Q20 operates in the same manner as the amplifier 23 of the series regulator 1 composed of the transistor Q2.
[0075]
Therefore, the series regulator 5 has the same effect as the series regulator 1 of the first embodiment. In addition, since the voltage output unit 11 and the amplifier 23 of the series regulator 5 are configured by Darlington-connected transistors Q17 and Q18 and transistors Q19 and Q20, respectively, it becomes possible to increase the amplification factor of the power transistor. ing.
[0076]
[Sixth Embodiment]
FIG. 7 is a block diagram of a series regulator according to the sixth embodiment of the present invention. Elements common to those in FIG. 6 are denoted by common reference numerals.
[0077]
In the series regulator 5 of the fifth embodiment described above, the voltage output unit 11 and the amplifier 23 are each composed of a plurality of NPN type bipolar transistors, but can also be composed of PNP type bipolar transistors.
[0078]
The voltage output unit 11 of the series regulator 6 shown in FIG. 7 includes a transistor Q21 that is a PNP bipolar transistor and a transistor Q22 that is a PNP bipolar transistor. The amplifier 23 of the series regulator 6 includes a transistor Q23, which is a PNP bipolar transistor, and a transistor Q24, which is a PNP bipolar transistor. Other configurations of the series regulator 6 are the same as those of the series regulator 5, for example.
[0079]
The collectors which are the second main electrodes of the transistor Q21 and the transistor Q22 of the voltage output unit 11 are connected to the output terminal Pout. The emitter of the transistor Q21 is connected to the base of the transistor Q22. The emitter of the transistor Q22, which is the first main electrode, is connected to the input terminal Pin. That is, the transistors Q21 and Q22 are Darlington connected. The base that is the first control electrode of the transistor Q21 in the first stage is connected to the emitter that is the third main electrode of the transistor Q24 in the amplifier 23.
[0080]
The emitter of the transistor Q23 in the amplifier 23 is connected to the base of the transistor Q24. That is, the transistor Q23 and the transistor Q24 are Darlington connected. The base that is the second control electrode of the first-stage transistor Q23 is connected to the collector of the transistor Q5 of the differential amplifier 21. The collectors which are the fourth main electrodes of the transistors Q23 and Q24 are grounded. A phase compensation circuit 24 is connected between the emitter of the transistor Q24 and the base of the transistor Q23.
[0081]
In such a series regulator 6, the voltage output unit 11 configured by the transistors Q21 and Q22 operates in the same manner as the voltage output unit 11 of the series regulator 2 configured by the transistor Q7. The amplifier 23 composed of the transistors Q23 and Q24 operates in the same manner as the amplifier 23 of the series regulator 2 composed of the transistor Q8.
[0082]
Therefore, the series regulator 6 has the same effect as the series regulator 2 of the second embodiment. Further, since the voltage output unit 11 and the amplifier 23 of the series regulator 6 are configured by Darlington-connected transistors Q21 and Q22 and transistors Q23 and Q24, respectively, it becomes possible to increase the amplification factor of the power transistor. ing.
[0083]
[Seventh Embodiment]
FIG. 8 is a block diagram of a series regulator according to the seventh embodiment of the present invention. Elements common to those in FIG. 6 are denoted by common reference numerals.
[0084]
In the series regulators 5 and 6 of the fifth and sixth embodiments described above, the voltage output unit 11 includes a plurality of NPN bipolar transistors or PNP bipolar transistors, and the amplifier 23 includes a plurality of NPN bipolar transistors or PNP. It consisted of a bipolar transistor. The voltage output unit 11 may be composed of an NPN bipolar transistor and a PNP bipolar transistor. It is also possible to configure the amplifier 23 with an NPN type bipolar transistor and a PNP type bipolar transistor.
[0085]
The voltage output unit 11 of the series regulator 7 shown in FIG. 8 includes a transistor Q25 that is a PNP bipolar transistor and a transistor Q26 that is an NPN bipolar transistor. The amplifier 23 of the series regulator 7 includes a transistor Q27, which is a PNP bipolar transistor, and a transistor Q28, which is an NPN bipolar transistor. Other configurations of the series regulator 7 are the same as those of the series regulator 6, for example.
[0086]
The collector of the transistor Q25 of the voltage output unit 11 is connected to the base of the transistor Q26, the emitter of the transistor Q25 is connected to the collector of the transistor Q26, and the transistor Q25 and the transistor Q26 are Darlington-connected. The collector of the transistor Q26, which is the first main electrode, is connected to the input terminal Pin. The emitter of the transistor Q26, which is the second main electrode, is connected to the output terminal Pout. The base of the transistor Q25, which is the first main electrode, is connected to the emitter of the transistor Q27 in the amplifier 23 and the collector, which is the third main electrode of the transistor Q28.
[0087]
The collector of the transistor Q27 in the amplifier 23 is connected to the base of the transistor Q28. That is, the transistor Q27 and the transistor Q28 are Darlington connected. The base that is the second control electrode of the first-stage transistor Q27 is connected to the collector of the transistor Q5 of the differential amplifier 21. The emitter of the transistor Q28, which is the fourth main electrode, is grounded. The phase compensation circuit 24 is connected between the collector of the transistor Q28 and the base of the transistor Q27.
[0088]
In such a series regulator 7, the voltage output unit 11 composed of the transistors Q25 and Q26 operates in the same manner as the voltage output unit 11 of the series regulator 6 of the sixth embodiment. The amplifier 23 composed of the transistors Q27 and Q28 operates in the same manner as the amplifier 23 of the series regulator 6.
Therefore, the series regulator 7 has the same effect as the series regulator 6 of the sixth embodiment.
In carrying out the present invention, various forms are conceivable and the present invention is not limited to the above embodiment. For example, the transistor Q1 constituting the voltage output unit 11 can be changed to a Darlington-connected transistor in three or more stages. Further, the transistor Q2 constituting the amplifier 23 can be changed to a transistor connected in Darlington to three or more stages.
[0089]
【The invention's effect】
As described above in detail, according to the present invention, the stabilized power supply circuit operates stably.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a stabilized power supply circuit according to a first embodiment of the present invention.
FIG. 2 is an explanatory diagram showing a phase compensation operation of the stabilized power supply circuit of FIG. 1;
FIG. 3 is a circuit diagram showing a configuration of a stabilized power supply circuit according to a second embodiment of the present invention.
FIG. 4 is a circuit diagram showing a configuration of a stabilized power supply circuit according to a third embodiment of the present invention.
FIG. 5 is a circuit diagram showing a configuration of a stabilized power supply circuit according to a fourth embodiment of the present invention.
FIG. 6 is a circuit diagram showing a configuration of a stabilized power supply circuit according to a fifth embodiment of the present invention.
FIG. 7 is a circuit diagram showing a configuration of a stabilized power supply circuit according to a sixth embodiment of the present invention.
FIG. 8 is a circuit diagram showing a configuration of a stabilized power supply circuit according to a seventh embodiment of the present invention.
FIG. 9 is a circuit diagram showing a configuration of a conventional stabilized power supply circuit.
FIG. 10 is an explanatory diagram showing a phase compensation operation of a conventional stabilized power supply circuit.
[Explanation of symbols]
1-7 series regulator
11 Voltage output section
12 Output voltage detector
13 Error amplifier
14 Reference voltage section
22 Constant current circuit
21 Differential amplifier
23 Amplifier
24 Phase compensation circuit
Q1, Q7, Q9, Q15, Q17, Q18, Q21, Q22, Q25, Q26 Transistors (for output voltage control)
Q2, Q8, Q10, Q16, Q19, Q20, Q23, Q24, Q27, Q28 Transistors (for amplification)
C1 capacitor (for stabilizing output voltage)
C2, C3 capacitors (for phase compensation)
R3 resistance (for phase compensation)

Claims (4)

A voltage output unit that is supplied with a DC voltage and outputs a DC output voltage based on a control signal;
A differential amplifier that generates an error voltage between an output voltage output from the voltage output unit and a reference voltage;
An amplifier that amplifies the error voltage and outputs the amplified error voltage to the voltage output unit as the control signal;
A resistor and a first capacitor are connected in series between the error voltage input terminal and the control signal output terminal of the amplifier, and the control signal is fed back to the error voltage for phase compensation. And setting a first cutoff frequency in a frequency band in which the gain when the error voltage is amplified exceeds 1 in the frequency characteristics of the control signal, and a phase at a frequency higher than the first cutoff frequency. A first phase compensation circuit for maintaining a margin in a range of 30 ° to 90 °;
A second capacitor connected in parallel with the resistor of the first phase compensation circuit, in a frequency band higher than the first cutoff frequency and having a gain of 1 or less in the frequency characteristic of the control signal; set the second cutoff frequency, a second phase compensation circuit for the gain definitive frequency higher than the cut-off frequency of the second to less than 1,
A stabilized power supply circuit comprising: The voltage output unit includes a first main electrode, a second main electrode, a first control electrode for controlling a conduction state between the first main electrode and the second main electrode, and the amplification. The first control electrode is connected to a terminal for outputting the control signal of the storage device, the first main electrode is connected to a terminal to which the DC voltage is supplied, and the terminal to which the output voltage is output Constituted by a first transistor to which two main electrodes are connected,
The amplification unit, the main electrodes of a constant current circuit connected, the third main electrode and the fourth main electrode and the third and between the before and Symbol first main electrode and the first control electrode And a second control electrode for controlling a conduction state between the fourth main electrodes, and the second control electrode constitutes a terminal for inputting the error voltage and is connected to the output terminal of the differential amplifier. The third main electrode constitutes a terminal for outputting the control signal, is connected to the first control electrode, and the fourth main electrode is formed by a grounded second transistor .
The stabilized power circuit according to claim 1 . Each of the voltage output units includes a first main electrode, a second main electrode, the first main electrode, and a first control electrode that controls a conduction state between the second main electrodes, and Darlington. comprising a transistor of the plurality of connected stages, the first stage of the first control electrode of the transistor of the transistors of said control signal several stages plurality to the output terminals of the amplifier device is connected, the DC voltage is supplied A first main electrode of a final-stage transistor of the plurality of transistors is connected to a first terminal, and a second main electrode of the final-stage transistor is connected to a terminal from which the output voltage is output. The stabilized power supply circuit according to claim 1 . The voltage output unit includes a first main electrode connected to a terminal to which the DC voltage is supplied, a second main electrode connected to a terminal to which the output voltage is output, and the first and second main electrodes. A first control electrode for controlling a conduction state between the electrodes,
The amplifier is
A constant current circuit connected between the first main electrode and the first control electrode;
The third main electrode, the fourth main electrode, the third main electrode, and the second control electrode for controlling the conduction state between the fourth main electrode, and a plurality of stages connected in Darlington connection Formed by a transistor ,
The second control electrode of the first stage transistor of the plurality of stages of transistors constitutes a terminal for inputting the error voltage and is connected to the output terminal of the differential amplifier, and the last stage of the plurality of stages of transistors is connected. A third main electrode of the first transistor constitutes a terminal for outputting the control signal and is connected to the first control electrode, and a fourth main electrode of the final-stage transistor is grounded;
The stabilized power circuit according to claim 1 .

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