JP3717606B2 - Controllable input buffer, integrated circuit including the same, and method for adjusting setup and hold times of logic devices - Google Patents

Description

[0001]
FIELD OF THE INVENTION
The present invention relates to the field of logic devices, and more particularly to controllable adjustment of logic device setup and hold times.
[0002]
[Description of related technology]
Many digital logic devices use the same generic device to receive and hold input data. In this device, a periodic latching pulse is applied to the clock signal input line connected to the logic device, so that the rising or falling edge of the latching pulse triggers a latching circuit within the logic device. Used for. When triggered, the latching circuit captures and holds whatever logic data level is currently on the data signal input line connected to the logic device.
[0003]
Due to the parasitic line capacitance common to all logic devices and the non-zero switching speed of semiconductor components typically used in logic devices, valid data is entered at exactly the same time as the corresponding latching circuit is triggered. Cannot be given to the line. Instead, in order for data to be properly latched, a valid input transition must occur on the data input line prior to the occurrence of a latching pulse on the clock input line by some minimum time interval. This shortest time interval, which is typically different for all logical units, is known as the shortest “setup time” required for the logical unit.
[0004]
Similarly, valid data cannot be removed from the data input line immediately after the corresponding latching circuit is triggered without causing the latching circuit to fail. In particular, an input invalid transition may occur in the data input line at the shortest time interval after a latching pulse occurs in the clock input line. This shortest time is known as the shortest “hold time” required of the logic device and is typically different for all logic devices.
[0005]
Even the most basic logic designs usually require that various logic units be driven by a common clock signal while operating on a common data input signal, so that It would be desirable to be able to controllably adjust the setup and hold times of a given logic unit so that setup and hold times can be matched. Prior art attempts to adjust the setup and hold times shift the data input signal in time with respect to the clock signal so that the effective setup and hold times of the logic device receiving the signal are adjusted. Using a delay element.
[0006]
For example, U.S. Pat. No. 5,107,153 to Osaki et al. Discloses a delay circuit that includes a parallel connection of switchable capacitors. By changing the number of active capacitors in the circuit, the data input signal can be controllably shifted in time with respect to the clock signal, so that the data input signal transitions between valid and invalid input transitions. Both are shifted in time with respect to the latching pulse of the clock signal. In this manner, the effective setup time and the effective hold time of the logic device that receives the delayed data input signal and the clock signal are adjusted. Other controllable delay circuits can be applied to achieve the same result in such situations. For example, Woo U.S. Pat. No. 5,220,216 discloses a CMOS gate with programmable drive power characteristics and variable propagation delay.
[0007]
However, such a system only delays the data input signal uniformly, and therefore the effective setup time and effective hold time cannot be adjusted independently of each other. As an example, consider a data input signal that is delayed in time relative to a clock signal by an amount Δ. In such a case, valid transitions of the input of the data input signal that occur prior to the corresponding latching pulse of the clock signal will be delayed by an amount Δ, so that they are close in time to the latching pulse. appear. Furthermore, ineffective transitions of the data input signal that occur after the corresponding latching pulse of the clock signal will be delayed by the same amount Δ, so they occur away in time from the latching pulse. Thus, the effective hold time of the logic device receiving the delayed data input signal and the clock signal is reduced by an amount Δ, but only at the expense of increasing the effective set-up time of the logic device by the same amount Δ. It is. This concept is succinctly expressed in the explanation that the sum of the setup and hold times, defined as the sum of the valid setup and hold times, remains constant regardless of the value chosen for Δ. It is. As logic design becomes more and more complex, such limitations are a serious problem because the designer's flexibility in choosing and mixing logic components is paramount.
[0008]
SUMMARY OF THE INVENTION
There is a need for a system that allows simultaneous but independent adjustment of logic unit setup and hold times. This need and other needs are met by the present invention which provides a controllable input buffer for driving a logic device having setup and hold time characteristics. The controllable input buffer includes a controllable signal filter that receives the input signal and shapes the amplitude of the input signal and provides the input signal with the amplitude shaped to the logic device. The controllable signal filter includes at least one control signal input that receives the control signal and responsively controls the amplitude shaping characteristic of the signal filter to adjust the sum of the logic device setup and hold times. . Thus, the effective setup time and effective hold time of the logic device can be adjusted independently.
[0009]
The present invention further provides an integrated circuit having setup and hold time characteristics. The integrated circuit includes a logic circuit for performing a predetermined function and a controllable input buffer. The controllable input buffer includes a controllable signal filter that receives the input signal, shapes the amplitude of the input signal, and provides the logic circuit with the input signal having a shaped amplitude. The controllable signal filter includes at least one control signal input that receives the control signal and responsively controls the amplitude shaping characteristic of the signal filter to adjust the total setup and hold times of the integrated circuit. Thus, the effective setup time and effective hold time of the integrated circuit can be adjusted independently.
[0010]
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the invention when read in conjunction with the accompanying drawings.
[0011]
Detailed Description of the Preferred Embodiment
FIG. 1 shows a prior art system used to adjust the effective setup time and effective hold time associated with logic device 10. The shortest required setup time ST of the logic device 10 is defined as the shortest allowable time interval between the arrival of a valid input signal on the input line 14 and the occurrence of a latching pulse on the clock line 12. The If the time between a valid transition of the input on line 14 and the corresponding latching pulse on line 12 is longer than or equal to the shortest setup time ST required, valid input The signal will be properly latched by a latching circuit inside the logic device 10, and the logic device 10 will function as intended. However, if the time interval between the valid transition of the input on line 14 and the latching pulse on line 12 is shorter than the shortest setup time ST required, the valid input signal is properly latched. The logic unit 10 will not work well.
[0012]
Conversely, the shortest required hold time HT of the logic device 10 is the shortest allowable time interval between the generation of a latching pulse on the clock line 12 and the removal of the valid input signal from the input line 14. Is defined as If the time between the latching pulse on line 12 and the invalid transition of the corresponding input on line 14 is greater than or equal to the shortest hold time HT required, the valid input The signal will be properly latched and the logic device 10 will function as intended. However, if the time interval between the latching pulse on line 12 and the invalid transition of the input on line 14 is less than the shortest hold time HT required, the valid input signal is properly latched. The logic unit 10 will not work well.
[0013]
In order to allow adjustment of the effective setup time ST _eff and effective hold time HT _eff of the logic device 10, the signal induced on the input line 14 appears to be a delayed replica of the input signal reaching the input line 18. A delay element 16 is provided. Adjustment of the effective setup time and hold time is accomplished by changing the amount of delay provided by the delay element 16. To illustrate this, FIG. 2 shows the relative timing between the input signal reaching input line 18, the delayed input signal induced on input line 14, and the clock signal transmitted on clock line 12. .
[0014]
As shown, the delayed input signal on line 14 is shifted in time relative to the input signal on line 18 by an amount Δ, so that a valid input transition 26 of the delayed input has a corresponding valid input transition 22. Occurs on line 14 after Δ of time occurring on line 18. The interval t _s is defined between the input valid transition 22 and the clock latching pulse 20 occurring on the line 12. Further, the interval t _s ′ is defined between the delayed input valid transition 26 and the clock latching pulse 20. To define, the relationship between t _s and t _s ′ is t _s ′ = t _s −Δ. As mentioned above, t _s ′ must be longer than or equal to the shortest setup time ST required for the logic device 10 to function properly. Therefore, t _s must be greater than or equal to the amount of ST + Δ. This amount is therefore the effective setup time ST _eff of the device of FIG. ST _eff constitutes the shortest acceptable time interval between the valid transition of the input on input line 18 and the clock latching pulse on line 12.
[0015]
Similarly, a delayed input invalid transition 28 occurs on line 14 after time Δ when the corresponding input invalid transition 24 occurs on line 18. The two intervals t _h and t _h ′ are defined to be t _h ′ = t _h + Δ. Again, as noted above, t _h ′ must be greater than or equal to the shortest hold time HT required for the logic device 10 to function properly. Therefore, t _h must be greater than or equal to the quantity HT−Δ, ie the effective hold time HT _eff of the device of FIG.
[0016]
By changing the amount of delay Δ, the effective setup and hold times ST _eff and HT _eff can be controllably adjusted. However, the effective setup and hold times ST _eff and HT _eff are independent because both the input valid transition 22 and the input non-valid transition 24 are each delayed by the same amount Δ to provide delayed transitions 26 and 28, respectively. May not be adjusted. The total setup and hold time A _{s & h} defined as ST _eff + HT _eff = (ST + Δ) + (HT−Δ) is constant regardless of the delay amount Δ. Thus, the effective setup time ST _eff is increased or decreased only at the expense of decreasing or increasing the effective hold time HT _eff by the same amount, and vice versa.
[0017]
FIG. 3 illustrates a system for adjusting the setup and hold times of a logic device configured in accordance with an embodiment of the present invention. The controllable input buffer 32 includes a controllable signal filter 30 and one or more control signal inputs 34. A controllable signal filter 30 receives the input signal on the input line 18 and sends the amplitude shaped input signal to the logic device 10 on the input line 14. At the same time, the control signal input 34 receives a corresponding control signal, for example from a microprocessor, and adjustably adjusts the amplitude shaping characteristics of the controllable signal filter 30. Thus, the amplitude shaped input signal received by the logic device 10 is controllably adjusted so that the effective setup time ST _eff and the effective hold time HT _eff of the logic device 10 are adjusted to have predetermined values. Is done.
[0018]
Advantageously, the embodiment of FIG. 3 allows independent adjustment of the effective setup time ST _eff and the effective hold time HT _eff of the logic device 10. To illustrate this, FIG. 4 provides a schematic diagram of a controllable signal filter 30 configured in accordance with an embodiment of the present invention. In FIG. 4, CMOS inverters INV <b> 1 to INVN are connected in parallel between an input line 14 and an input line 18. Each of CMOS inverters INV1 to INVN includes two MOS transistors that are controlled independently.
[0019]
For example, the inverter INV1 includes a PMOS transistor P1 and an NMOS transistor N1. PMOS transistor P1 via the control circuit having an enable transistor EP1 and control line 34 _p1, are controlled by a control signal CP1. The NMOS transistor N1 is controlled by a control signal CN1 through a control circuit including an enable transistor EN1 and a control line 34 _N1 .
[0020]
When the control signal CP1 is logic 0, the enable transistor EP1 is set to the “on” state, so that the PMOS transistor P1 is activated and active in the circuit. However, when the control signal CP1 is logic 1, EP1 is “off” and P1 is disabled and effectively removed from the circuit. Similarly, when the control signal CN1 is logic 1, the enable transistor EN1 is “on” and the NMOS transistor N1 is enabled and active in the circuit. When CN1 is logic 0, EN1 is “off” and N1 is disabled and not active.
[0021]
Thus, the control signals CP1 to CPN can be used to adjust the number of PMOS transistors P1 to PN activated in the circuit, and the control signals CN1 to CNN are NMOS transistors activated in the circuit. It can be used to adjust the number of N1 to NN. In this way, the PN ratio of the controllable signal filter 30, defined as the ratio of the activated PMOS transistor to the activated NMOS transistor, can be tightly controlled. As will be described next, the PN ratio adjusts the characteristics of the controllable signal filter 30 to shape the amplitude and allows the effective setup and logic of the logic device to receive the amplitude shaped input signal at the input line 14 and It can be modified to adjust the hold time independently.
[0022]
When the input signal on input line 18 is at logic level 0, NMOS transistors N1-NN activated in the circuit are "off" and do not change the amplitude shaped input signal on line 14. However, the PMOS transistors P1 to PN activated in the circuit are "on" and the amplitude-shaped input signal on line 14 is set to logic level 1 ( _Vcc ). Conversely, when the input signal on line 18 goes to logic level 1, enable PMOS transistors P1-PN are "off", causing no change in amplitude shaped input signal, and enable NMOS transistors N1-NN are ""On" and the amplitude-shaped input signal is set to logic level 0 (GND).
[0023]
Thus, a valid input transition from logic level 0 to logic level 1 is different from a non-valid input transition from logic level 1 to logic level 0 as it passes from line 18 to line 14. Filtered. The manner in which a valid transition of the input passes from line 18 to line 14 is largely determined by the number of NMOS transistors activated in the circuit, and in general, the higher the number of enabled NMOS transistors, the more the line 14 The effective transition of the input transmitted to is fast. Conversely, the manner in which an invalid input transition is transferred from line 18 to line 14 is largely determined by the number of enabled PMOS transistors. Again, in general, the greater the number of enabled PMOS transistors, the faster the ineffective transition of the input that is transmitted on line 14. Note that the signal traveling on line 14 is actually the inverted version of the signal reaching line 18. This is usually not a problem because many logic devices use inverting latching circuits to sample and hold the input signal. However, if the logic device in question does not use an inverting latching circuit, an inverter can be introduced on line 14 to return the signal to its original direction.
[0024]
Since the controllable signal filter 30 can be controlled to filter or shape the input valid and inactive transitions differently, the embodiment of FIG. 3 reduces the effective setup and hold times of the logic device. Can be used to adjust independently. To further illustrate this point, FIG. 5 shows the input signal reaching the input line 18, the amplitude shaped input signal induced on the input line 14, and the clock signal transmitted on the clock line 12. The relative timing between is shown.
[0025]
As shown, the amplitude-shaped input signal on line 14 has a valid input valid transition 50 relative to the input signal on line 18 and a corresponding input valid transition 22. Shaped to occur on line 14 after time δ ₁ after occurrence on line 18. The interval t _s is defined between the input valid transition 22 and the clock latching pulse 20 occurring on the line 12. Further, the interval t _s ″ is defined between a valid input valid transition 50 and the clock latching pulse 20. By definition, the relationship between _ts and t _s ″ is t _s ″. = T _s −δ _1. As described with respect to FIG. 1, t _s ″ is greater than or equal to the shortest setup time ST required for the logic device 10 to function properly. There must be. Therefore, t _s must be greater than or equal to the quantity ST + δ ₁ , ie the effective setup time ST _eff of the device of FIG. ST _eff constitutes the shortest allowable time interval between the valid transition of the input on input line 18 and the clock latching pulse on line 12.
[0026]
Similarly, a valid non-input valid transition 52 occurs on line 14 after time δ ₂ after the corresponding non-input valid transition 24 occurs on line 18. The two intervals t _h and t _h ″ are defined such that t _h ″ is equal to t _h + δ ₂ . Again, as described with respect to FIG. 1, t _h ″ needs to be greater than or equal to the shortest hold time HT required for the logic device 10 to function properly. Therefore, t _h needs to be greater than or equal to the quantity HT−δ ₂ , ie the effective hold time HT _eff of the device of FIG.
[0027]
By changing the value of δ ₁ , the effective setup time ST _eff can be controllably adjusted. Furthermore, by changing the value of δ ₂ , the effective hold time HT _eff can be controllably adjusted. Since δ ₁ and δ ₂ can be adjusted independently, effective setup and hold times ST _eff and HT can be _achieved , for example, by changing the number of enabled NMOS and PMOS transistors in the controlled signal filter 30 as described with respect to FIG. _eff can be adjusted independently. Similarly, the total setup and hold time, A _{s & h} , defined as ST _eff + HT _eff = (ST + δ ₁ ) + (HT−δ ₂ ) can be controllably adjusted.
[0028]
FIG. 6 is a block diagram of an alternative embodiment of the present invention. In this embodiment, integrated circuit 60 includes controllable input buffer 32 and logic circuit 62. The controllable input buffer 32 includes a controllable signal filter 30 and one or more control signal inputs 34. In addition, logic circuit 62 includes a latching circuit 64 and an additional circuit configuration 66. The configuration of the additional circuit configuration 66 is arbitrary and may be configured to perform all desired logic functions. Thus, the integrated circuit 60 may be used as a component in any circuit design of interest. Further, as described below, the controllable input buffer 32 independently controls the effective setup and hold times of the integrated circuit 60 to match the setup and hold times of other components in the circuit design. It may be used to adjust.
[0029]
In the embodiment of FIG. 6, controllable signal filter 30 receives the input signal on input line 18 and sends the amplitude shaped input signal to logic circuit 62 on input line 14. At the same time, the control signal input 34 receives a corresponding control signal, eg, from a microprocessor, and adjusts the controllable characteristics of the controllable signal filter 30 for amplitude. Controllable signal filter 30, for example as shown in FIG. 4, is received by the logic circuit 62, the shaped input signal amplitude is adjusted so as to be controlled, and effective setup time of the integrated circuit 60 ST _eff and effective The hold time HT _eff may be configured to be independently adjusted to have a predetermined value. Similarly, the total setup and hold time A _{s & h of} the integrated circuit 60, which is defined to be ST _eff + HT _eff , is controllably adjusted.
[0030]
It should be noted that the detailed embodiments described above are provided for illustration only and are not intended to limit the scope of the invention. For example, other alternatives to the controllable signal filter 30 embodiment depicted in FIG. 4 may be considered. In one such embodiment, some of the NMOS transistors N1-NN and some of the PMOS transistors P1-PN are not controllable and remain permanently activated. Furthermore, an embodiment can be considered in which a pair of NMOS and PMOS transistors are activated in series so that the inverters INV1-INVN are selectively activated or deactivated as discrete units. Embodiments can also be envisaged where only NMOS transistors or only PMOS transistors are enabled and disabled to adjust the PN ratio of the controllable signal filter. With respect to the controllable signal filter 30 as used in the integrated circuit of FIG. 6, the controllable signal filter 30 is not used to shape the input data signal, but instead of the clock signal or integrated circuit 60. It can also be considered an embodiment used to shape other signals inside. In sum, the present invention has been described and illustrated in detail, which is by way of illustration and example only and is not to be construed as limiting, and the spirit and scope of the invention is limited only by the appended claims. Is clearly understood.
[Brief description of the drawings]
FIG. 1 is a block diagram of a prior art system for adjusting logic device setup and hold times.
FIG. 2 is a timing analysis diagram of the prior art system of FIG.
FIG. 3 is a block diagram of a system configured in accordance with an embodiment of the present invention for adjusting logic device setup and hold times.
4 is a schematic diagram of a controllable input buffer configured in accordance with an embodiment of the present invention and constituting one component of the system of FIG.
FIG. 5 is a timing analysis diagram of the system of FIG.
FIG. 6 is a block diagram of a system used to adjust logic device setup and hold times configured in accordance with another embodiment of the invention.
[Explanation of symbols]
30 Controllable signal filter 32 Controllable input buffer

Claims (2)

A controllable input buffer for driving a logic device having setup and hold time characteristics,
A controllable signal filter that receives the input signal and at least one control signal and provides the logic device with an amplitude-shaped input signal by controlling a transition time between logic levels of the input signal;
The controllable signal filter includes a plurality of parallel- connected CMOS inverters that receive the input signal and output the amplitude-shaped input signal, each of the plurality of CMOS inverters being connected in series. At least one of the PMOS transistor and NMOS transistor constituting at least one of the plurality of CMOS inverters is enabled or disabled by the corresponding at least one control signal; This controls the transition time between the logic levels of the input signal according to the PN ratio, which is the ratio of the number of activated PMOS transistors to the number of activated NMOS transistors,
The at least one control signal controls a transition time between logic levels of the input signal of the controllable signal filter such that a sum of setup and hold times of the logic device has a predetermined value. A controllable input buffer that is responsively generated to determine the ratio. An integrated circuit having setup and hold time characteristics,
A logic circuit for performing a predetermined function;
And a controllable input buffer
The controllable input buffer is
A controllable signal filter that receives the input signal and at least one control signal and provides the logic device with an amplitude-shaped input signal by controlling a transition time between logic levels of the input signal;
The controllable signal filter includes a plurality of parallel- connected CMOS inverters that receive the input signal and output the amplitude-shaped input signal, each of the plurality of CMOS inverters being connected in series. At least one of the PMOS transistor and NMOS transistor constituting at least one of the plurality of CMOS inverters is enabled or disabled by the corresponding at least one control signal; This controls the transition time between the logic levels of the input signal according to the PN ratio, which is the ratio of the number of activated PMOS transistors to the number of activated NMOS transistors,
The at least one control signal controls a transition time between logic levels of the input signal of the controllable signal filter such that a sum of setup and hold times of the logic device has a predetermined value. An integrated circuit that is responsively generated to determine the ratio.

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