JP3727480B2 - Synchronous signal regeneration circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a synchronization signal reproduction circuit used for a receiver of a television broadcast signal, and more particularly to a synchronization signal reproduction capable of outputting a stable reproduction horizontal synchronization signal and reproduction vertical synchronization signal even when foreign broadcast signals and the like are mixed. Regarding the circuit.
[0002]
[Prior art]
When a signal is propagated wirelessly, there is a case where a signal from a distant place interferes due to reflection in the ionosphere.
In particular, there is an ionosphere that suddenly appears near the same altitude as the ionosphere (E layer) generated at an altitude of about 100 km, called the sporadic E layer. It is known that it causes abnormal propagation of radio waves in the band (VHF) and causes foreign broadcast signals to interfere with domestic television broadcast signals ("Sporadic E layer propagation and foreign radio interference", Television Society Journal, Vol. 36, No. 5 (1982)).
[0003]
On the other hand, in television broadcasting, when transmitting a video signal, the transmitter side adds a synchronization signal indicating which pixel of the screen is transmitted to the video signal and transmits the video signal, and the receiver side transmits this synchronization signal. Is reproduced by a synchronizing signal reproducing circuit, and the movement of the electron beam of the picture tube is controlled using the reproduced synchronizing signal to assemble the image.
Here, the synchronization signal includes a horizontal synchronization signal that indicates the timing of moving to the next horizontal scan after finishing one horizontal scan of the screen, and a vertical synchronization signal that indicates the timing of moving to the next field after finishing one field scan. is there.
[0004]
In addition to the signal format called NTSC used in Japan, TV broadcast signals include a signal format called PAL that is widely used in Europe and the like. I will explain it with the signal in mind.
[0005]
A conventional synchronizing signal reproduction circuit will be described with reference to FIG. FIG. 14 is a configuration block diagram showing a configuration example of a conventional synchronization signal reproduction circuit.
As shown in FIG. 14, the conventional synchronizing signal regeneration circuit includes a sync chip clamp circuit 21, a first threshold value determination circuit 22, a first one-shot gate circuit 23, an integrator 24, a second The threshold determination circuit 25 and the second one-shot gate circuit 26 are mainly configured.
[0006]
Hereinafter, each part will be described in detail. The sync chip clamp circuit 21 receives the input of the NTSC inverted signal, and clamps the level of the leading end portion (sync chip) of the synchronization pulse included in the NTSC inverted signal (level). Is a constant voltage) and output.
[0007]
The first threshold value determination circuit 22 compares the signal output from the sync chip clamp circuit 21 with a preset threshold value, and the signal output from the sync chip clamp circuit 21 is greater than the threshold value. If it is large, a pulse signal is output.
The threshold value is a value for detecting a horizontal synchronization signal.
[0008]
The first one-shot gate circuit 23 includes an electrical switch (gate) that is open in a normal state. When the gate signal is open when the gate is open, Outputs as a playback horizontal sync signal (through output) and closes the gate until a certain period of time equal to or more than one half of the horizontal sync signal period (horizontal sync signal period) has elapsed, and pulses when the gate is not open Even when a signal is input, the signal is not output to the outside.
[0009]
Note that the first one-shot gate circuit 23 generates an equalizing pulse (horizontal period of half the horizontal synchronizing signal) during the vertical blanking period of the NTSC signal (the period during which the scanning line returns from the lower right of the screen to the upper left of the screen). When a signal having the same voltage level as that of the synchronization pulse is transmitted, it operates as a protection circuit for preventing an unnecessary pulse from being generated.
[0010]
The integrator 24 integrates the signal input from the sync tip clamp circuit 21 over a certain period of time, and outputs the result of the integration as an integration value.
[0011]
The second threshold value determination circuit 25 compares the integral value input from the integrator 24 with a preset threshold value. If the integral value is larger than the threshold value, the second threshold value determination circuit 25 determines the pulse signal. Output to the outside.
The threshold value is a value for detecting a vertical synchronization signal.
[0012]
The second one-shot gate circuit 26 is the same as the first one-shot gate 23. When the gate is open, the second one-shot gate circuit 26 receives the pulse signal input from the second threshold value determination circuit 25 and continues as it is. While outputting (through output) as a reproduction | regeneration vertical synchronizing signal, a gate is closed until the fixed time about 3 times the horizontal synchronizing signal period (horizontal synchronizing signal period) passes.
Further, the second one-shot gate circuit 26 is configured not to output a pulse signal to the outside even when the gate is closed.
[0013]
Next, the operation of the conventional sync signal reproduction circuit will be described.
First, the sync tip clamp circuit 21 receives an NTSC inversion signal from the outside, controls the level of the front end portion of the synchronization pulse to a constant voltage, and outputs it.
[0014]
Then, the first threshold value determination circuit 22 compares the signal output from the sync chip clamp circuit 21 with a preset threshold value, and the signal output from the sync chip clamp circuit 21 When it is larger than the threshold value, a pulse signal is output.
[0015]
At this time, since the gate is opened in the first one-shot gate circuit 23, the pulse signal received from the first threshold value judgment circuit 22 is output as it is as a reproduction horizontal synchronization signal. .
From this timing, the first one-shot gate circuit 23 closes the gate until a certain period (a certain time equal to or more than one half of the horizontal synchronizing signal period) elapses.
[0016]
Therefore, even if an unnecessary pulse signal arrives while the gate is closed and the first threshold determination circuit 22 outputs a pulse signal, the first one-shot gate circuit 23 operates to generate a false signal. No reproduction horizontal sync signal is output.
[0017]
On the other hand, the signal output from the sync tip clamp circuit 21 is integrated by the integrator 24 and output to the second threshold value determination circuit 25.
The second threshold value determination circuit 25 outputs a pulse signal when the integrated value input from the integrator 24 is larger than the threshold value as compared with a preset threshold value. It becomes like this.
[0018]
In the second one-shot gate circuit 26, since the gate is initially open, the pulse signal input from the second threshold value determination circuit 25 is output as a reproduced vertical synchronization signal as it is. Become.
Further, the second one-shot gate circuit 26 closes the gate until a certain period (a certain time of about three times the horizontal synchronizing signal period) elapses from this timing.
[0019]
Therefore, even if an unnecessary pulse arrives during the period when the gate is closed and the second threshold value determination circuit 25 outputs a pulse signal, the second one-shot gate circuit 26 operates to generate a false signal. The reproduction vertical synchronization signal is not output.
[0020]
That is, the NTSC inverted signal is a signal in which the waveform of the vertical blanking period shown in the center portion of FIG. 16 is inserted between the repetition of the waveform of the video signal period shown in FIG. 15, and in the video signal period shown in FIG. The pulse signal corresponding to the horizontal synchronization signal has a level difference compared to the video signal and the color burst signal. In the vertical blanking period shown in FIG. The amplitude level is the highest. FIG. 15 is an explanatory diagram illustrating an example of a schematic waveform of the video signal period in the NTSC inverted signal, and FIG. 16 is an explanatory diagram illustrating an example of an approximate waveform of the vertical blanking period in the NTSC inverted signal. It is.
[0021]
That is, the threshold value set in the first threshold value determination circuit 22 is an intermediate level between the pulse signal corresponding to the horizontal synchronization signal and other video signals, as indicated by a broken line in FIG. If the range is set, the pulse signal portion corresponding to the horizontal synchronizing signal can be detected.
[0022]
In addition, in the vertical blanking period, the integral value output by the integrator 24 changes as shown in FIG. 16B and becomes the maximum in the period of the vertical synchronization signal. If the threshold value of the second threshold value determination circuit 25 is set as indicated by a broken line, the reproduced vertical synchronization signal can be detected.
[0023]
[Problems to be solved by the invention]
However, in the above-described conventional sync signal reproduction circuit, when foreign broadcast signals or the like interfere due to the influence of the sporadic E layer, such interference waves, the frequency and electric field strength fluctuate with time, and the horizontal synchronization period The transmitted sync pulse is partially buried in the interference wave, and even if the sync tip clamp circuit operates correctly, it is extremely difficult for the threshold judgment circuit to identify and detect the sync pulse part, There was a problem that the sync signal could not be reproduced.
[0024]
In addition, it is necessary to adjust the threshold value of the threshold value determination circuit according to the level of the received video signal. However, if there is an interference wave, more accurate adjustment is required and adjustment becomes difficult. There was a problem.
[0025]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a synchronization signal reproduction circuit capable of outputting a stable reproduction horizontal synchronization signal and reproduction vertical synchronization signal even in the presence of interference waves.
[0027]
[Means for Solving the Problems]
The present invention for solving the problems of the conventional example described above is a synchronization signal reproduction circuit that outputs a desired reproduction horizontal synchronization signal and reproduction vertical synchronization signal regardless of the presence or absence of interference waves due to the influence of the sporadic E layer. Other than sync pulse components of horizontal and vertical sync signals including equalized pulses from the input NTSC inverted signal Unnecessary signal part Remove Output as a signal in which the horizontal sync pulse component mainly remains From a narrowband filter circuit having filter characteristics to be output and a signal output from the narrowband filter circuit, Add the output signal and the signal of one line delay delayed by one horizontal sync signal period, Equalization pulse component transmitted intermittently in half the horizontal sync signal period of Of which, horizontal sync signal Same timing An equalization pulse removal circuit that passes only the equalization pulse component of the signal, and a signal output from the equalization pulse removal circuit Waveform of Within one line period The maximum level is obtained Peak point Detecting timing, and at that timing, horizontal synchronizing signal reproducing means for outputting a pulse signal as a reproducing horizontal synchronizing signal, a clock oscillator for generating and outputting a clock signal, and dividing the clock signal output by the clock oscillator A horizontal synchronizing signal cycle address indicating a time timing within one line period repeated every horizontal synchronizing signal cycle, and a vertical synchronizing signal cycle address indicating a time timing within one field period repeated every vertical synchronizing signal cycle; And an integration circuit that integrates and outputs a signal output from the narrowband filter circuit over a horizontal synchronization signal period according to a horizontal synchronization signal period address output from the frequency divider, The timing at which the maximum integrated value output by the integration circuit is obtained is detected, and the pulse is detected at that timing. The reproduction is characterized by having a vertical synchronizing signal reproducing means for outputting a vertical synchronizing signal, stable reproduction horizontal synchronization signal and outputs the reproduced vertical synchronizing signal No..
[0028]
The narrowband filter circuit has a downsampling circuit that thins out the input NTSC inverted signal to reduce the data rate, and a filter characteristic that allows the synchronization pulse component to pass. A narrow-band filter circuit having a narrow-band filter that passes and outputs components is preferable from the viewpoint of suppressing an increase in circuit scale.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described with reference to the drawings.
The synchronization signal regeneration circuit according to the embodiment of the present invention receives an NTSC inverted signal in which an interference wave exists and a horizontal synchronization pulse is embedded in the video signal, and is unnecessary other than the horizontal synchronization pulse. The timing at which the maximum value of the signal is obtained by detecting the maximum value of the signal after removing the equalization pulse component from the signal after removing the signal and extracting the horizontal synchronization pulse and removing the unnecessary signal. In addition to outputting the reproduction horizontal sync signal, the signal at the stage where unnecessary signals other than the horizontal sync pulse are removed is integrated over one horizontal sync period, and the reproduction vertical sync signal is output at the timing when the result of the integration becomes maximum. Even when there is an interference wave, it is possible to output a stable reproduction horizontal synchronization signal and reproduction vertical synchronization signal.
[0031]
A synchronization signal regeneration circuit (this circuit) according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of this circuit.
As shown in FIG. 1, this circuit has a narrowband filter circuit 11 as means for removing signals other than the horizontal synchronization signal from the NTSC inverted signal, and an equalized pulse component from the signal output from the narrowband filter circuit 11. Horizontal synchronization as means for detecting equalization pulse removal circuit 12 as means for removing and timing at which the signal output from equalization pulse removal circuit 12 becomes maximum, and reproducing and outputting a horizontal synchronization signal at that timing A signal regeneration means 13; a clock oscillator 14 for generating and outputting a clock signal; a clock signal output from the clock oscillator 14; and a horizontal synchronizing signal period address that makes one round in a horizontal synchronizing signal period; A frequency divider 15 as a means for outputting a vertical synchronizing signal cycle address that makes one round in a signal cycle and a signal output from the narrowband filter circuit 11 are constant. An integration circuit 16 as means for integrating over time, and a vertical synchronization signal as means for detecting a timing at which the integration result output from the integration circuit 16 is maximized, and reproducing and outputting the vertical synchronization signal at the timing. The reproducing unit 17 is mainly configured.
[0032]
The horizontal synchronizing signal reproducing means 13 is composed of a horizontal synchronizing position detecting circuit 31 and a coincidence detector 32. The vertical synchronizing signal reproducing means 17 is composed of a vertical synchronizing position detecting circuit 71, a coincidence detector 72, and the like. It is composed of
[0033]
Here, the outline of the signal flow of each part will be described. The clock signal output from the clock oscillator 14 is output to the frequency divider 15, and the frequency divider 15 is reset to “0” in the horizontal synchronization signal cycle. Address value (horizontal synchronization signal cycle address) is generated and output to the horizontal synchronization signal reproduction means 13 and the integration circuit 16, and the address value (vertical synchronization signal cycle) is reset to “0” in the vertical synchronization signal cycle. Address) is generated and output to the vertical synchronizing signal reproducing means 17.
[0034]
On the other hand, the NTSC inverted signal is filtered by the narrowband filter circuit 11, and further, the equalization pulse removal circuit 12 removes a pulse signal having a timing different from the horizontal synchronization signal timing, and outputs it to the horizontal synchronization signal reproduction means 13, thereby generating The synchronization signal reproduction means 13 reproduces and outputs the horizontal synchronization signal.
[0035]
The signal filtered by the narrowband filter circuit 11 is integrated over the period of the horizontal synchronizing signal by the integrating circuit 16, and the vertical synchronizing signal reproducing means 17 reproduces the vertical synchronizing signal based on the result of the integration. Output.
[0036]
Hereafter, each part of this circuit is demonstrated concretely.
The narrow-band filter circuit 11 is a low-pass filter having a filter characteristic for removing unnecessary signals other than the sync pulse component from the NTSC inverted signal, and specifically has a configuration as shown in FIG. FIG. 2 is a configuration block diagram showing an example when the narrowband filter circuit 11 is realized by a digital circuit.
In the following description, the narrow band filter circuit 11 is configured to receive an NTSC inverted signal.
[0037]
As shown in FIG. 2, the narrowband filter circuit 11 is input from the LPF 41 and a low-pass filter (LPF) 41 that performs band limitation so that spectrum overlap does not occur due to aliasing prior to the thinning process in the downsampling circuit 42. A down-sampling circuit 42 that reduces the data rate by thinning out the signal to be received, and a low-pass filter having a filter characteristic that removes unnecessary signals other than the synchronization pulse component. The down-sampling circuit 42 reduces the data rate. The signal corresponding to the value “0” is inserted between the narrowband filter 43 that receives the received NTSC inverted signal and removes unnecessary signals other than the sync pulse component, and the signal that the narrowband filter 43 outputs. The signal is output at the data rate before the downsampling circuit 42 decreases That the up-sampling circuit 44, and a corresponding up-sampling circuit 44 Metropolitan interpolation filter 45 outputs by performing an interpolation of the signal to be output.
[0038]
Here, the down-sampling circuit 42 of the narrowband filter circuit 11 outputs a signal only once per 8 signal inputs, for example, when the data rate of the input signal is 4 fsc (4 times the color subcarrier frequency). The data rate is reduced to (1/2) fsc by thinning out the signal to about one-eighth.
[0039]
Further, the upsampling circuit 44 inserts a signal corresponding to seven values “0” between signals input at a cycle of (1/2) fsc, and outputs a signal at a cycle of 4 fsc. Is.
[0040]
Accordingly, since the output signal of the upsampling circuit 44 includes the aliasing component generated by the thinning process in the downsampling circuit 42, the aliasing component may be removed by the interpolation filter 45.
[0041]
Note that the narrowband filter circuit 11 performs processing after reducing the data rate and then returning the data rate to the original value when the desired filter characteristics are obtained by the digital filter without reducing the data rate. This is because the circuit scale may increase and the increase in the circuit scale is suppressed.
[0042]
That is, when digitally processing an NTSC signal, it is normal to perform processing at a data rate about four times the color subcarrier signal frequency (fsc), that is, about 14.318 MHz. On the other hand, when trying to realize a narrow-band filter with a pass band of 100 kHz or less and a sharp cutoff characteristic, the ratio between the sampling frequency and the filter pass bandwidth is too large, increasing the tap length and coefficient bit length of the digital filter. This increases the circuit scale.
[0043]
Next, the narrow band filter 43 performs a filtering process. The narrow band filter 43 may be an FIR filter, an IIR filter, or the like.
Then, the upsampling circuit 44 upsamples the sampling frequency from 1/2 of 1 fsc to 4 times of 1 fsc, for example, by inserting a signal corresponding to the value “0” between the signals.
[0044]
After upsampling, the interpolation filter 45 removes the aliasing component and extracts only the necessary signal component. If the required accuracy of the reproduction signal phase may be a coarse accuracy of 1/2 or more of 1 fsc, the upsampling circuit 44 and the interpolation filter 45 may not be provided.
[0045]
The equalization pulse removal circuit 12 is a 1 horizontal synchronizing signal cycle recursive filter, and has an equalization pulse transmitted at a half cycle of the horizontal synchronizing signal cycle at a timing different from the horizontal synchronizing signal timing. The pulse is removed.
As shown in FIG. 3, the equalization pulse removal circuit 12 is a constant that is a factor that determines the frequency characteristics of the adder 46, the one-line delay unit 47, the multiplier 48, and the filter of the equalization pulse removal circuit 12. And a constant generator 49 for generating and outputting a signal corresponding to (constant signal). The constant output from the constant generator 49 is a value smaller than 1.0. FIG. 3 is a configuration block diagram illustrating an example of the equalization pulse removal circuit 12.
[0046]
Here, the adder 46 adds the signal output from the narrowband filter circuit 11 and the signal output from the multiplier 48 and outputs the result to the one-line delay unit 47.
The 1-line delay unit 47 delays the signal input from the adder 46 by one line period, outputs the delayed signal to the multiplier 48, and outputs it to the outside as the output signal of the equalization pulse removing circuit 12. is there.
Specifically, the 1-line delay unit 47 can be realized by a shift register, a line memory, or the like.
[0047]
Further, the multiplier 48 multiplies the constant signal output from the constant generator 49 and the signal output from the one-line delay unit 47 and outputs the result to the adder 46.
[0048]
The horizontal synchronizing signal reproducing means 13 detects the timing at which the maximum value of the level of the output signal of the equalization pulse removing circuit 12 is obtained, and outputs the timing information as a reproducing horizontal synchronizing signal.
Specifically, the horizontal synchronizing signal reproduction means 13 is used for the horizontal synchronizing signal cycle address input from the frequency divider 15 described later at the time when the level of the signal output from the equalization pulse removing circuit 12 is maximum. The horizontal synchronization position detection circuit 31 that detects and outputs the address value compares the address value input from the horizontal synchronization position detection circuit 31 with the address value of the horizontal synchronization signal cycle address input from the frequency divider 15. The coincidence detector 32 outputs a pulse as a reproduction horizontal synchronization signal at the timing when both coincide.
[0049]
Here, the horizontal synchronization position detection circuit 31 includes the maximum value of the signal output from the equalization pulse removal circuit 12, and the horizontal synchronization signal cycle address input from the frequency divider 15 when the maximum value is obtained. Are stored in association with each other, and the stored value is reset every horizontal synchronization period.
[0050]
That is, it is conceivable that the horizontal synchronization position detection circuit 31 is, for example, as shown in FIG. FIG. 4 is a configuration block diagram illustrating an example of the configuration of the horizontal synchronization position detection circuit 31.
The horizontal synchronization position detection circuit 31 shown in FIG. 4 basically includes a comparator 51, a level maximum value data register 52, and a level maximum value address register 53.
[0051]
Here, the comparator 51 receives the input of the signal (a) output from the equalization pulse removal circuit 12 and the signal (hereinafter referred to as “stored value”) (b) stored in the level maximum value data register 52. The result is compared and the result of magnitude determination (c) is output. When (a) is larger than (b), (c) is output as enabled, and (a) is more than (b). When it is small, (c) is output as disabled.
[0052]
When the comparator 51 outputs enable as the magnitude determination result (c), the level maximum value data register 52 stores the signal (a) output from the equalization pulse removal circuit 12 at the time as a new storage value (b). To do.
Further, the level maximum value data register 52 holds the stored value (b) held at that time as it is while the comparator 51 outputs disable as the magnitude determination result (c). .
[0053]
When the comparator 51 outputs enable as the magnitude determination result (c), the level maximum value address register 53 stores the address value (d) of the horizontal synchronizing signal cycle address output by the frequency divider 15 at the time. Is.
Further, the level maximum value address register 53 holds the stored value (e) of the address held at that time as it is while disabling is output as the magnitude determination result (c).
[0054]
Further, the horizontal synchronizing signal cycle address returns to its original value even after one round of every horizontal synchronizing signal cycle. The level maximum value data register 52 and the level maximum value address register 53 are divided by a frequency divider. Each time the address value (d) of the horizontal synchronizing signal cycle address input from 15 makes a round (every horizontal synchronizing signal cycle), each stored value is reset to “0”.
[0055]
Specifically, a method of determining whether or not the address value (d) has made a round can be determined by detecting the timing at which the MSB (MostSignificantBit) of the address value rises.
[0056]
In other words, the horizontal synchronization position detection circuit 31 detects the maximum value of the signal output from the equalization pulse removal circuit 12 for each horizontal synchronization signal period by the action of the comparator 51 and the level maximum value data register 52, and also separates them. The level maximum value address register 53 stores the address value of the horizontal synchronization cycle address output from the frequency divider 15 and outputs it to the coincidence detector 32 as the timing of the horizontal synchronization signal.
[0057]
The clock oscillator 14 is an oscillator that generates a clock signal.
The frequency divider 15 generates an address (horizontal synchronization signal cycle address) that is reset to “0” in the horizontal synchronization signal cycle based on the clock signal input from the clock oscillator 14 and the horizontal synchronization signal regeneration means 13 and the integration circuit. 16 and an address (vertical synchronization signal cycle address) that is reset to “0” in the vertical synchronization signal cycle is output to the vertical synchronization signal reproduction means 17.
[0058]
The integrating circuit 16 integrates the output signal from the narrow band filter circuit 11.
The integration circuit 16 outputs an integration value in the horizontal synchronization signal period and resets the integration value in accordance with the horizontal synchronization signal period address output from the frequency divider 15.
[0059]
Specifically, it is conceivable that the integrating circuit 16 is as shown in FIG. FIG. 5 is a block diagram illustrating an example of the integration circuit 16.
For example, as shown in FIG. 5, the integration circuit 16 integrates the output signal from the narrowband filter circuit 11, stores an integrator 61 that outputs an integration value, and a signal output from the integrator 61, and And a register 62 for outputting to the main.
[0060]
Here, the integrator 61 refers to the horizontal synchronizing signal cycle address output from the frequency divider 15, for example, detects the rising edge of the MSB, clears the integration value to “0”, and performs integration again. It will be done. Therefore, the integrator 61 repeats the integration calculation and clear in the horizontal synchronization signal cycle.
[0061]
Similarly to the integrator 61, the register 62 refers to the horizontal synchronization signal cycle address output from the frequency divider 15 and performs integration at a timing immediately before the integrator 61 clears the integration value to “0”. The integral value 61 is held and output to the vertical synchronizing signal reproducing means 17.
[0062]
The vertical synchronizing signal reproducing means 17 detects the timing at which the maximum integrated value output from the integrating circuit 16 is obtained, and outputs the timing information as a reproducing vertical synchronizing signal.
[0063]
Specifically, the vertical synchronization signal reproducing means 17 is composed of a vertical synchronization position detection circuit 71 and a coincidence detector 72 as shown in FIG.
Here, the vertical synchronization position detection circuit 71 detects and outputs the address value of the vertical synchronization signal cycle address at the time when the integration value output from the integration circuit 16 becomes maximum.
Further, the coincidence detector 72 compares the address value input from the vertical synchronization position detection circuit 71 with the address value of the vertical synchronization signal cycle address input from the frequency divider 15, and at a timing when they match. A pulse as a reproduction vertical synchronizing signal is output.
[0064]
The vertical synchronization position detection circuit 71 detects the maximum value of the signal level output from the integration circuit 16 every vertical synchronization signal period in accordance with the horizontal synchronization signal period address input from the frequency divider 15. ing.
That is, the vertical synchronization position detection circuit 71 repeats detection of the maximum value every vertical synchronization signal period.
[0065]
Specifically, as shown in FIG. 6, the vertical synchronization position detection circuit 71 basically includes a comparator 56, a level maximum value data register 57, and a level maximum value address register 58. Can be considered. FIG. 6 is a configuration block diagram illustrating an example of the vertical synchronization position detection circuit 71.
[0066]
Here, the comparator 56 receives and compares the signal (a) output from the integrating circuit 16 and the signal (b) stored in the level maximum value data register 57, and compares the magnitude determination result (c). When (a) is larger than (b), the magnitude determination result (c) is output as enabled, and when (a) is smaller than (b), the magnitude determination result ( c) is output as disabled.
[0067]
The level maximum value data register 57 stores the signal (a) output from the integration circuit 16 at that time as a new stored value (b) when the comparator 56 outputs the magnitude determination result (c) as enabled. is there.
The level maximum value data register 57 holds the stored value (b) held at that time while the comparator 56 outputs disable as the magnitude determination result (c). .
[0068]
When the comparator 56 outputs enable as the magnitude determination result (c), the level maximum value address register 58 stores the address value (d) of the vertical synchronization signal cycle address output by the frequency divider 15 at the time. Is.
The level maximum value address register 58 holds the stored value (e) of the address held at that time while the comparator 56 outputs disable as the magnitude determination result (c). It is.
[0069]
Further, the vertical synchronizing signal cycle address returns to its original value even after one round of every vertical synchronizing signal cycle. The level maximum value data register 57 and the level maximum value address register 58 are divided by a frequency divider. Each time the address value (d) of the vertical synchronization signal cycle address input from 15 completes a cycle (every vertical synchronization signal cycle), each stored value is reset to “0”.
[0070]
Specifically, a method of determining whether or not the address value (d) has made a round can be determined by detecting the timing at which the MSB of the address value rises.
[0071]
That is, the vertical synchronization position detection circuit 71 detects the maximum value of the signal output from the integration circuit 16 for each vertical synchronization signal period by the action of the comparator 56 and the level maximum value data register 57, and the frequency divider 15 The level maximum value address register 58 stores the address value of the vertical synchronizing signal cycle address output from the signal and outputs it to the coincidence detector 72 as the timing of the vertical synchronizing signal.
[0072]
Here, since the normal NTSC modulation wave is negative modulation and the output signal of the detection circuit is the NTSC inverted signal, the circuit for reproducing the horizontal and vertical synchronization signals from the NTSC inverted signal has been described. A circuit for reproducing horizontal and vertical synchronizing signals from the NTSC signal itself instead of the NTSC inverted signal can be configured in the same manner as the circuit shown in FIG.
[0073]
That is, in this case, the horizontal synchronization position detection circuit 31 detects not the maximum value for each horizontal synchronization signal period but the minimum value for each horizontal synchronization signal period and the horizontal synchronization signal period address from which the minimum value is obtained. The vertical synchronization position detection circuit 71 detects not the maximum value for each vertical synchronization signal period but the minimum value for each vertical synchronization signal period and the vertical synchronization signal period address from which the minimum value is obtained. Just keep it.
[0074]
Next, with regard to the operation of this circuit, specifically, the case where the horizontal and vertical synchronization signals are reproduced based on the NTSC inverted signal having an interference wave frequency of 150 kHz and a desired wave interference wave power ratio d / u = 0 dB. This will be described as an example.
In general, the NTSC inverted signal is obtained by alternately arranging vertical blanking periods and video signal periods. Here, in the video signal period, the outline of the signal waveform for each horizontal synchronization signal period has already been described. Further, it is as shown in FIG.
[0075]
In one horizontal sync signal period, the NTSC inverted signal is composed of a horizontal sync pulse, a subsequently transmitted color burst (a signal for reproducing a color subcarrier), and a subsequent video signal. The horizontal synchronization pulse is originally received as a signal having the highest level.
[0076]
However, in the case of an NTSC inverted signal with an interference wave frequency of 150 kHz and a desired wave interference wave power ratio d / u = 0 dB, as shown in FIGS. 7A and 7B, the horizontal synchronization indicated by circles in the figure. A signal portion in which the level of the other video signal becomes larger than the pulse can be seen. FIG. 7 is an explanatory diagram showing an example of the NTSC inverted signal when there is an interference wave.
[0077]
As described above, the narrowband filter circuit 11 of the present circuit attenuates signal components other than the horizontal synchronization pulse even in the NTSC inverted signal in which the horizontal synchronization pulse is buried in the video signal due to the influence of the interference wave. Since it has frequency characteristics, most of the unnecessary signal portion disappears, and the horizontal synchronization pulse is output as a mainly remaining signal.
[0078]
That is, the signal waveform after passing through the narrowband filter circuit 11 of this circuit is as shown in FIG. As shown in the figure, the signal waveform output from the narrowband filter circuit 11 is equalized when a signal other than the horizontal synchronizing pulse is almost eliminated (section (a) in the figure) and in the vertical blanking period. The case where a component is mixed (section (b) in the figure) may be mixed. FIG. 8 is an explanatory diagram illustrating an example of a signal waveform after passing through the narrowband filter 11 of the present circuit.
When equalization pulse components are mixed in this way, the pulses indicated by c and e in the figure are horizontal synchronization pulses, whereas pulses d and f of the same level are present. The horizontal sync signal cannot be played correctly.
[0079]
Therefore, the equalization pulse removal circuit 12 operates to remove the equalization pulse component and output a signal to the horizontal synchronization signal reproduction means 13.
The frequency characteristics of the equalization pulse removal circuit when the constant generator 49 of the equalization pulse removal circuit 12 outputs the constant “0.9” are as shown in FIG. FIG. 9 is an explanatory diagram illustrating an example of frequency characteristics of the equalization pulse removal circuit 12.
[0080]
Since the frequency characteristics as shown in FIG. 9 are provided, the equalization pulse removal circuit 12 passes a signal corresponding to an integral multiple of the horizontal synchronization frequency, but the equalization pulse component existing only in the vertical blanking period is horizontal. Since there are many frequency components other than an integral multiple of the synchronization frequency, the frequency is attenuated.
[0081]
Thus, the waveform of the signal output from the equalization pulse removal circuit 12 is as shown in FIG. FIG. 10 is an explanatory diagram illustrating an example of a signal waveform output from the equalization pulse removal circuit 12.
As shown in FIG. 10, in the signal output from the equalization pulse removal circuit 12, since the equalization pulse component is attenuated, only the horizontal synchronization pulse appears as a signal having a peak.
[0082]
Then, the horizontal synchronizing signal reproducing means 13 detects the position where the peak of the signal is detected, and outputs a pulse signal as a reproducing horizontal synchronizing signal at the position.
[0083]
On the other hand, the integration circuit 16 integrates the signal including the equalization pulse that has passed through the narrow band filter circuit 11 over one horizontal synchronization period, and the vertical synchronization signal regeneration means 17 detects the timing when the integration value becomes maximum. At this timing, a pulse signal is output as a reproduction vertical synchronization signal.
[0084]
Here, the operation of the horizontal synchronizing signal reproducing means 13 will be described more specifically with reference to FIG. FIG. 11 is a timing chart showing a specific operation of the horizontal synchronizing signal reproducing means 13.
[0085]
In the following description, the case where the horizontal synchronizing signal reproducing means 13 is realized by a digital circuit is described in mind. Therefore, when the equalization pulse removing circuit 12 is an analog circuit, FIG. It is necessary to separately generate a clock signal as shown in A), A / D-convert the output of the equalization pulse removal circuit 12 at each timing of the clock signal, and then output it to the horizontal synchronizing signal reproduction means 13.
If the equalization pulse removal circuit 12 is a digital circuit, a signal may be output at every timing of the clock signal.
[0086]
First, the stored value (b) of the level maximum value data register 52 is reset to “0” at the timing of the rising edge (m) of the MSB (FIG. 11E) of the horizontal synchronizing signal cycle address.
At this time, as shown in FIG. 11F, the horizontal synchronization signal cycle address (d) output by the minute cycle 15 is “3”.
[0087]
At the next clock timing, the signal (a) (FIG. 11B) output from the equalization pulse removal circuit 12 is input to the comparator 51, and the value of (a) (here, “6C”) is the level. It is compared with the stored value (b) of the maximum value data register 52 (FIG. 11C).
[0088]
At this time, since the stored value (b) of the level maximum value data register 52 is already cleared “0”, “a> b”, and the magnitude determination result (hereinafter referred to as “update signal”). (C) is enabled (H level in the figure).
[0089]
Then, the level maximum value data register 52 latches the signal (a), and the stored value (b) becomes the value “6C” as shown in FIG.
[0090]
On the other hand, since the update signal (c) is enabled, the level maximum value address register 53 latches the horizontal synchronizing signal cycle address (d) input from the frequency divider 15 and stores the stored value (e) (FIG. 11 (G)) becomes the value “4”.
[0091]
Thereafter, the same operation is repeated, but the value “6C” of the stored value (b) is the value of the signal a output from the equalization pulse removing circuit 12 until the fifth clock timing is reached after the reset. Since the values are larger than “60”, “67”, and “63”, the update signal c output from the comparator 51 remains disabled (L level), and the level maximum value data register 52 receives a new signal. The value “6C” of the stored value (b) is held without latching.
Similarly, the level maximum value address register 53 does not latch, and the value “4” of the stored value (e) is held.
[0092]
Then, at the fifth clock timing, the signal a output from the equalization pulse removal circuit 12 becomes the value “ED”, and the value “6C” of the stored value (b) of the level maximum value data register 52 at that time Since it is large, the update signal c output from the comparator 51 is enabled.
[0093]
Then, the level maximum value data register 52 latches the value “ED”, and the stored value (b) becomes “ED”.
Similarly, the level maximum value address register 53 latches the value “8” of the horizontal synchronization signal cycle address (d) and updates the stored value e to “8”.
[0094]
Thereafter, in the same manner, in FIG. 11, the final stored value (b) of the level maximum value data register 52 is “FD”, and the stored value (e) of the level maximum value address register 53 is “2F”. It has become.
Then, the level maximum value address register 53 outputs “2F” of the stored value (e) to the coincidence detector 32 at the timing of the rising edge (m + 1) of the next horizontal synchronizing signal cycle address MSB.
[0095]
Accordingly, the coincidence detector 32 outputs a pulse indicating that the horizontal synchronization signal cycle address inputted from the frequency divider 15 coincides at a timing when it becomes “2F” as a reproduction horizontal synchronization signal.
[0096]
Here, the operation of the integrating circuit 16 will be described more specifically with reference to FIG. FIG. 12 is a timing chart showing a specific operation of the integration circuit 16.
Here, the case where the integrating circuit 16 is realized by a digital circuit is described in mind, so that when the narrowband filter circuit 11 is an analog circuit, a clock signal as shown in FIG. It is necessary to separately generate and A / D convert the output of the narrowband filter circuit 11 at every timing of the clock signal, and then output it to the integrating circuit 16.
If the narrowband filter circuit 11 is a digital circuit, the integration circuit 16 may receive the signal input at each timing of the clock signal.
[0097]
First, the integrator 61 of the integrating circuit 16 detects the MSB rising edge (m in FIG. 12D) of the horizontal synchronization cycle address from the frequency divider 15 and clears the integrated value to “0” at that timing. (FIG. 12C).
At this time, the register 62 holds the integration value (“f6” in FIG. 12) immediately before the integrator 61 is cleared to “0”.
[0098]
Then, at the next clock timing (“1” in FIG. 12A), the signal (FIG. 12B) “1C” output from the narrowband filter circuit 11 and the integral value “0” at that time point The integrator 61 stores the addition result 0 + 1C = 1C as an integration value at the timing.
Further, at the clock timing of “1”, the horizontal synchronization signal cycle address MSB does not rise, so the register 62 does not update the stored value and remains “F6”.
[0099]
Then, at the next clock timing (clock timing “2”), the signal “05” input from the narrowband filter circuit 11 and the integration value “1C” at that time are added, and the addition result (1C + 05) = 21) is stored in the integrator 61 as an integral value.
[0100]
In the same manner, addition and storage are repeated until the nth clock timing. In FIG. 12, the stored value stored in the integrator 61 at the time of the nth clock timing is “FB”.
In FIG. 12, at this time, the timing of the rising edge (m + 1) of the MSB of the horizontal synchronization signal cycle address is reached, the integrator 61 clears the integration value “0”, and the register 62 stores The integral value “FB” immediately before “0” is cleared is stored.
[0101]
That is, the integration circuit 16 outputs the integration value to the vertical synchronization position detection means 17 in synchronization with the rising edge of the MSB of the horizontal synchronization signal cycle address.
[0102]
Here, the operation of the vertical synchronizing signal reproducing means 17 will be described more specifically with reference to FIG. FIG. 13 is a timing chart showing a specific operation of the vertical synchronizing signal reproducing means 17.
[0103]
Here, the case where the vertical synchronizing signal reproducing means 17 is realized by a digital circuit is described in mind, so that when the narrowband filter circuit 11 and the integrating circuit 16 are analog circuits, FIG. It is necessary to separately generate a clock signal as shown in FIG. 5 and A / D-convert the output of the integration circuit 16 at each timing of the clock signal before outputting it to the vertical synchronization signal reproducing means 17.
When the integrating circuit 16 is a digital circuit, it is only necessary to receive a signal input from the integrating circuit 16 at each timing of the clock signal.
[0104]
First, the level maximum value data register 57 clears the stored value to “0” at the timing of the MSB of the vertical synchronization signal cycle address (the rising edge (m) in FIG. 13E).
Further, the comparator 56 receives the input of the signal (a) (FIG. 13B) from the integration circuit 16 in synchronization with the clock signal shown in FIG. 13A, and the timing (clock timing “1”). Then, the signal is compared with the signal output from the level maximum value data register 57.
[0105]
Then, the value output by the integration circuit 16 at the clock timing “1” (“FB” in FIG. 13B) is compared with the value (b) stored in the level maximum value data register 57. It will be.
At this time, the stored value (b) of the level maximum value data register 57 is cleared to “0” at the clock timing of “1”, so that “a> b” is determined and the comparator 56 is determined. Outputs an enable signal (H level in FIG. 13D) as the update signal (c).
Then, the level maximum value data register 57 latches the signal input from the integration circuit 16 and updates the stored value (b) to “FB”.
[0106]
On the other hand, the level maximum value address register 58 receives the enable update signal (c) from the comparator 56, latches the vertical synchronization signal cycle address (d) input from the frequency divider 15, and divides the frequency at that time. “2” of the value (FIG. 13 (F)) output by the device 15 is stored as the stored value (e).
[0107]
Thereafter, at the clock timings “2” to “4”, the comparator 56 stores the value “fb” stored therein and the value output from the integrator 16 (“F6”, “E8”, “DF” in FIG. 13 respectively). And the stored value (b) of the level maximum value data register 57 is larger than the input value (a), so that the update signal (c) is disabled (L level). )
[0108]
Accordingly, the level maximum value data register 57 does not latch, the value “FB” of the stored value (b) is held as it is, and the level maximum value address register 58 also does not latch, so that the stored value (e) The value “2” remains held.
[0109]
Hereinafter, the same operation is performed, but in FIG. 13, the value of the signal (a) output from the integration circuit 16 at the clock timing of “5” becomes “10A” of three digits, and the level maximum value data register at that time Since the stored value (b) of 57 becomes larger than “FB”, the comparator 56 outputs an enable update signal (c), and the level maximum value data register 57 outputs the integration circuit 16 at that time. The value “10a” is latched, and the stored value (b) is set to “10a”.
Similarly, the level maximum value address register 58 latches the vertical synchronizing signal cycle address (d) at that time, and the stored value (e) becomes the value “6”.
[0110]
Thereafter, the comparison operation in the comparator 56 and the latch in the level maximum value data register 57 and the level maximum value address register 58 are repeated.
In the example of FIG. 13, the stored value (b) of the level maximum value data register 57 is finally “2AC”, and the stored value (e) of the level maximum value address register 58 is “88”.
[0111]
The final stored value (e) of the level maximum value address register 58 is output to the coincidence detector 72 at the timing of the rising edge (m + 1) of the MSB of the vertical synchronization signal cycle address (d). However, the coincidence pulse is output as the vertical synchronization reproduction signal at the timing when the vertical synchronization signal cycle address input from the frequency divider 15 becomes “88”.
[0112]
As described above, according to the present circuit, even when an interference wave is mixed in the reception signal of the television broadcast wave, the narrowband filter circuit 11 sufficiently removes the interference wave component, and the equalization pulse removal circuit 12 is equalized. The horizontal synchronization signal regeneration means 13 in the subsequent stage detects the maximum value of the signal output from the equalization pulse removal circuit 12 to regenerate the horizontal synchronization signal, and the integration circuit 16 The vertical synchronization signal is reproduced by integrating the signal output from the narrowband filter circuit 11 and having sufficiently attenuated the interference wave component, so that the vertical synchronization signal can be reliably detected.
In addition, there is an effect that the threshold judgment circuit according to the level of the received video signal does not require high-precision adjustment of the threshold, the circuit configuration can be made relatively simple, and the circuit scale can be reduced.
[0113]
【The invention's effect】
Book According to the invention, In a synchronous signal reproduction circuit that outputs a desired reproduction horizontal synchronization signal and reproduction vertical synchronization signal regardless of the presence or absence of interference waves due to the influence of the sporadic E layer, Even when interference signals are mixed in the reception signal of TV broadcast waves, the narrowband filter circuit sufficiently removes the interference wave components, and the equalization pulse removal circuit removes the equalization pulse components before the horizontal synchronization signal. The reproduction means detects the maximum value of the signal output from the equalization pulse removal circuit and reproduces the horizontal synchronization signal, and the integration circuit sufficiently attenuates the interference wave component output from the narrowband filter circuit. , And the sync signal recovery circuit that recovers the vertical sync signal by detecting the maximum value of the integrated value so that the timing of the horizontal sync signal and the timing of the vertical sync signal can be detected reliably and stable. The reproduced horizontal synchronizing signal and the reproduced vertical synchronizing signal can be output.
[0114]
Also, Book As in the invention, when the narrowband filter circuit is a narrowband filter circuit that performs filtering that allows the synchronization pulse component to pass after the data rate is once reduced, the circuit is realized when the narrowband filter circuit is realized as a digital circuit. There is an effect that the scale can be reduced.
[Brief description of the drawings]
FIG. 1 is a configuration block diagram of this circuit.
FIG. 2 is a configuration block diagram showing an example of a case where the narrowband filter circuit 11 is realized by a digital circuit.
FIG. 3 is a configuration block diagram showing an example of an equalization pulse removal circuit 12;
4 is a configuration block diagram illustrating an example of a configuration of a horizontal synchronization position detection circuit 31. FIG.
FIG. 5 is a configuration block diagram illustrating an example of an integration circuit 16;
6 is a configuration block diagram illustrating an example of a vertical synchronization position detection circuit 71. FIG.
FIG. 7 is an explanatory diagram showing an example of an NTSC inverted signal when there is an interference wave.
FIG. 8 is an explanatory diagram showing an example of a signal waveform after passing through the narrowband filter 11 of the present circuit.
FIG. 9 is an explanatory diagram showing an example of frequency characteristics of the equalization pulse removal circuit 12;
FIG. 10 is an explanatory diagram showing an example of a signal waveform output from the equalization pulse removal circuit 12;
11 is a timing chart showing a specific operation of the horizontal synchronizing signal reproducing means 13. FIG.
12 is a timing chart illustrating specific operations of the integration circuit 16. FIG.
FIG. 13 is a timing chart showing a specific operation of the vertical synchronizing signal reproducing means 17;
FIG. 14 is a block diagram showing a configuration example of a conventional synchronization signal regeneration circuit.
FIG. 15 is an explanatory diagram illustrating an example of a schematic waveform of a video signal period in an NTSC inverted signal.
FIG. 16 is an explanatory diagram showing an example of a schematic waveform of a vertical blanking period in an NTSC inverted signal.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Narrow-band filter circuit, 12 ... Equalization pulse removal circuit, 13 ... Horizontal synchronizing signal reproduction | regeneration means, 14 ... Clock oscillator, 15 ... Frequency divider, 16 ... Integration circuit, 17 ... Vertical synchronizing signal reproduction | regeneration means, 21 ... Sink Chip clamp circuit, 22... First threshold value judgment circuit, 23... First one-shot gate circuit, 24... Integrator, 25 ... Second threshold value judgment circuit, 26. 31 ... Horizontal synchronization position detection circuit, 32 ... Match detector, 41 ... LPF, 42 ... Downsampling circuit, 43 ... Narrow band filter, 44 ... Upsampling circuit, 45 ... Interpolation filter, 51, 56 ... Comparator, 52 , 57 ... level maximum value data register, 53, 58 ... level maximum value address register, 71 ... vertical synchronization position detection circuit, 72 ... coincidence detector

Claims (10)

A synchronization signal reproduction circuit that outputs a desired reproduction horizontal synchronization signal and reproduction vertical synchronization signal regardless of the presence or absence of interference waves due to the influence of the sporadic E layer,
Narrow band with filter characteristics for removing unnecessary signal parts other than the sync pulse components of horizontal and vertical sync signals including equalization pulses from the input NTSC inverted signal and outputting them as signals in which the horizontal sync pulse components mainly remain A filter circuit;
The signal output from the narrowband filter circuit is added with the output signal and a one-line delayed signal delayed by a period of one horizontal synchronizing signal period, and the period is one half of the horizontal synchronizing signal period. An equalization pulse removal circuit that passes only the equalization pulse component of the same timing as the horizontal synchronization signal among the components of the equalization pulse transmitted intermittently;
Horizontal sync signal reproduction that detects the timing of the peak point where the maximum value of the level of one line period of the signal waveform output from the equalization pulse removal circuit is obtained, and outputs the pulse signal as a reproduction horizontal synchronization signal at the timing Means,
A clock oscillator that generates and outputs a clock signal; and
The clock signal output from the clock oscillator is divided and a horizontal synchronization signal period address indicating a time timing within one line period repeated every horizontal synchronization signal period, and within one field period repeated every vertical synchronization signal period A frequency divider that outputs a vertical synchronizing signal period address indicating the time timing of
An integration circuit that integrates and outputs a signal output from the narrowband filter circuit over a horizontal synchronization signal period in accordance with a horizontal synchronization signal period address output from the frequency divider;
A synchronizing signal reproducing circuit comprising: a vertical synchronizing signal reproducing means for detecting a timing at which a maximum integrated value output from the integrating circuit is obtained and outputting a pulse signal as a reproducing vertical synchronizing signal at the timing. A down-sampling circuit in which the narrowband filter circuit thins out the input NTSC inverted signal to reduce the data rate;
A narrowband filter circuit having a filter characteristic that removes unnecessary signal portions and allows a synchronization pulse component to pass, and a narrowband filter that outputs a signal in which the synchronization pulse component mainly remains from the signal output from the downsampling circuit. 2. The synchronizing signal reproducing circuit according to claim 1, wherein the synchronizing signal reproducing circuit is provided. The low-band filter circuit limits the band of the signal to prevent the spectrum from overlapping due to the folding of the spectrum caused by the thinning process prior to the thinning process of the input NTSC inverted signal with respect to the input NTSC inverted signal. Filters,
A downsampling circuit that performs a thinning process for thinning out the signal output by the low-pass filter, and lowers the data rate;
A narrowband filter circuit having a filter characteristic that removes an unnecessary signal portion and allows a synchronization pulse component to pass, and a narrowband filter that outputs a signal in which a synchronization pulse component mainly remains from a signal output from the downsampling circuit. 2. The synchronizing signal reproducing circuit according to claim 1, wherein the synchronizing signal reproducing circuit is provided. The low-band filter circuit limits the band of the signal to prevent the spectrum from overlapping due to the folding of the spectrum caused by the thinning process prior to the thinning process of the input NTSC inverted signal with respect to the input NTSC inverted signal. Filters,
A downsampling circuit that performs a thinning process for thinning out the signal output by the low-pass filter, and lowers the data rate;
A narrowband filter that has a filter characteristic that removes unnecessary signal portions and allows a synchronization pulse component to pass through, and outputs a signal in which the synchronization pulse component mainly remains from the signal output by the downsampling circuit;
An upsampling circuit that inserts a predetermined signal between signals input from the narrowband filter to increase the data rate;
2. The synchronous signal regeneration circuit according to claim 1, wherein the synchronous signal regeneration circuit includes an interpolation filter that interpolates and outputs a waveform of a signal output from the upsampling circuit. An equalization pulse removal circuit includes an adder, a one-line delay device, and a multiplier,
The adder is an adder that adds and outputs the signal output from the narrowband filter circuit and the signal output from the multiplier,
The one-line delay unit is a one-line delay unit that outputs a signal output from the adder after being delayed by a period of one horizontal synchronization signal period,
5. The equalization pulse elimination circuit as claimed in claim 1, wherein the multiplier is a multiplier for outputting a signal output from the one-line delay unit by multiplying a preset constant. The synchronizing signal reproduction circuit described. The horizontal synchronization signal period outputted by the frequency divider at the peak point timing at which the level of one line period of the signal waveform output from the equalization pulse removal circuit is maximum for each horizontal synchronization signal period. A horizontal synchronization position detection circuit that detects an address value and outputs the value;
Compares the address value output by the horizontal sync position detection circuit with the horizontal sync signal cycle address output by the frequency divider, and outputs a coincidence pulse as a playback horizontal sync signal when they match. 6. A synchronizing signal regeneration circuit according to claim 1, wherein said synchronizing signal regeneration means comprises a detector. The vertical sync signal reproducing means detects the value of the vertical sync signal cycle address output by the frequency divider at the timing at which the maximum value of the integral value output by the integration circuit is obtained for each horizontal sync signal cycle, and calculates the value. An output vertical synchronization position detection circuit;
Compare the value output from the vertical sync position detection circuit with the address value of the vertical sync signal cycle address output from the frequency divider, and output a match pulse as a playback vertical sync signal when they match. 7. A synchronizing signal reproducing circuit according to claim 1, wherein said synchronizing signal reproducing means has a coincidence detector. The horizontal synchronization position detection circuit includes a comparator, a level maximum value data register, and a level maximum value address register.
The comparator is a comparator that compares the signal output from the equalization pulse removal circuit with the stored value in the level maximum value data register and outputs the magnitude determination result as an update signal,
When the update signal is enabled, the level maximum value data register latches and stores the signal output from the equalization pulse removal circuit at the timing, and stores that the update signal is disabled. It is a level maximum value data register that holds the signal as it is, receives the input of the horizontal synchronization signal cycle address from the frequency divider, and clears the held signal for each horizontal synchronization cycle,
When the update signal is enabled, the level maximum value address register latches and stores the value of the horizontal synchronization signal cycle address output by the frequency divider at the timing, and when the update signal is disabled, 7. A synchronizing signal reproducing circuit according to claim 6, wherein the synchronizing signal reproducing circuit is a horizontal synchronizing position detecting circuit which is a level maximum value address register for holding a stored value as it is. An integrator that receives an input of a horizontal synchronizing signal cycle address output from the frequency divider, integrates a signal output from the narrowband filter circuit over the horizontal synchronizing signal cycle, and outputs an integrated value; ,
9. The synchronization circuit according to claim 1, further comprising a register that stores an integration value output by the integrator and clears a value stored in the horizontal synchronization signal period. Signal regeneration circuit. The vertical synchronization position detection circuit includes a comparator, a level maximum value data register, and a level maximum value address register.
The comparator is a comparator that compares the signal output from the integration circuit with the stored value in the level maximum value data register and outputs the magnitude determination result as an update signal;
When the update signal is enabled, the level maximum value data register latches and stores the signal output from the integration circuit at the timing. When the update signal is disabled, the level maximum value data register stores the stored signal as it is. It is a level maximum value data register that holds and receives the vertical sync signal cycle address input from the frequency divider and clears the held signal for each vertical sync signal cycle,
When the update signal is enabled, the level maximum value address register latches and stores the value of the vertical synchronization signal cycle address output by the frequency divider at the timing, and when the update signal is disabled, 8. A synchronizing signal reproducing circuit according to claim 7, wherein the synchronizing signal reproducing circuit is a vertical synchronizing position detecting circuit which is a level maximum value address register for holding a stored value as it is.

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