JP3741570B2 - Synchronous tracking circuit and communication device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a received signal tracking control (DLL: Delay Locked Loop) technique in CDMA (Code Division Multiple Access) communication.
[0002]
[Prior art]
The CDMA communication apparatus is provided with means for continuously tracking the synchronization position even after acquisition of synchronization in order to prevent the reception side spread code sequence from causing a time lag with respect to the reception signal that has been successfully acquired. A means for this is a synchronous tracking circuit. The synchronization tracking circuit operates so that the synchronization state is maintained by changing the phase of the spread code or changing the latch phase of the input data based on the tracking clock adjusted according to the detection result of the synchronization position. This operation is follow-up control (DLL).
[0003]
Hereinafter, the principle of the tracking control (DLL) operation used in the conventional apparatus will be described with reference to FIGS. 2 and 3. In the case of the conventional apparatus, the amount of change that can be phase-shifted by one follow-up control is limited to one type (fixed amount). For example, when the input data is oversampled data that has been oversampled at 8 times the chip rate, the synchronization tracking circuit performs the correlation power in the 1/2 chip advance phase of the current tracking phase and the correlation in the 1/2 chip delay phase. The phase change amount with respect to the follow-up clock is determined based on the comparison result between the correlation power difference, which is a difference value with respect to power, and the DLL threshold (FIG. 2).
[0004]
(1) (1 / 2Chip delayed correlation power)-(1 / 2Chip advanced correlation power)> DLL threshold
: Phase change amount = + 1 / 8Chip (FIG. 3A)
▲ 2 ▼ | (1 / 2Chip delayed correlation power) − (1 / 2Chip advanced correlation power) | ≦ DLL threshold
: Phase change amount = 0 (FIG. 3B)
(3)-{(1 / 2Chip delayed correlation power)-(1 / 2Chip advanced correlation power)}> DLL threshold
: Phase change amount = −1 / 8Chip (FIG. 3C)
[0005]
[Problems to be solved by the invention]
However, in the case of the conventional synchronous tracking circuit, even when the required phase change amount is 1/8 chip or more, the phase change amount that can be shifted in one control operation is limited to 1/8 chip. Therefore, the amount of change required in one control operation cannot be secured, and the control operation has to be repeated many times.
[0006]
[Means for Solving the Problems]
(A) In order to solve such a problem, the first inventionSynchronous tracking circuit(1) Phase change amount determining means for calculating correlation power for a plurality of front and rear phases including a synchronization phase and determining a difference between the phase giving the maximum value and the synchronization phase as a phase change amount with respect to the follow-up clock; and (2 ) Follow-up clock generating means for partially expanding and contracting the period of the follow-up clock generated according to the phase change amountWith (2) The following clock generating means is (2-1) A shift register that outputs the output of the first stage as the follow-up clock; and (2-2) Either a plurality of outputs given from each stage constituting the shift register unit or an operation output thereof is selected according to the phase change amount given from the phase change amount determining means, and this is sent to the first stage of the shift register unit A feedback input switching unit that partially expands and contracts the period of the follow-up clock. (2-2) The shift register unit includes a mask unit including a plurality of mask units provided between two adjacent stages constituting the shift register unit, and the period of the follow-up clock is increased from a short cycle to a long cycle by the mask unit. Propagation of the remaining clock generated when the period is switched to the inside of the shift register unit is prohibited and masked.
[0007]
With this configuration, the amount of phase change corresponding to the phase shift between the tracking clock and the received signal can be adjusted by a single tracking operation.
[0008]
(B) The second inventionSynchronous tracking circuit(1) Phase change amount determining means for calculating the correlation power for two phases before and after the synchronization phase and determining the phase change amount with respect to the follow-up clock by comparing the difference between them and a plurality of threshold values; Tracking clock generation means for partially expanding and contracting the period of the generated tracking clock according to the amount of change;With (2) The following clock generating means is (2-1) A shift register that outputs the output of the first stage as the follow-up clock; and (2-2) Either a plurality of outputs given from each stage constituting the shift register unit or an operation output thereof is selected according to the phase change amount given from the phase change amount determining means, and this is sent to the first stage of the shift register unit A feedback input switching unit that partially expands and contracts the period of the follow-up clock. (2-2) The shift register unit includes a mask unit including a plurality of mask units provided between two adjacent stages constituting the shift register unit, and the period of the follow-up clock is increased from a short cycle to a long cycle by the mask unit. Propagation of the remaining clock generated when the period is switched to the inside of the shift register unit is prohibited and masked.
[0009]
In such a configuration, even when the phase change amount is set finely, only two correlation power calculating means are required for the phase change amount determining means, and the hardware configuration is less than that of the first invention.
[0010]
(C) In the third invention, the synchronization tracking circuit of the first or second invention is communicated with the demodulation means for demodulating the correlation output calculated from the follow-up clock of the synchronization tracking circuit after detection. Install on the device. As a result, it is possible to improve the follow-up performance of the follow-up clock with respect to the received signal, and it is possible to realize a communication device that has high communication quality and is difficult to disconnect the line.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
(A) First embodiment
Hereinafter, a first embodiment of a synchronous tracking circuit according to the present invention will be described with reference to the drawings.
[0012]
(A-1) Clock cycle determination method
First, a method for determining a clock cycle used in the synchronous tracking circuit according to the present embodiment will be described. In this clock cycle determination method, correlation power is calculated for a plurality of phases centered on the synchronization phase, and the difference between the phase giving the maximum value and the synchronization phase is determined as the optimum phase change amount for tracking the clock phase. It is. If the phase change amount is given to a follow-up clock generation circuit capable of controlling the clock cycle in multiple stages, the follow-up clock phase can be corrected by a single follow-up control.
[0013]
In the following description, as shown in FIG. 4, each of nine positions given by halving the ½ Chip advance phase range from the ½ Chip lag phase to the ½ Chip advance phase with the synchronization phase (current tracking phase) as the center. A method for calculating the correlation power for the phase and determining the difference between the phase that gives the maximum value and the synchronization phase as the optimum phase change amount for tracking the clock phase will be described.
[0014]
Incidentally, the symbol C (p) shown in FIG. 4 represents the value of the correlation power in the phase p. In the case of FIG. 4, the correlation calculated for the phase that is ¼ chip lag with respect to the synchronization phase. The power value is the maximum value. Therefore, in the case of FIG. 4, the synchronous tracking circuit performs control so that the phase of the follow-up clock is delayed by 1/4 Chip with respect to the current follow-up phase.
[0015]
For reference, FIG. 5 shows how the phase change of the follow-up clock is changed by the control operation when the maximum value of the correlation power is obtained in each phase shown in FIG. In addition, the part shown with the thick line in the figure is a part in which the phase was adjusted.
[0016]
(A-2) Configuration of synchronization tracking circuit
FIG. 1 shows a functional block configuration of a synchronous tracking circuit mounted on a CDMA communication apparatus that uses the method described in the section (A-1) for determining the clock cycle. In a CDMA communication apparatus in which the synchronization tracking circuit is mounted, the correlation output (despread output) whose phase is adjusted by the follow-up clock is detected, and further error correction is performed, so that the original bit stream is changed. Demodulation processing is performed.
[0017]
Returning to the description of the synchronous tracking circuit of FIG. The synchronous tracking circuit includes nine correlation power calculation units 1 (1A to 1I) corresponding to the nine phases described above, a clock cycle selection / phase change accumulated value calculation unit 2, a follow-up clock generation circuit 3, and a CPU 4 And are the main components.
[0018]
(A) Correlation power calculation unit
Each of the correlation power calculation units 1A to 1I has a function of generating a clock of a phase corresponding to each unit based on the tracking clock given from the tracking clock generation circuit 3, and latches input data using the generated clock. And a function of calculating the correlation power with the spreading code.
[0019]
Here, the correlation power calculation unit 1A generates a clock having a ½ chip phase advanced from the follow-up clock, and latches input data using this. Similarly, the correlation power calculation units 1B, 1C, and 1D respectively generate clocks having advanced 3/8 chip, 1/4 chip, and 1/8 chip phases from the follow-up clock, and latch the input data using the generated clocks. The correlation power calculation units 1F, 1G, 1H, and 1I generate clocks that are delayed by 1/8 chip, 1/4 chip, 3/8 chip, and 1/2 chip from the follow-up clock, respectively. Latch. However, the correlation power calculation unit 1E latches input data using the tracking clock as it is.
[0020]
Here, the input data given to the correlation power calculation units 1A to 1I is obtained by dropping the received signal (modulated with the CDMA spreading code) received through the propagation path into the paceband band by the filter. Is oversampled at 8 times the Chip rate.
[0021]
In addition, in these correlation power calculation units 1A to 1I, the correlation power is usually added over a plurality of chip sections (for example, 64 Chip section, 128 Chip section, etc.), and the addition result is displayed every time the section expires. It is designed to output. That is, if the correlation power is added over the 64 Chip interval, the added value is output as the correlation power for every 64 Chip.
[0022]
(B) Clock cycle selection and phase change cumulative value calculation unit
The clock cycle selection / phase change accumulated value calculation unit 2 detects the input having the maximum correlation power among the nine inputs given from the correlation power calculation units 1A to 1I, and provides the phase and the synchronization phase. And a function of giving the phase difference (phase change amount) to the follow-up clock generation circuit 3 as a correction value so that the correlation power of the synchronization phase is maximized.
[0023]
The clock cycle selection and phase change accumulated value calculation unit 2 realizes the latter function by notifying the switch number corresponding to the phase difference. This is because the follow-up clock generation circuit 3 in this embodiment adopts a circuit configuration that realizes phase control of the follow-up clock by switching control of the switch. Therefore, the clock cycle selection / phase change accumulated value calculation unit 2 is provided with a correspondence table storing a relationship with the switch number corresponding to the correction value (phase change amount), and the correspondence table is referred to. Accordingly, the corresponding switch number is selected.
[0024]
FIG. 6 shows an example of the correspondence table. In FIG. 6, in addition to the relationship between the switch number and the phase change amount, the relationship between the switch number and the period, the duty ratio, and the mask code is also shown. Of these, the cycle represents how the cycle length is switched by switching the switch, and the duty ratio is the length and ratio of the first half cycle and the second half cycle of the cycle (reference) The duty ratio of the chip period is 4: 4). The mask code will be described again when the tracking clock generation circuit 3 is described.
[0025]
In addition, the clock cycle selection and phase change accumulated value calculation unit 2 has a function of calculating the accumulated value of the changed phase and reporting the value to the CPU 4 or the like as the phase change accumulated value. This is because the CDMA communication apparatus is generally provided with a plurality of demodulation units (finger), and the CPU 4 needs to monitor and control the follow-up status of each finger. This function is realized by an adder / subtracter. Incidentally, the accumulated value held in the adder / subtracter is once reset at the time of the stem reset, and then the value is updated every time the phase change amount (actually the switch number) is instructed.
[0026]
(C) Tracking clock generation circuit
The follow-up clock generation circuit 3 has a function of controlling the phase (cycle) of the follow-up clock generated based on the phase change amount notified from the clock cycle selection and phase change accumulated value calculation unit 2. The follow-up clock generation circuit 3 realizes this function by adaptively switching the feedback period of the cyclic clock with a switch. FIG. 7 shows an example of the circuit. FIG. 7 shows a configuration example for adjusting the phase of the follow-up clock from a 1/2 Chip delay phase to a 1/2 Chip advance phase with respect to the synchronization phase in 1/8 Chip increments as long as the switching speed is allowed. It is possible to realize a circuit capable of adjusting the phase in an arbitrary range with respect to an arbitrary range.
[0027]
The follow-up clock generation circuit 3 includes a shift register unit 31 and a feedback input switching unit 32. Among these, the shift register unit 31 is configured by cascading six D flip-flops FF0 to FF5. These D flip-flops FF0 to FF5 operate using a 1/8 chip clock as a shift clock. This is because the phase of the follow-up clock is controlled in increments of 1/8 Chip. The output of each D flip-flop FF0 to FF5 is given to the next stage via a mask gate.
[0028]
Here, the propagation through the mask gate is to prohibit the remaining pulses from appearing in the follow-up clock at an unexpected timing when the period is switched (particularly when switching from the short period to the long period). . In the present embodiment, the mask gate is composed of an OR gate. Incidentally, a mask code of a value “0” is given to a mask gate that is allowed to propagate a clock to the subsequent stage. On the other hand, a mask code having a value “1” is given to a mask gate in which clock propagation to the subsequent stage is prohibited.
[0029]
This is because the mask code of the value “1” gives the value input to the next flip-flop to be “1”, and the inverted output NQ fed back to the feedback input switching unit 32 from the flip-flop. This is because the value of can be forced to the “L” level. If this function is not provided, it is unavoidable that after switching from the short cycle to the long cycle, the residual pulse propagated before the cycle switching appears in the tracking flop. Incidentally, in the present embodiment, the function of the mask gate is realized by the OR gate, but it can also be realized by directly controlling the S terminal (set terminal) of the flip-flop.
[0030]
On the other hand, the feedback input switching unit 32 synchronizes with the falling timing of the follow-up clock according to the input of the switch number from the clock cycle selection and phase change accumulated value calculation unit 2 (that is, the inverted output of the first stage D flip-flop FF0). This is a means for selectively outputting one of nine feedback inputs using the rise of NQ (0) as a trigger.
[0031]
By selecting the feedback input in the feedback input switching unit 32, the cycle and duty ratio of the follow-up clock (that is, Q output) output from the first stage D flip-flop FF0 constituting the shift register unit 31 can be switched.
[0032]
For example, if the input of the switch number 1 (SW1) is selected, the inverted output NQ (5) of the D flip-flop FF5 constituting the sixth stage of the shift register unit 31 can be output as the follow-up clock. The period of this follow-up clock is 3/2 Chip (1/8 chip clock divided by 12), and its duty ratio is 6: 6.
[0033]
In this case, each mask gate is given a value of “0” as mask codes Mask (0) to (4) (see FIG. 6). This is to allow propagation to the subsequent stage of the tracking clock. That is, in the output Q and the inverted output NQ of each D flip-flop, a follow-up clock or a signal obtained by inverting it is delayed by a time corresponding to the number of stages of the D flip-flop.
[0034]
If the input of the switch number 2 (SW2) is selected, the inverted output NQ (4) of the flip-flop FF5 constituting the fifth stage of the shift register unit 31 and the inverted output NQ of the flip-flop FF5 constituting the sixth stage. An output composed of the logical sum of (5) can be output as a follow-up clock.
[0035]
Here, the logical sum of the inverted outputs NQ output from two different output stages is used as a feedback input in order to generate a follow-up clock obtained by dividing the shift pulse by an odd multiple. At this time, the period of the follow-up clock is 11/8 Chip, and the duty ratio is 5: 6. Also in this case, the values of the mask codes Mask (0) to (4) are all “0”.
[0036]
Similarly, when each input of switch number 3 (SW3) to switch number 9 (SW9) is selected, an inverted output NQ of the corresponding D flip-flop or an output of the logical sum thereof is output as a follow-up clock. And a tracking clock having a desired period and duty ratio can be obtained.
[0037]
The relationship between the inverted output NQ fed back to each switch number or the output of the logical sum thereof is shown in FIG. 7 as in the case of the switch number 1 (SW1) and switch number 2 (SW2) described above. Since it exists, description is abbreviate | omitted. FIG. 6 also shows the values of the mask codes Mask (0) to (4) to be given when each of these switch numbers is selected.
[0038]
(A-3) Operation of synchronization tracking circuit
Next, the operation of the synchronous tracking circuit according to the present embodiment, that is, the operation for generating the tracking clock will be described. Here, description will be made with reference to FIGS.
[0039]
First, the case where the phase of the follow-up clock is delayed by 1/4 Chip by one follow-up control will be described with reference to FIG. In this operation, when the clock cycle selection and phase change cumulative value calculation unit 2 detects that the value of the correlation power calculated by the correlation power calculation unit 1G corresponding to the 1/4 Chip delay phase is the maximum value. This is the operation performed.
[0040]
When the clock cycle selection and phase change accumulated value calculation unit 2 detects that the phase shift is + 1 / 4Chip in this way, the switch number SW3 corresponding to this is read from the correspondence table and is sent to the follow-up clock generation circuit 3. Output. At this time, the mask code “00001” is also read and output.
[0041]
The follow-up clock generation circuit 3 provides the notified switch number SW3 to the feedback input switching unit 32 and also provides the mask code “00001” to the mask gate of the shift register unit 31.
[0042]
As shown in FIGS. 8C and 8D, the feedback input switching unit 32 performs feedback input switching at the trailing edge of the follow-up clock, and constitutes the fifth stage of the shift register unit 31. The inverted output NQ (4) of the flip-flop FF4 is output to the first stage D flip-flop FF0. At this time, since the logic level of the inverted output NQ (4) is “L”, the waveform of the follow-up clock also falls to the “L” level.
[0043]
Thereafter, the inverted output NQ (4) of the “L” level is sequentially transferred to the subsequent D flip-flop, and after 5/8 chip clock, the inverted output of the D flip-flop FF4 constituting the fifth stage of the shift register unit 31. NQ (4) rises to a logic “H” level. Since this is fed back to the first-stage D flip-flop FF0, the logic level of the feedback input inputted to the first-stage D flip-flop FF0 becomes “H” level after 5/8 Chip clocks from the switching of the previous feedback input. The waveform of the tracking clock rises.
[0044]
After this, the clock whose waveform has risen is sequentially transferred. As in the case of the first half cycle, the inverted output NQ (4) of “H” level is sequentially transferred to the D flip-flop at the subsequent stage, and after the 5/8 chip clock, the D constituting the fifth stage of the shift register unit 31 again. The flip-flop FF4 is reached and its inverted output NQ (4) falls to the logic “L” level. This is fed back to the first stage D flip-flop FF0, so that the follow-up clock falls to the logic “L” level.
[0045]
At this time, since the inverted output NQ (1) of the first stage D flip-flop FF0 is switched to the “H” level, the feedback input switching unit 32 is triggered by the input of the inverted output NQ (1) as a trigger. The feedback input to be output to the FF0 is switched, and thereafter, the process returns to the process of selectively outputting the feedback input of the switch number SW5 corresponding to the synchronization phase.
[0046]
Since the above operation is the same as inserting one cycle of a 5/4 chip cycle clock, the phase correction required for one follow-up control is realized.
[0047]
Next, a case where the phase of the follow-up clock is advanced by 3/8 Chip by one follow-up control will be described with reference to FIG. This operation is performed when it is detected in the clock cycle selection and phase change cumulative value calculation unit 2 that the value of the correlation power calculated by the correlation power calculation unit 1B corresponding to the 3/8 chip advance phase takes the maximum value. This is the operation performed.
[0048]
When the clock cycle selection and phase change accumulated value calculation unit 2 detects that the phase shift is −3 / 8Chip in this way, the switch number SW8 corresponding to this is read from the correspondence table, and the follow-up clock generation circuit 3 Output to. At this time, the mask code “00111” is also read and output.
[0049]
The follow-up clock generation circuit 3 provides the notified switch number SW8 to the feedback input switching unit 32 and also provides the mask code “00111” to the mask gate of the shift register unit 31.
[0050]
As shown in FIGS. 9C and 9D, the feedback input switching unit 32 performs feedback input switching at the falling timing of the follow-up clock, and forms a second stage of the shift register unit 31. An output consisting of the logical sum of the inverted output NQ (1) of the flip-flop FF1 and the inverted output NQ (2) of the D flip-flop FF2 constituting the third stage is output to the first-stage D flip-flop FF0. At this time, since the logical level of any inverted output is “L”, the logical sum thereof is also “L” level. Of course, at this time, the waveform of the follow-up clock also falls to the “L” level.
[0051]
Thereafter, the logical sum output of the “L” level is sequentially transferred to the subsequent D flip-flop, and after 2/8 chip clock, the inverted output NQ (1) of the D flip-flop FF1 constituting the second stage of the shift register unit 31. ) Rises to a logic "H" level. Incidentally, at this time, the inverted output NQ (2) of the D flip-flop FF2 constituting the third stage is still at the logic “L” level, but the logical sum of both inverted outputs is “H” at this time. Switch to level. Therefore, after 2/8 Chip clocks from the switching of the previous feedback input, the logical level of the feedback input input to the first stage D flip-flop FF0 changes to the “H” level, and the waveform of the follow-up clock rises.
[0052]
After this, the clock whose waveform has risen is sequentially transferred. However, this time, a period of 3/8 Chip clock is required to invert the waveform of the logical sum of both inverted outputs. This is because the logical value of the inverted output NQ (1) of the D flip-flop FF1 constituting the second stage of the shift register unit 31 falls to the logic “L” level at the time of 2/8 Chip clock, but the third stage This is because the logical value of the inverted output NQ (2) of the D flip-flop FF2 that is configured still maintains the “H” level. The logical sum of both inverted outputs is switched to the “L” level for the first time after the 3/8 Chip clock, and the logical level of the feedback input input to the first stage D flip-flop FF0 also changes to the “L” level. As a result, the waveform of the tracking clock falls.
[0053]
At this time, since the inverted output NQ (1) of the first stage D flip-flop FF0 is switched to the “H” level, the feedback input switching unit 32 is triggered by the input of the inverted output NQ (1) as the trigger. The feedback input to be output to the flip-flop FF0 is switched, and thereafter, the process returns to the process of selectively outputting the feedback input of the switch number SW5 corresponding to the synchronization phase.
Since the above operation is the same as inserting a 3/8 chip cycle clock, the phase correction required for one follow-up control is realized.
[0054]
(A-4) Effects of the first embodiment
As described above, according to the synchronous tracking circuit according to the present embodiment, the tracking clock generation circuit 3 that can control the period of the tracking clock in multiple stages is provided, so that the received signal and the tracking clock are between the received signal and the tracking clock. Even when a phase difference is detected, the phase difference can be corrected by changing the clock cycle once, so that the time required for tracking can be reduced.
[0055]
If the synchronization tracking circuit is installed in a CDMA communication device, the follow-up performance of the follow-up clock with respect to the received signal can be improved, and a communication device with high communication quality and hardly broken lines can be realized.
[0056]
(B) Second embodiment
Next, a second embodiment of the synchronous tracking circuit according to the present invention will be described with reference to the drawings. In the following description, only differences from the first embodiment will be described. That is, only the difference in configuration between the clock cycle determination method and the synchronization tracking circuit associated therewith will be described.
[0057]
(B-1) Clock cycle determination method
A feature of the clock cycle determination method according to the present embodiment is that the correlation power is calculated only for two phases. The phase change amount optimal for tracking the clock phase is calculated, and a plurality of calculated correlation power differences are calculated. It is in the point determined by comparing with the threshold value. That is, in this embodiment, as shown in FIG. 10, the correlation power is calculated only for the ½Chip delay phase and the ½Chip advance phase, and the difference is compared with the following four thresholds to obtain the clock phase. The optimum phase change amount for tracking is determined.
[0058]
There are four threshold values used here: DLL threshold value, threshold value A, threshold value B, and threshold value C. Among these, the DLL threshold value is the same as that used in the description of the prior art, that is, a threshold value used for determining the state of the substantially synchronous phase. On the other hand, the threshold A is a threshold for determining whether or not the phase adjustment is within １ ／ Chip. The threshold B is a threshold for determining whether or not the phase adjustment is within 1/4 Chip. The threshold value C is a threshold value for determining whether or not the phase adjustment is within 3/8 Chip.
[0059]
Since the optimum values for these threshold values are determined according to the Chip interval for calculating the correlation power, the level of the input signal, and the like, it is necessary to set values according to the system to be applied.
[0060]
Next, how the phase adjustment amount is determined using the four threshold values will be described. However, the determination method shown below is based on the assumption that the correlation power characteristic curve has a maximum value in the original synchronization phase and decreases symmetrically as the distance from the phase increases, as shown in FIG. Yes.
[0061]
(1) Threshold C <(1 / 2Chip delayed correlation power)-(1 / 2Chip advanced correlation power)
: Phase change amount = + 1 / 2Chip (FIG. 5A)
(2) Threshold B <(1 / 2Chip delayed correlation power) − (1 / 2Chip advanced correlation power) ≦ Threshold C
: Phase change amount = + 3 / 8Chip (FIG. 5B)
(3) Threshold A <(1 / 2Chip delayed correlation power) − (1 / 2Chip advanced correlation power) ≦ Threshold B
: Phase change amount = + 1 / 4Chip (FIG. 5C)
(4) DLL threshold <(1 / 2Chip delayed correlation power) − (1 / 2Chip advanced correlation power) ≦ Threshold A
: Phase change amount = + 1 / 8Chip (FIG. 5D)
▲ 5 ▼ | (1 / 2Chip delayed correlation power) − (1 / 2Chip advanced correlation power) | ≦ DLL threshold
: Phase change amount = 0 (FIG. 5E)
(6) DLL threshold <-{(1 / 2Chip delayed correlation power)-(1 / 2Chip advanced correlation power)} ≦ threshold A
: Phase change amount = −1 / 8Chip (FIG. 5F)
(7) Threshold A <− {(1 / 2Chip delayed correlation power) − (1 / 2Chip advanced correlation power)} ≦ Threshold B
: Phase change amount = −1 / 4Chip (FIG. 5G)
(8) Threshold B <− {(1 / 2Chip delayed correlation power) − (1 / 2Chip advanced correlation power)} ≦ Threshold C
: Phase change amount = −3 / 8Chip (FIG. 5H)
(9) Threshold value C <-{(1 / 2Chip delayed correlation power)-(1 / 2Chip advanced correlation power)}
: Phase change amount = −1 / 2Chip (FIG. 5I)
Therefore, in the case of FIG. 10, since the correlation power difference is larger than the threshold A but less than or equal to the threshold B (threshold A <correlation power difference ≦ threshold B), the phase of the follow-up clock may be delayed by 1/4 Chip.
[0062]
(B-2) Configuration and operation of synchronization tracking circuit
FIG. 11 shows a functional block configuration of a synchronous tracking circuit mounted on a CDMA communication apparatus that uses the method described in the section (B-1) for determining the clock cycle. In FIG. 11, corresponding parts to those in FIG. 1 showing the functional block configuration of the synchronous tracking circuit in the first embodiment are denoted by corresponding reference numerals, and the same parts are denoted by the same reference numerals.
[0063]
The difference between the synchronization tracking circuit shown in FIG. 11 and the synchronization tracking circuit shown in FIG. 1 is that the correlation power calculation unit 1 ′ calculates the correlation power at the 1 / 2Chip lead phase, and the 1 / 2Chip delay phase. The correlation power calculation unit 1I for calculating the correlation power at 2 and the clock cycle selection and phase change accumulated value calculation unit 2 ′ are adjusted by comparing the difference between the two inputs and the four threshold values. There are only two points for determining the necessary phase amount.
[0064]
Therefore, the operation after the clock cycle selection and the phase change accumulated value calculation unit 2 ′ determines the phase change amount (reading of the switch number SW No. based on the correspondence table shown in FIG. 6) and the follow-up clock generation circuit 3 Is notified of the switch number SW No. The operation of changing the clock cycle according to the above is exactly the same as in the first embodiment.
[0065]
(B-3) Effects of the second embodiment
As described above, according to the synchronization tracking circuit according to the present embodiment, only two correlation power calculation units need to be provided, so that the hardware configuration is compared to the case of the first embodiment. Can be reduced.
[0066]
If the synchronization tracking circuit is installed in a CDMA communication device, the follow-up capability of the follow-up clock with respect to the received signal can be improved as in the first embodiment, and a communication device with high communication quality and difficult to disconnect the line can be realized. .
[0067]
(C) Other embodiments
In the above-described embodiment, the case where the phase of the follow-up clock is adjusted in the range of the 1/2 Chip lag phase to the 1/2 Chip advance phase centering on the synchronization phase (current follow-up phase) has been described. It is not limited to. For example, it may be adjustable over a wider range than this, or may be adjustable over a narrow range.
[0068]
Similarly, in the above-described embodiment, the case where the minimum unit of the phase change amount given to the follow-up clock is 1/8 Chip has been described. However, the adjustment unit is not limited to this, and the phase change amount is smaller. Can be specified.
[0069]
The correspondence relationship (FIGS. 6 and 7) between the switch number and the phase change amount in the above-described embodiment is an example, and can be set according to the connection relationship.
[0070]
In the above-described embodiment, the case where the correlation power is calculated over a certain interval (for example, 64 Chip interval, 128 Chip interval, etc.) has been described. However, this does not preclude calculation for each Chip interval.
[0071]
In the above-described embodiment, the synchronization tracking circuit used in the CDMA communication apparatus has been described. However, the present invention can be widely applied to communication apparatuses that perform communication using spread spectrum technology.
[0072]
In the second embodiment described above, the case where the phase change amount is calculated based on the correlation power calculated for the two phases of the ½ Chip lag phase and the ½ Chip advance phase of the synchronization phase has been described. The two phases used for this calculation are not limited to such combinations of phases.
[0073]
In the second embodiment described above, the case where the phase change amount is determined using the DLL threshold value and the threshold values A, B, and C has been described. However, the phase change can be achieved by increasing or decreasing the number of threshold values to be used. The accuracy of quantity can be changed freely.
[0074]
【The invention's effect】
According to the first aspect described above, the correlation power is calculated for a plurality of front and rear phases including the synchronization phase, and the difference between the phase giving the maximum value and the synchronization phase can be directly given as the phase change amount with respect to the follow-up clock. The amount of phase change corresponding to the phase shift between the tracking clock and the received signal can be adjusted by a single tracking operation, and the time required for tracking can be reduced.
[0075]
Further, according to the second invention described above, no matter how fine the phase change amount is set, only two correlation power calculation means are required for calculating the correlation power. The effect can be realized with a small hardware configuration.
[0076]
Furthermore, according to the above-mentioned third invention, the follow-up performance of the follow-up clock with respect to the received signal can be improved by mounting the synchronous tracking circuit of the above-described first or second invention in the communication device, and communication quality can be improved. It is possible to realize a communication device that is high and is difficult to disconnect.
[Brief description of the drawings]
FIG. 1 is a diagram showing a functional block configuration of a synchronous tracking circuit according to a first embodiment.
FIG. 2 is a diagram illustrating a principle of determining a phase change amount used in a conventional apparatus.
FIG. 3 is a diagram showing a clock cycle change mode that is possible in a conventional apparatus.
FIG. 4 is a diagram illustrating a principle of determining a phase change amount used in the first embodiment.
FIG. 5 is a diagram illustrating a clock cycle change mode that is possible in the embodiment device;
FIG. 6 is a diagram illustrating a correspondence table.
FIG. 7 is a diagram showing a functional block configuration of a follow-up clock generation circuit.
FIG. 8 is a diagram showing the phase relationship of each signal when the phase of the follow-up clock is delayed by extending the clock cycle by one place.
FIG. 9 is a diagram showing the phase relationship of each signal when the phase of the follow-up clock is advanced by shortening the clock cycle by one place.
FIG. 10 is a diagram illustrating a principle of determining a phase change amount used in the second embodiment.
FIG. 11 is a diagram showing a functional block configuration of a synchronous tracking circuit according to a second embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1A-1I ... Correlation power calculation part, 2, 2 '... Clock period selection and phase change accumulation value calculation part, 3 ... Tracking clock generation circuit, 4 ... CPU, 31 ... Shift register part, 32 ... Feedback input switching part.

Claims (3)

Phase change amount determining means for calculating the correlation power for a plurality of front and rear phases including a synchronization phase, and determining the difference between the phase giving the maximum value and the synchronization phase as the phase change amount with respect to the tracking clock;
Tracking clock generating means for partially expanding and contracting the period of the generated tracking clock according to the phase change amount,
The following clock generating means is
A shift register that outputs the output of the first stage as the follow-up clock; and
Either a plurality of outputs given from each stage constituting the shift register unit or an operation output thereof is selected according to the phase change amount given from the phase change amount determining means, and this is sent to the first stage of the shift register unit A feedback input switching unit that partially expands and contracts the period of the follow-up clock.
The shift register unit includes a mask unit including a plurality of mask units provided between two adjacent stages constituting the shift register unit, and the period of the follow-up clock is increased from a short cycle to a long cycle by the mask unit. A synchronization tracking circuit, wherein masking is performed by prohibiting propagation of a remaining clock generated when switching to a period in the shift register unit . Phase change amount determining means for calculating correlation power for two phases before and after the synchronization phase, and determining a phase change amount with respect to the follow-up clock by comparing the difference between them and a plurality of threshold values;
Tracking clock generating means for partially expanding and contracting the period of the generated tracking clock according to the phase change amount,
The following clock generating means is
A shift register that outputs the output of the first stage as the follow-up clock; and
Either a plurality of outputs given from each stage constituting the shift register unit or an operation output thereof is selected according to the phase change amount given from the phase change amount determining means, and this is sent to the first stage of the shift register unit A feedback input switching unit that partially expands and contracts the period of the follow-up clock.
The shift register unit includes a mask unit including a plurality of mask units provided between two adjacent stages constituting the shift register unit, and the period of the follow-up clock is increased from a short cycle to a long cycle by the mask unit. A synchronization tracking circuit, wherein masking is performed by prohibiting propagation of a remaining clock generated when switching to a period in the shift register unit . 3. A communication apparatus comprising: the synchronization tracking circuit according to claim 1; and demodulation means for demodulating a correlation output calculated from a tracking clock of the synchronization tracking circuit after detection.

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