JP3754803B2 - Imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an imaging apparatus, which relates to an imaging apparatus that electronically enlarges / reduces a captured image with high image quality.
[0002]
[Prior art]
Recent advances in digital signal processing technology have brought about significant development in the video field. With the advent of digital recording media such as digital video cameras and digital still cameras, it has become an environment where image data can be recorded, edited, and processed on a personal computer, etc., easily and with high image quality.
[0003]
Conventionally, in digital video cameras, in order to perform zooming more than zooming by an optical system, many processes called electronic zoom for interpolating and enlarging and reducing captured images have been proposed. These used the following algorithm.
[0004]
When there is continuous image data sampled at a certain frequency and the image data is linearly interpolated at some other frequency sampling interval, the time between the original sampling pixel data before and after the interpolation pixel and the interpolation pixel Relative position data k is required.
[0005]
As a method for obtaining this continuously, U.S. Pat. S. Pat. Memory reading means using an accumulator as shown in 4,774,581 may be used. As an example in which this is applied to a video camera, there is JP-A-5-328184. This uses a linear interpolation algorithm.
[0006]
FIG. 10 is an explanatory diagram of this linear interpolation algorithm, and shows a part of an image stored in a memory. S_n , S_n-1 Indicates accumulated pixel data, and S ′ indicates pixel data to be interpolated.
[0007]
At this time, S_n , S_n-1 , S ′ is given by S ′ = S_n ・ K + S_n-1 -It is represented by (1-k). In order to realize this with a digital circuit, this equation is applied to an adder, a subtracter, or a multiplier as it is, or modified to reduce the number of multipliers, and S ′ = (S_n -S_n-1 ) ・ K + S_n-1 It was applied as.
[0008]
FIG. 11 shows an example of an interpolation portion of these conventional linear interpolation type imaging devices. Original sampling pixel data S immediately before the interpolation pixel S ′_n The original sampling pixel data S immediately after the interpolation pixel_n-1Based on the above-mentioned linear interpolation formula based on the relative position data k with the interpolation pixel S ′, S ′ = (S_n -S_n-1 ) ・ K + S_n-1 Is calculated by the subtractor 61, the multiplier 62, and the adder 63, and the interpolated pixel data S 'is output.
[0009]
[Problems to be solved by the invention]
However, these conventional methods have the following drawbacks. In the above-described conventional linear interpolation, although the circuit configuration is simplified, the frequency characteristics are such that the high frequency components are greatly attenuated as shown in FIG. There were drawbacks.
[0010]
In order to solve this, Japanese Patent Laid-Open No. 5-83612 proposes a method of correcting after applying a coefficient to the vertical aperture signal. Although this method is effective in the vertical direction, it is originally shown in FIG. Since the attenuation of the high frequency component is large as shown in FIG. In addition, since the correction in the horizontal direction is not performed, the deterioration in the horizontal resolution is remarkable.
[0011]
A method of enlarging and reducing high-quality images by software processing has also been proposed, but it takes time to process, and a high-performance CPU, large-capacity memory, etc. are required to execute the software. There was a drawback that would be necessary.
[0012]
SUMMARY OF THE INVENTION An object of the present invention is to provide an imaging apparatus capable of enlarging / reducing a high-resolution image with a high resolution with a simple circuit configuration, except for the disadvantages of these conventional examples.
[0013]
[Means for Solving the Problems]
  In order to solve the above problems, the present inventionAn image pickup apparatus having an image pickup device and an image processing unit capable of enlarging or reducing an image of an output signal of the image pickup device in at least one horizontal or vertical direction, 4 adjacent to the horizontal or vertical direction. S data of two pixels _n , S _n-1 , S _n-2 , S _n-3 And S _n-1 And S _n-2 There is a position to be interpolated between _n-1 And the distance to S _n-1 , S _n-2 The image processing unit for the interpolation processing performed when the value divided by the distance is K is P _n = KS _n + (1-K) S _n-3 The average value P represented by _n A first arithmetic circuit for calculating _n-1 = KS _n-1 + (1-K) S _n-2 The average value P represented by _n-1 A second arithmetic circuit that calculates a new coefficient K ′ based on the value of K, and a P _n , P _n-1 And a third arithmetic circuit for calculating the image data value S ′ at the position to be complemented based on the value of K ′.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a first embodiment of the present invention.
[0015]
1 is a CCD which is a color imaging device, 2 is a timing pulse generation which generates a driving timing pulse of the CCD 1 in accordance with the inputted vertical transfer control signal STV, and 3 is a sample and hold of the output signal of the CCD 1 to make a continuous signal Sample and hold, 4 is an AD converter that converts an input signal into a digital signal, 5 and 6 are 1H delays that delay the input signal by one horizontal period or hold the current data in accordance with the given write control signal WC , 7 is a color separation that separates the color signals R, G, and B from the input signal, 8 is a low-pass filter, 9 is a clamp, white balance, gamma correction, white, dark clip, and color difference matrix for the input RGB signal. Color signal processing for forming a color signal C and 10 is a clamp gamma correction for the input signal Luminance signal processing for forming a luminance signal Y by performing white, dark clip, and edge enhancement. 11 and 12 are to output an output obtained by delaying an input signal by one horizontal period according to a given readout control signal RC. 1H delay for the operation of stopping reading, 13 and 14 horizontal interpolation for horizontally interpolating the input signal according to the given interpolation coefficient SCH, 15 and 16 for the input signal for 1 horizontal period, 2 horizontal 3H delay for obtaining an output delayed for a period and 3 horizontal periods, 17 and 18 for vertical interpolation for performing vertical interpolation of the input signal according to the given interpolation coefficient SCV, 19 for output of the color signal C, and 20 for luminance signal 20 is an input terminal for a zoom ratio ZOOM, 22 is a write control signal WC for a vertical transfer control signal STV, 1H delay 5 and 6 in accordance with the input zoom ratio ZOOM. And a vertical coefficient generator 23 for generating the interpolation coefficient SCV of the vertical interpolations 17 and 18, the read control signal RC of 1H delays 11 and 12, and the interpolation coefficient SCH of the horizontal interpolations 13 and 14 according to the input zoom ratio ZOOM. This is a horizontal coefficient generator.
[0016]
A subject image (not shown) is imaged on the imaging surface on the CCD 1 by an imaging optical system (not shown) and subjected to photoelectric conversion. The photoelectrically converted charges are transferred in the vertical and horizontal directions in accordance with the drive timing pulse generated by the timing pulse 2. At this time, when the vertical transfer control STV is generated, a pulse for performing the vertical transfer in the CCD 1 is not generated from the timing pulse generation 2 and the vertical transfer in the CCD 1 is not performed. For example, when enlarging at a magnification of 2 times, after the charge photoelectrically converted in one horizontal period is read out, vertical transfer is not performed in the next horizontal period, and no charge is read out. This operation is repeated. In the CCD 1, the charge transferred as described above is subjected to charge-voltage conversion at the output unit and output as an imaging signal.
[0017]
This imaging signal is made continuous by the sample and hold 3, converted into a digital signal by the AD converter 4, and then input to the 1H delay 5.
[0018]
The output delayed by one horizontal period by the 1H delay 5 is input to the color separation 7 and low-pass filter 8 and simultaneously input to the 1H delay 6, and further delayed by one horizontal period.
[0019]
Further, in the 1H delays 5 and 6, when the vertical transfer of the CCD 1 is stopped as described above, the write control signal WC is generated from the vertical coefficient generator 22 and no write is performed, and the same signal is transmitted in the next horizontal period. Is also read out.
[0020]
The color separation 7 receives the outputs of the 1H delays 5 and 6 described above. The configuration of the color separation 7 differs depending on the configuration of the mosaic color filter on the imaging surface of the CCD 1, but for example, in the case of interlaced readout with a filter configured by repetition of yellow, cyan, green, and magenta, which are often used. R, G, and B signals can be obtained by calculating signals in two horizontal periods. The R, G, and B signals undergo the above-described process processing in the color signal processing 9 to form a color signal C. This color signal is output in a format suitable for subsequent digital processing, for example, a time division multiplexing format of Cr and Cb.
[0021]
The low-pass filter 8 is set to a characteristic that removes the color carrier generated by the above-described mosaic color filter of the CCD 1 and extracts a luminance signal. The output of the low-pass filter is subjected to the above-described process processing in the luminance signal processing 10, and the luminance signal Y is formed.
[0022]
C and Y formed as described above are first input to 1H delays 11 and 12. In the 1H delays 11 and 12, the written input signal is delayed by one horizontal period, and at the same time, reading is performed according to the read control signal RC generated by the horizontal coefficient generator 23. The outputs of the 1H delays 11 and 12 are input to horizontal interpolations 13 and 14, respectively. In the horizontal interpolations 13 and 14, horizontal four-point interpolation is performed according to the interpolation coefficient SCH generated by the horizontal coefficient generator 23.
[0023]
The outputs of the horizontal interpolations 13 and 14 are input to 3H delays 15 and 16, respectively. The 3H delays 15 and 16 generate outputs obtained by delaying the input signals by 1H, 2H, and 3H, respectively, and are input to the vertical interpolations 17 and 18 together with the undelayed signals.
[0024]
In the vertical interpolations 17 and 18, four-point interpolation is performed from the four signals input according to the interpolation coefficient SCV generated from the vertical coefficient generator 22, and the interpolated signals are output, respectively, and the color signal output terminals 19, The signal is output from the luminance signal output terminal 20 to an external device such as a VTR (not shown) or a television monitor.
[0025]
The zoom ratio ZOOM set by the setting means such as the zoom volume and the zoom switch is input from the input terminal 21 and input to the vertical coefficient generator 22 and the horizontal coefficient generator 23. The vertical coefficient generator 22 generates the vertical transfer control signal STV for the timing pulse generation 2, the write control signal WC for the 1H delays 5 and 6, and the interpolation coefficient SCV for the vertical interpolations 17 and 18 according to the input ZOOM signal. Then, it operates so as to form an image signal enlarged or reduced in the vertical direction at a predetermined magnification.
[0026]
Further, the horizontal coefficient generator 23 generates a 1H delay 11, 12 readout control signal and horizontal interpolation 13, 14 interpolation coefficient SCH in accordance with the input ZOOM signal, and expands it at a predetermined magnification in the horizontal direction. Alternatively, it operates to form a reduced image signal.
[0027]
FIG. 2 shows a detailed example of the vertical interpolation 18 in the embodiment of the present invention. 101, 102, 103, 104, and 105 are input terminals, 106, 109, 112, and 115 are subtracters, 107, 110, 113, and 116 are multipliers, 108, 111, and 114 are adders, and 117 is an output terminal. . The input terminal 101 is the output signal S of the horizontal interpolation 14 in FIG._nEnter. The input terminal 102 receives the signal S delayed by 1H out of the output of the 3H delay 16._n-1Enter. The input terminal 103 receives the signal S delayed by 2H out of the output of the 3H delay 16._n-2Enter. The input terminal 104 receives the signal S delayed by 3H out of the output of the 3H delay 16._n-3Enter. The input terminal 105 inputs the interpolation coefficient SCV among the outputs of the vertical coefficient generator 22.
[0028]
S_nAnd S_n-3Is first subtracted by a subtracter 106 and then multiplied by SCV by a multiplier 107. The output is output by the adder 108 to S_n-3And the signal P_nIt becomes.
[0029]
If the value of SCV is K, this signal P_nS_nAnd S_n-3Is an average value obtained by adding and averaging with K and (1-K) as weights.
[0030]
S_n-1And S_n-2Is first subtracted by a subtractor 109, then multiplied by SCV by a multiplier 110, and S by an adder 111._n-2To be a signal Pn-1.
[0031]
This signal Pn-1 is S_n-1And S_n-2Is an average value obtained by adding and averaging with K and (1-K) as weights. P_nAnd P_n-1Is subtracted by the subtractor 112 and then SCV described later by the multiplier 113.₂And the adder 114 adds P._n-1And the luminance signal Sv vertically interpolated is output from the luminance signal output terminal 117 described above.
[0032]
The input SCV is also multiplied with the SCV itself by the multiplier 116 and then subtracted from the SCV itself.₂It becomes. This SCV₂Is input to the multiplier 113 as described above.
[0033]
The vertical interpolation 17 can also be realized with the same configuration as in FIG.
[0034]
FIG. 3 is a detailed example of the horizontal coefficient generator 23 in the embodiment of the present invention.
[0035]
121 is an input terminal for a zoom coefficient input from the zoom coefficient input terminal 21, 122 is an adder, 123 is a register, 124 is an output terminal for read control RC, and 125 is an output terminal for an interpolation coefficient SCH.
[0036]
The zoom coefficient input from the input terminal 121 is added to the signal obtained by removing the most significant bit from the output of the register 123 in the adder 122, and the output is held in the register 123. Data is updated in the register 123 every clock. As described above, the register 123 outputs the signal excluding the most significant bit as input to the adder 122, outputs the most significant bit as the read control RC from the output terminal 124, and interpolates the value excluding the most significant bit. The coefficient SCH is output from the output terminal 125. For example, if the SCH is 8 bits and the RC is 1 bit, the register 123 is 9 bits. The zoom coefficient is 9 bits, and when it is 1 time, it is assumed to be 256. At this time, since 256 is always added in the adder 122, the lower 8 bits are always 0. The most significant bit is always 1. This value is held in the register 123, RC is always 1, SCH is always 0, data is always read from the above-mentioned 1H delay, no interpolation is performed in the horizontal interpolation, and the whole is expanded in the horizontal direction. The enlargement rate is 1x.
[0037]
When the zoom ratio is about twice, the value of ZOOM becomes 128, and the value of the register 123 changes to 0 128 256 128 256. At this time, the most significant bit is 00 1 0 1, and except for the beginning, one pixel is read out every two pixel periods, and it can be seen that the coefficient changes to 0 0.5 0 0.5 0.
[0038]
The operation of the vertical coefficient generator 22 can also be realized with the same configuration as described above, considering that one pixel is shifted by one horizontal period in the vertical direction.
[0039]
FIG. 4 is a characteristic diagram of the vertical interpolation 18 of FIG.
[0040]
It is the figure which frequency-converted the characteristic provided by the above-mentioned structure, obtained the frequency response, and represented this corresponding to the normalized frequency. Compared with the conventional linear interpolation of FIG. 12, the amount of attenuation in the high frequency region is greatly reduced.
[0041]
FIG. 5 shows a detailed example of horizontal interpolation 14 in the embodiment of the present invention.
[0042]
201, 202 are input terminals, 203, 204, 205 are one-clock delays for delaying one pixel, 206, 209, 212, 215 are subtractors, 207, 210, 213, 216 are multipliers, 208, 211, Reference numeral 214 denotes an adder, and 201 denotes an output terminal.
[0043]
The output from the 1H delay 12 in FIG._nIs entered as Also, the interpolation coefficient output from the horizontal coefficient generator 23 is S from the input terminal 202._chIs entered as S entered_nAre delayed by one pixel by one clock delay 203, 204, 205, respectively. Each output is S_n-1, S_n-2, S_n-3And
[0044]
S_nAnd S_n-3Is first subtracted by the subtracter 206 and then multiplied by the multiplier 207._chAnd multiplied. The output is output by the adder 208 to_n-3And the signal P_nIt becomes.
[0045]
S_n-1And S_n-2Is first subtracted by a subtracter 209, then multiplied by SCV by a multiplier 210, and S by an adder 211._n-2To be a signal Pn-1.
[0046]
P_nAnd P_n-1Is subtracted by the subtractor 212, and then S is described later by the multiplier 213._ch2And the adder 114 adds P._n-1And the horizontally interpolated luminance signal S_hAnd is output from the luminance signal output terminal 207 described above.
[0047]
S entered_chAlso, S_chAfter multiplying with itself, S_chSubtracted from itself, S_ch2It becomes. This S_ch2Is input to the multiplier 213 as described above.
[0048]
The configuration of the horizontal interpolation 13 is substantially the same as in FIG. 5, but since the color signal is dot sequential of Cr and Cb, the point of 1 clock delay becomes 2 clocks and the distance between pixels is doubled. 4 is different from FIG. 4 in that the coefficient is halved.
[0049]
FIG. 6 is an explanatory diagram of an embodiment of the present invention.
[0050]
FIG. 6A shows an operation of horizontal interpolation by the horizontal interpolation 14. Original pixel S_n, S_n-1, S_n-2, S_n-3Against S_n-1And S_n-2The value of the interpolated pixel S ′ is obtained.
[0051]
First, S_n-1, S_n-2The ratio of the distance from is determined as (1-k): k (0 <= K <1).
[0052]
  Next, according to this k, the values of the surrounding pixels Sn, Sn-1, Sn-2, Sn-3 in the horizontal direction are weighted and added to obtain the value of the interpolated pixel S '. The configuration for obtaining the coefficients used at this time is the configuration shown in FIG. This configuration has a frequency response during interpolation.The amount of attenuation in the high frequency region is greatly reduced.
[0053]
FIG. 6B shows the operation of vertical interpolation by the vertical interpolation 18. Similar to FIG. 6A, the original pixel S_n, S_n-1, S_n-2, S_n-3Against S_n-1And S_n-2The value of the interpolated pixel S ′ is obtained.
[0054]
The structure for obtaining the coefficient used at this time is the structure shown in FIG.
[0055]
FIG. 7 shows a second embodiment of the present invention.
[0056]
The same or equivalent parts as those in the previous figure are given the same reference numerals.
[0057]
301 and 302 are field memories, and 303 is a read address generation.
[0058]
A subject image (not shown) is imaged on the imaging surface on the CCD 1 by an imaging optical system (not shown) and subjected to photoelectric conversion. The photoelectrically converted charges are transferred in the vertical and horizontal directions in accordance with the drive timing pulse generated by the timing pulse 2. In the CCD 1, the transferred charge is subjected to charge-voltage conversion at the output unit and output as an imaging signal.
[0059]
This imaging signal is made continuous by the sample and hold 3, converted into a digital signal by the AD converter 4, and then input to the 1H delay 5.
[0060]
The output delayed by one horizontal period by the 1H delay 5 is input to the color separation 7 and low-pass filter 8 and simultaneously input to the 1H delay 6, and further delayed by one horizontal period.
[0061]
The color separation 7 receives the outputs of the 1H delays 5 and 6 described above. The configuration of the color separation 7 differs depending on the configuration of the mosaic color filter on the image pickup surface of the CCD 1. For example, in the case of interlaced readout with a filter composed of repeated yellow, cyan, green, and magenta R, G, and B signals are obtained by calculating signals for two horizontal periods. The R, G, and B signals undergo the above-described process processing in the color signal processing 9 to form a color signal C. This color signal is output in a format suitable for subsequent digital processing, for example, a time division multiplexing format of Cr and Cb.
[0062]
The low-pass filter 8 is set to a characteristic that removes the color carrier generated by the above-described mosaic color filter of the CCD 1 and extracts a luminance signal. The output of the low-pass filter 8 is subjected to the above-described process processing in the luminance signal processing 10 to form the luminance signal Y.
[0063]
C and Y formed as described above are input to the field memories 301 and 302. In the field memories 301 and 302, the written input signal is delayed by one field period, and reading is performed in accordance with the read addresses RAC and RAY generated by the read address generation 303, respectively. The read addresses RAC and RAY are controlled by the vertical read control RCV generated by the vertical coefficient generator 22 and the horizontal read control RCH generated by the horizontal coefficient generator, respectively, and are set to values input from the zoom coefficient input terminal 21. In response, a read address is generated. For example, when the zoom coefficient is a value representing double magnification, control is performed so that one pixel is read out in a period of two pixels in both the horizontal direction and the vertical direction.
[0064]
The outputs of the field memories 301 and 302 are input in the horizontal periods 13 and 14, respectively. In the horizontal interpolations 13 and 14, horizontal four-point interpolation is performed according to the interpolation coefficient SCH generated by the horizontal coefficient generator 23.
[0065]
The outputs of the horizontal interpolations 13 and 14 are input to 3H delays 15 and 16, respectively. The 3H delays 15 and 16 generate outputs obtained by delaying the input signals by 1H, 2H, and 3H, respectively, and are input to the vertical interpolations 17 and 18 together with the undelayed signals.
[0066]
In the vertical interpolations 17 and 18, four-point interpolation is performed from the four signals input according to the interpolation coefficient SCV generated from the vertical coefficient generator 22, and the interpolated signals are output, respectively, and the color signal output terminals 19, It is output from the luminance signal output terminal 20 to an external device such as a VTR (not shown) or a television monitor.
[0067]
The zoom ratio ZOOM set by the setting means such as the zoom volume and the zoom switch is input from the input terminal 21 and input to the vertical coefficient generator 22 and the horizontal coefficient generator 23.
[0068]
As described above, the vertical coefficient generator 22 generates the vertical read control signal RCV for controlling the read address generation 303 and the 3H delay 15 and the interpolation coefficient SCV for the vertical interpolations 17 and 18 in accordance with the input ZOOM signal. Then, it operates to form an image signal enlarged or reduced in the vertical direction at a predetermined magnification.
[0069]
Further, the horizontal coefficient generator 23 generates a horizontal read control signal RCH for the read address generation 303 and an interpolation coefficient SCH for the horizontal interpolations 13 and 14 in accordance with the inputted ZOOM signal, and expands it at a predetermined magnification in the horizontal direction. Alternatively, it operates to form a reduced image signal.
[0070]
FIG. 8 is a diagram showing a third embodiment of the present invention.
[0071]
310 is a clock generation that generates a clock having a frequency different from the timing pulse generation, and 311 and 312 are dual port types in which an input signal is continuously written in synchronization with a write clock, and an output signal is read according to a read clock and a read address. 1H memory for one horizontal period called.
[0072]
The signal flow from the CCD 1 to the output of the color signal processing 9 and the luminance signal processing 10 is the same as in the previous embodiment.
[0073]
The output C of the color signal processing 9 and the output Y of the luminance signal processing 10 are input to the 1H memories 311 and 312.
[0074]
In the 1H memories 311 and 312, writing is continuously performed in synchronization with the clock CK 1 synchronized with the horizontal transfer clock of the CCD 1 generated by the timing pulse generation 2.
[0075]
As described above, the read is performed by the read address RAC generated by the read address generation in accordance with the CK2 generated from the clock generator 310 and the frequency CK2 different from CK1 and the horizontal read control RCH generated from the horizontal coefficient generator 23. It is performed according to RAY.
[0076]
This operation is performed as follows. For simplification of description, only the luminance signal will be described.
[0077]
When the ratio FCK2 / FCK1 of the frequency FCK1 of CK1 and the frequency FCK2 of CK2 is F, the output of the 1H memory 312 is read so that the frequency of the read clock is FCK2 and the read data rate is the same as FCK1. Address RAY is generated. In the horizontal interpolation 14, the signal read from the 1H memory 312 and synchronized with CK2 as described above and having a data rate of FCK1 is input, and this signal is interpolated K times in the horizontal direction. Is output. As a result, the data rate of the luminance signal output from the output terminal 20 becomes FCK2.
[0078]
For example, if K is 5/4, the output from the 1H memory 312 is output in synchronization with the frequency of the FCK2, but the output outputs four data every five clocks. That is, the same data is output twice every five clocks. In the horizontal interpolation 14, the above-described four-point interpolation is performed based on this data, and five interpolated data are generated and output. Therefore, in the output of the horizontal interpolation 14, both the clock frequency and the data rate are FCK2.
[0079]
FIG. 9 is a diagram showing a fourth embodiment of the present invention.
[0080]
320 and 321 are field memories in which writing is performed in accordance with a write address, and reading is performed by sequential scanning, and 322 is a write address generation for generating a write address of the field memory.
[0081]
The signal flow from the CCD 1 to the output of the color signal processing 9 and the luminance signal processing 10 is the same as in the previous embodiment.
[0082]
The output C of the color signal processing 9 and the output Y of the luminance signal processing 10 are input to 3H delays 15 and 16.
[0083]
In the 3H delays 15 and 16, signals delayed by one horizontal period, two horizontal periods, and three horizontal periods are output and input to the vertical interpolations 17 and 18 together with the input signals.
[0084]
In the vertical interpolations 17 and 18, the pixels are interpolated in the vertical direction by the above-described four-point interpolation method according to the interpolation coefficient SCV generated from the horizontal coefficient generator 22. These outputs are input to horizontal interpolations 13 and 14, respectively. In the horizontal interpolations 13 and 14, the input signals are interpolated in the horizontal direction by the above-described four-point interpolation method according to the interpolation coefficient SCH generated from the horizontal coefficient generator 23. Those outputs are input to the field memories 320 and 321.
[0085]
In the field memory 321, the input signal is written according to the write address WAY generated by the write address generation 322. At this time, an address WAY is generated so that a reduced image is written in the field memory in accordance with the zoom ratio input to the zoom ratio input terminal 21.
[0086]
For example, when the zoom ratio represents a reduction of 1/2, the same address is generated every two pixel periods in the horizontal direction and in the vertical direction for two line periods, and the image on the field memory is reduced to 1/2. Operate to become a rendered image.
[0087]
When the zoom ratio is between 1 and 1/2, the vertical interpolation 18 and horizontal interpolation 14 are used to interpolate in the vertical and horizontal directions, and then the address is controlled to increase according to the zoom ratio and written. It operates so that the image on the memory becomes an image reduced to the value of the zoom ratio.
[0088]
The operation of the field memory 320 is almost the same as that described above, but the color signals are time-division multiplexed, so that the data for two pixels is handled as one unit.
[0089]
In the field memories 320 and 321, the color signal and the luminance signal of the reduced image are read out by sequentially reading out the images written by the above-described operation, and are output from the output terminals 19 and 20, respectively.
[0090]
【The invention's effect】
As described above, according to the present invention, when the image of the output signal of the image sensor is enlarged or reduced in at least one horizontal or vertical direction, four points of image data adjacent in the horizontal or vertical direction are used. By obtaining the interpolated image data at a certain position between the pixels based on the above, it is possible to obtain an enlarged / reduced image with excellent frequency characteristics and very little image deterioration.
[0091]
Furthermore, when generating interpolation data based on the four points of image data according to the present invention, data of four adjacent pixels are D0, D1, D2, and D3, and positions to be interpolated between D1 and D2. When the value obtained by dividing the distance between the position and D1 by the distance of D1 and D2 is K, first, in the two combinations of D0 and D3 and D1 and D2, the data of each set is given to the former The average value obtained by adding and averaging (1-K) as a weight for K and the latter is obtained, and the image data at the position to be complemented is obtained based on the two average values, so that only the integer calculation is performed. Since image data can be calculated, it can be easily realized by hardware.
[Brief description of the drawings]
FIG. 1 is a first embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of a vertical interpolation circuit.
FIG. 3 is a diagram showing an example of a horizontal coefficient generator.
FIG. 4 is a characteristic diagram of the vertical interpolation of FIG.
FIG. 5 is a diagram showing a detailed example of horizontal interpolation.
FIG. 6A is an explanatory diagram of a horizontal interpolation operation. B is an explanatory diagram of the vertical interpolation operation.
FIG. 7 is a diagram showing a second embodiment of the present invention.
FIG. 8 is a diagram showing a third embodiment of the present invention.
FIG. 9 is a diagram showing a fourth embodiment of the present invention.
FIG. 10 is an explanatory diagram of conventional linear interpolation.
FIG. 11 is a diagram illustrating an example of a conventional interpolation circuit.
FIG. 12 is a conventional frequency characteristic diagram.

Claims (2)

An image pickup apparatus having an image pickup device and an image processing unit capable of expanding or reducing an image of an output signal of the image pickup device in at least one horizontal or vertical direction,
S _n , S _n−1 , S _n−2 , and S _n−3 are the data of four pixels adjacent in the horizontal direction or the vertical direction, and there are positions to be interpolated between S _n−1 and S _n−2. Yes, the image processing unit for the interpolation processing performed when the value obtained by dividing the distance between the position and S _n-1 by the distance of S _n-1 and S _n-2 is K ,
A first arithmetic circuit that calculates an average value P _n represented by P _n = KS _n + (1−K) S _n−3 ;
A second arithmetic circuit that calculates an average value P _n−1 represented by P _n−1 = KS _n−1 + (1−K) S _n−2 ;
A coefficient calculation circuit for calculating a new coefficient K ′ based on the value of K;
And a third arithmetic circuit that calculates the image data value S ′ at the position to be complemented based on the values of P _n , P _n−1 , and K ′ . The coefficient arithmetic circuit has K ′ = K−K. ² The third arithmetic circuit calculates S ′ = − K′P. _n + (K ′ + 1) P _n-1 The image pickup apparatus according to claim 1, wherein the image data value S ′ at the position to be complemented expressed by:

Images