JP3755658B2 - Manufacturing method of HBT - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a high speed heterojunction bipolar transistor (hereinafter referred to as “HBT”).
[0002]
In this specification, ternary semiconductors are represented as “InAlAs” and “InGaAs”, but these notations simply represent the constituent elements arranged, and do not indicate the ratio of the three elements. Further, the terms “upper” and “lower” mean directions relative to the substrate, and are independent of the direction in which the device is used and the direction during the manufacturing process.
[0003]
[Prior art]
FIG. 6 is a cross-sectional view showing the basic structure of the HBT.
In the figure, reference numeral 10 denotes a substrate. A collector layer 12 is formed on the substrate 10 via a low-resistance subcollector layer 11, and a base layer 14 is formed on the collector layer 12.
[0004]
An emitter layer 16 made of a material having a bandgap different from that of the base layer 14 and a collector electrode 13 connected to the collector layer 12 via the subcollector layer 11 are formed on the upper surface of the base layer 14. Yes.
A base electrode 15 is formed on the upper surface of the base layer 14, and an emitter electrode 17 is formed on the upper surface of the emitter layer 16.
[0005]
A gap E is provided in a region sandwiched between the base electrode 15 and the subcollector layer 11 of the collector layer 12. This air gap contributes to the reduction of parasitic components of the HBT and is for reducing the base-collector capacitance.
[0006]
The material of each layer is, for example, substrate 10: semi-insulating InP, subcollector layer 11: n ⁺ type InGaAs, collector layer 12: n type InP, base layer 14: p ⁺ type InGaAs, emitter layer 16: n type InAlAs. is there.
[0007]
FIG. 7 is a schematic process diagram showing the manufacturing method of this conventional example.
First, as shown in FIG. 1A, on a semi-insulating InP substrate 20, an InAlAs layer 28, an n ⁺ type InGaAs layer 21, an n type InP layer 22, a p ⁺ type InGaAs layer 24, an n type InP layer 29, The n-type InAlAs layer 26 and the n ⁺ -type InGaAs layer 30 are epitaxially grown in order.
[0008]
The n ⁺ -type InGaAs layer 21, the n-type InP layer 22, the p + -type InGaAs layer 24, and the n-type InAlAs layer 26 are the sub-collection layer 11, the collector layer 12, the pace layer 14, and the emitter layer 16 shown in FIG. It is a layer for forming.
[0009]
Although the InAlAs layer 28, the InP layer 29, and the n + type InGaAs layer 30 are omitted in the drawing, they are a buffer layer for growing InGaAs on InP, a layer for stopping etching during emitter formation, And a layer for ohmic contact.
[0010]
Next, as shown in FIG. 7B, the n ⁺ -type InGaAs layer 30 and the n-type InAlAs layer 26 are etched using the InP layer 29 as an etching stopper layer to form the emitter layer 16. Thereafter, the exposed InP layer 29 is removed, the emitter electrode 17 is formed, the sidewall 18 is formed, and the base electrode 15 is formed.
[0011]
Subsequently, as shown in FIG. 3C, the p ⁺ type In GaAs layer 24, the n type InP layer 22, and the n ⁺ type In GaAs layer 21 are etched by wet etching. As the etchant, a chloroacetic acid solution HCl: CH ₃ COOH = 1: 2 is used, and the etching time is extended to remove the InP layer 22 under the base electrode 15.
[0012]
The chloroacetic acid solution is selective and InP dissolves, but InGaAs does not. Selectivity is almost 100%. Therefore, over-etching is possible. After the etching, the collector electrode 13 is attached to the exposed n ⁺ -type InGaAs layer 21.
[0013]
Thereafter, as shown in FIG. 7D, the n ⁺ -type InGaAs layer 21, the InAlAs layer 28, and the semi-insulating InP substrate 20 are etched to perform element isolation.
[0014]
[Problems to be solved by the invention]
[0015]
By the way, in the above-mentioned conventional example, InGaAs is used as the material of the base and the subcollector, and InP is used as the material of the collector sandwiched between them. In such a combination of materials, a chloroacetic acid solution HCl: CH ₃ COOH = 1: 2 can be used as an etchant, and the InP layer 22 under the base electrode 15 can be removed by extending the etching time, so that the selectivity is almost 100. %, So other layers are not etched.
[0016]
However, when the characteristics of the HBT are varied, the base and collector materials may be the same.
Figure 8 shows an example thereof, in this case, ⁿ as the material of the ^p + GaAs, the collector 12 sandwiched between the meantime using the ⁿ + GaAs as the material of the subcollector 11 as the base material - is used GaAs.
[0017]
Then, as shown in FIG. 8A, a mask 50a including the base electrode 15 is applied using a known means, and the base layer is etched.
Subsequently, as shown in FIG. 8B, the masking layer 50b and the collector layer 12 are etched. Here, a mixed solution of citric acid (300 g): hydrogen peroxide (15 cc): water (450 cc) capable of side etching with respect to GaAs is used as the etching solution.
[0018]
As a result, the collector layer is removed downward and the lower portion of the base layer 14 is also removed by side etching, and the portion indicated by the symbol M is also etched, so that the base layer 14 becomes thin.
As a result, there is an adverse effect on the function of the semiconductor, which adversely affects the transistor characteristics (for example, high-speed performance) and lowers the reliability of the device.
The present invention has been made to solve the above-described problems, and provides an HBT manufacturing method in which over-etching does not reach the base layer and does not adversely affect the function of the semiconductor. Objective.
[0019]
[Means for Solving the Problems]
The configuration of the present invention for achieving the above object is as follows.
A subcollector layer (11), a collector layer (12), a base layer (14), and an emitter layer (16) are sequentially stacked on the substrate (10), and are formed on the base layer (14) and the subcollector layer (11). A method of manufacturing a heterojunction bipolar transistor in which a gap is provided in a lower portion of the base layer while leaving a collector portion of the sandwiched collector layer,
In the configuration of the collector layer and the base layer in which there is an etchant that can etch both the material constituting the collector layer and the material constituting the base layer,
A method of manufacturing a heterojunction bipolar transistor, comprising forming the gap in a collector layer sandwiched between the base layer and the subcollector layer, including the following steps.
Step 1: A subcollector layer, a collector layer, a base layer, and an emitter layer are sequentially stacked on a substrate.
Step 2: An emitter electrode is formed on the emitter layer sequentially laminated in Step 1 above, and an emitter layer other than the emitter layer below the emitter electrode is etched to expose the base layer, and the base layer near the emitter electrode is exposed. A base electrode is formed, and the collector layer is exposed by etching the emitter layer and the base layer below the emitter electrode and the base layer other than the base layer below the base electrode.
Step 3: Etching is stopped while the collector layer excluding the lower part of the base layer is being removed by etching using an etchant that can etch both the material constituting the collector layer and the material constituting the base layer.
Step 4: Masking is performed so as to cover the side surface of the portion of the collector layer removed in Step 3 of the collector layer including the emitter electrode and the base electrode.
Step 5: Using an etchant that can etch both the material constituting the collector layer and the material constituting the base layer used in Step 3, above the lower end of the masking that covers the side surface of the collector layer, and The collector layer is side-etched so that the lower surface of the base layer is not etched, thereby forming a void under the base layer.
[0020]
In Claim 2, in the manufacturing method of the heterojunction bipolar transistor of Claim 1,
The base layer, collector layer, and subcollector layer are made of a GaAs compound semiconductor.
[0023]
In Claim 3, in the manufacturing method of the heterojunction bipolar transistor of Claim 1 or 2,
3. The method of manufacturing a heterojunction bipolar transistor according to claim 1, further comprising a step of filling the gap with a material having a dielectric constant smaller than that of the material constituting the collector layer.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a cross-sectional view showing an example of an embodiment of the present invention. As shown in the drawing, the collector layer 12 below the base layer 14 is side-etched to form a gap E, but the lower portion of the base layer 14 is not etched.
[0025]
Next, a method for manufacturing such an HBT will be described with reference to FIG.
In FIG. 2, the step of sequentially stacking the subcollector, collector, base, and emitter on the GaAs substrate and the material of each layer are known as in the conventional example shown in FIG. Further, as shown in FIG. 2 (a), the masking 50a including the base electrode 15 is performed, and the base layer is etched.
[0026]
Next, as shown in FIG. 2B, masking 50b is applied on the base layer 14, and then the collector layer 12 is etched. In the present invention, the thickness of the collector layer 12 is about ½ (in the embodiment, Etching is stopped when the thickness of the collector layer is set to 6000 angstroms (about 3000 angstroms).
[0027]
Next, as shown in FIG. 2C, masking 50c is applied to the removed side of the collector layer 12, and the remaining collector layer is removed by etching.
As a result, as shown in FIG. 1, the collector layer under the base layer is also removed, but the base layer is not etched.
[0028]
Incidentally, and FIG. 2 (b) to what extent the digging thickness of the collector layer 12 in either the extent and etchant materials and impurities constituting the collector layer when the extent to which the thickness of the collector layer 1 2 Since it differs depending on the type, it must be obtained in advance through experiments.
According to the manufacturing method described above, the gap E can be formed in the collector layer 12 without affecting the thickness of the base layer 14.
Note that the space below the base layer may be filled with a material having a lower dielectric constant than the material constituting the collector layer.
[0029]
Next, the third aspect of the present invention will be described. As described above, in order to obtain a desired HBT characteristic, a combination of various compound semiconductors is used. However, a material that is difficult to side-etch may be used for the collector layer 12.
[0030]
FIG. 3 shows an example of an HBT stacking example. A semi-insulating InP substrate is used, and a subcollector layer 31 (n ⁺ InGaAs), a collector layer 32 (n-InP), and a buffer layer 34a (InAlAs) are formed thereon. / InGaAs), a base layer 34 (p ⁺ InGaAs), an etching stopper layer 36b (n-InP), an emitter layer 36 (n ⁺ InAlAs), and an emitter cap layer (n ⁺ InGaAs) 36a. Note that the thickness of each layer is determined according to the desired HBT function.
[0031]
In the above description, the collector layer 32 is n-InP, and this layer is sandwiched between the buffer layer 34a (InAlAs / InGaAs CSL: Shaped Super Lattice) and the sub-collector layer 31 (n ⁺ InGaAs). These layers are both As-based materials and are different materials from the collector layer. Therefore, when etching the collector layer, it is desirable to use an etching solution having such selectivity that only the InP can be removed without removing the As-based material.
[0032]
As a desirable etching solution, there is a mixed solution of hydrochloric acid and phosphoric acid (for example, HCl: H ₃ PO ₄ = 1: 25).
However, this etching solution cannot perform side etching on the collector layer (InP) with respect to a direction parallel or perpendicular to OF (orientation flat) on a wafer having a normal plane orientation.
[0033]
As a method of performing side etching, a method of exposing the surface of the excess collector portion to be removed by side etching to the buffer layer and then removing the excess collector portion by selective etching can be considered. However, when etching the buffer layer, FIG. Since the base layer is also etched in the same manner as the conventional example shown, it causes deterioration of characteristics.
Claim 3 is for solving such a problem.
The subcollector layer 31 (n ⁺ InGaAs), collector layer 32 (n-InP), base layer 34 (p ⁺ InGaAs), and emitter layer 36 (n ⁺ InAlAs) shown in FIG. 3 are shown in FIG. This is a layer for forming the sub-collection layer 11, the collector layer 12, the pace layer 14, and the emitter layer 16.
[0034]
First, as shown in FIG. 4A, the base layer 14 and the base electrode 15 are formed using a known method. Then, masking (51a) is applied to the upper portions of the base layer 14 and the base electrode 15, and etching is performed to expose the collector layer 12.
[0035]
Next, as shown in FIG. 4B, masking 51b is applied to cover the base layer 14, the upper portion of the base electrode 15 and the side surface of the base layer, and the collector layer of the other portion is left leaving the collector 12 layer below the base layer. The subcollector layer 11 is exposed by removing.
[0036]
Next, as shown in FIG. 4C, masking 51 (c) is applied to cover the side surface of the collector layer, and the sub-collector layer 11 (n ⁺ InGaAs) is etched using, for example, a citric acid peraqueous solution. As a result, an undercut can be formed below the collector layer.
[0037]
Subsequently, as shown in FIG. 5, etching is performed from below to above using an InP-based etching solution (for example, a mixed solution of hydrochloric acid and phosphoric acid). As a result, the void E can be formed in the collector under the base layer.
[0038]
The foregoing description of the present invention has only shown certain preferred embodiments for purposes of illustration and illustration. Accordingly, it will be apparent to those skilled in the art that the present invention can be modified and modified in many ways without departing from the essence thereof. For example, the material of the HBT is not limited to the embodiment and can be appropriately selected according to a desired function, and the etching solution can also be appropriately selected depending on the material system. The scope of the present invention defined by the description in the appended claims is intended to include modifications and variations within the scope.
[0039]
【The invention's effect】
As described above in detail, according to the present invention,
A step of sequentially laminating a subcollector layer, a collector layer, a base layer and an emitter layer on the substrate, an emitter electrode is formed on the emitter layer, and an emitter layer other than the emitter layer below the emitter electrode is etched to form a base layer Forming a base electrode on the base layer in the vicinity of the emitter electrode, etching the emitter layer below the emitter electrode, the base layer, and the base layer other than the base layer below the base electrode to expose the collector layer; Using an etchant that can etch both the material constituting the collector layer and the material constituting the base layer, and stopping the etching while the collector layer except the lower portion of the base layer is removed by etching, and the emitter Masking the side surface of the collector layer including the electrode and the base electrode and masking the collector layer Etching solution that can etch both the material to be formed and the material to form the base layer is located above the lower end of the masking that covers the side surface of the collector layer, and the collector layer is side-mounted so that the lower surface of the base layer is not etched. Since an air gap is formed under the base layer by the etching process, overetching is performed in the collector layer and base layer configuration in which there is an etchant that can etch both the material constituting the collector layer and the material constituting the base layer. Therefore, it is possible to realize a method of manufacturing an HBT that is speeded up without reaching the base layer.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of an embodiment of an HBT of the present invention.
2 is a cross-sectional view showing an example of the manufacturing process of FIG. 1. FIG.
FIG. 3 is a cross-sectional view showing another example of stacking of the HBT embodiment of the present invention.
4 is a cross-sectional view showing an example of a manufacturing process of the HBT in the stacked example of FIG. 3. FIG.
5 is a cross-sectional view showing an example of a manufacturing process of the lamination example of FIG. 3. FIG.
FIG. 6 is a cross-sectional view showing an example of a general HBT.
7 is a cross-sectional view showing the manufacturing step of FIG. 6. FIG.
FIG. 8 is a cross-sectional view showing another manufacturing process of the HBT.
[Explanation of symbols]
10 Substrate 11 Subcollector layer 12 Collector layer 14 Base layer 16 Emitter layer

Claims (3)

A subcollector layer (11), a collector layer (12), a base layer (14), and an emitter layer (16) are sequentially stacked on the substrate (10), and are formed on the base layer (14) and the subcollector layer (11). A method of manufacturing a heterojunction bipolar transistor in which a gap is provided in a lower portion of the base layer while leaving a collector portion of the sandwiched collector layer,
In the configuration of the collector layer and the base layer in which there is an etchant that can etch both the material constituting the collector layer and the material constituting the base layer,
A method of manufacturing a heterojunction bipolar transistor, comprising forming the gap in a collector layer sandwiched between the base layer and the subcollector layer, including the following steps.
Step 1: A subcollector layer, a collector layer, a base layer, and an emitter layer are sequentially stacked on a substrate.
Step 2: An emitter electrode is formed on the emitter layer sequentially laminated in Step 1 above, and an emitter layer other than the emitter layer below the emitter electrode is etched to expose the base layer, and the base layer near the emitter electrode is exposed. A base electrode is formed, and the collector layer is exposed by etching the emitter layer and the base layer below the emitter electrode and the base layer other than the base layer below the base electrode.
Step 3: Etching is stopped while the collector layer excluding the lower part of the base layer is being removed by etching using an etchant that can etch both the material constituting the collector layer and the material constituting the base layer.
Step 4: Masking is performed so as to cover the side surface of the portion of the collector layer removed in Step 3 of the collector layer including the emitter electrode and the base electrode.
Step 5: Using an etchant that can etch both the material constituting the collector layer and the material constituting the base layer used in Step 3, above the lower end of the masking that covers the side surface of the collector layer, and The collector layer is side-etched so that the lower surface of the base layer is not etched, thereby forming a void under the base layer.   2. The method of manufacturing a heterojunction bipolar transistor according to claim 1, wherein the base layer, the collector layer, and the subcollector layer are made of a GaAs compound semiconductor.   3. The method of manufacturing a heterojunction bipolar transistor according to claim 1, further comprising a step of filling the gap with a material having a dielectric constant smaller than that of the material constituting the collector layer.

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