JP3757388B2 - Despread demodulator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a despreading demodulator in wireless communication in which a desired signal is frequency-spread by an operation using a spread code and transmitted, and the desired signal is extracted and received by an operation using the spread signal. It is about.
[0002]
[Prior art]
FIG. 9 shows the configuration of a despreading demodulator as the first prior art. In this configuration, the received spread signal is multiplied by the spread code generated by the spread code generation circuit 102 in the multiplier 101 and passed through a low-pass filter (LPF) 103 to remove harmonic components and obtain a received signal. Reference numeral 104 denotes a synchronization control circuit for matching the phases of the spread code and the spread signal.
[0003]
FIG. 10 shows the configuration of the despread demodulator according to the second prior art, and FIG. 11 shows the characteristic of the signal at the point A on the input side and the point B on the output side of the peak detector 204 in the despread demodulator of FIG. Shows a simple waveform. In this configuration, the received spread signal is converted into a correlation signal by the matched filter 201 corresponding to the spread code, delayed by the inverse of the data clock by the delay line 202, and the delayed signal and the correlation signal are multiplied by the multiplier 203. After that, the peak detector 204 performs peak detection to obtain a received signal.
[0004]
[Problems to be solved by the invention]
In the despreading demodulator which is the first prior art shown in FIG. 9, it is necessary to match the phase of the spreading code and the spread signal with high accuracy. For this reason, there is a problem that the synchronization control circuit 104 becomes complicated and the circuit scale and power consumption increase.
[0005]
In the despreading demodulator that is the second prior art shown in FIG. 10, a normal SAW filter is used as the matched filter 201. Therefore, there is a problem that the mounting area and the mounting cost increase. Further, since the matched filter 201 specialized for a specific spreading code is used, there is a problem that a spread signal with a different spreading code cannot be demodulated. Further, when the matched filter 201 is configured by an on-chip circuit, there is a problem that the circuit scale and power consumption increase.
[0006]
The present invention has been made in view of the above points. An object of the present invention is to provide a low-power despreading demodulator that eliminates the need for external components and does not require synchronization control. This contributes to lower power consumption and lower costs.
[0007]
[Means for Solving the Problems]
According to the first aspect of the present invention, there are provided N (N ≧ 2) switches for holding samples of spread signals, a switch control circuit for controlling opening and closing of the N switches by inputting a first clock, A spread code generating circuit that receives N clocks and generates N spread codes; and N outputs that individually multiply the outputs of the N switches and the N spread codes generated by the spread code generator. A multiplier, an adder for adding the outputs of the N multipliers, and a peak detector for detecting a peak of the output of the adder, wherein the period of the first clock is a spread of the spread signal rather equal the period of the clock used for the is said multipliers f input order of said spreading code generated at the spreading code generating circuit and the multiplier f input order the spread signal are the same, and the Difference in frequency between the first clock and the second clock Time obtained by dividing the spreading code length is a despread demodulator, characterized in that it is the same as the data clock period.
[0008]
According to a second aspect of the present invention, there are provided N (N ≧ 2) switches for holding samples of spread signals, a switch control circuit for controlling opening / closing of the N switches by inputting a first clock, A spread code generating circuit that receives N clocks and generates N spread codes; and N outputs that individually multiply the outputs of the N switches and the N spread codes generated by the spread code generator. A multiplier, an adder for adding the outputs of the N multipliers, and a peak detector for detecting a peak of the output of the adder, wherein the period of the first clock is a spread of the spread signal And the input order of the spread code generated by the spread code generation circuit to each multiplier is opposite to the input order of the spread signal to each multiplier, and The sum of the clock frequency and the second clock frequency Time obtained by dividing the dispersion code length is the despread demodulator, characterized in that it is the same as the data clock period.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
FIG. 1 is a block diagram showing a despreading demodulator according to a first embodiment of the present invention. 1a to 1g are switches that sample and hold a spread signal, 2 is a switch control circuit that sequentially controls the switches 1a to 1g by inputting a clock f1 synchronized with the clock used for spreading the spread signal, and 3 is a clock f2. Is a spread code generation circuit that generates a spread code (same as the spread code used for spreading the spread signal), and 4a to 4g are spread signals output from the switches 1a to 1g and spread output from the spread code generation circuit 3 A multiplier for multiplying the sign, 5 is an adder for adding the output signals of the multipliers 4a to 4g, and 6 is a peak detector for detecting a peak value from the output signal of the adder 5.
[0013]
The spread signal is sampled and held by the switches 1a to 1g and input to the multipliers 4a to 4g. At this time, new spread signals received by the switch control circuit 2 are held at the inputs of the multipliers 4a to 4g for every number of clocks equal to the number of multipliers. Also, a spread code is generated from the spread code generation circuit 3 with the clock f2, and is input to the multipliers 4a to 4g in the same order as the spread signal sample holding. In the present embodiment, the case where the number of multipliers is seven is shown, but the number of multipliers is not limited to seven as long as it is plural.
[0014]
FIG. 2 shows an example of the configuration of the switch control circuit 2. A switch control signal waveform generation circuit 21 receives the clock f1 and generates a control signal waveform for turning on the switch by one clock every clocks (here, every 7 clocks) equal to the number of multipliers. . Reference numerals 22a to 22f denote flip-flops serving as shift registers that shift with the clock f1, and supply the switch control signal waveform generated by the switch control signal waveform generation circuit 21 to the switches 1a to 1g while shifting the time by the period of the clock f1. .
[0015]
FIG. 3 shows an example of the configuration of the multiplier 4 (4a to 4g). MN1 to MN7 are NMOS transistors, and the multiplier 4 is constituted by a two-stage vertically stacked differential circuit. The spread code from the spread code generation circuit 3 and the spread signal from the switch 1 (1a to 1g) are differential signals, and the spread code is input to the upper two differential circuits in reverse phase, and the switch 1 The spread signal from is input to the lower differential circuit, the two are multiplied, and the multiplication result is output in the current mode.
[0016]
FIG. 4 shows an example of the configuration of the adder 5. Reference numerals 51 and 52 denote load resistors, and the differential outputs of the multipliers 4a to 4g are added here. As described above, the differential outputs of the multipliers 4a to 4g output in the current mode are converted into voltages by the load resistors 51 and 52 in the adder 5 and added, and output as a baseband signal in the voltage mode.
[0017]
FIG. 5 shows an example of the configuration of the spread code generating circuit 3. Reference numeral 31 denotes an exclusive OR circuit, and 32a to 32f are flip-flops as shift registers that shift with the clock f2. In this example, the output of the second and fifth flip-flops 32b and 32e is taken into the exclusive OR circuit 31, and the result is returned to the input of the first flip-flop 32a to form a spreading code. By simply changing the combination of inputs to the exclusive OR circuit 31, spread codes corresponding to various spread signals can be formed.
[0018]
When the number of switches 1 and multipliers 4 is increased, the number of flip-flops of the switch control circuit 2 and the spread code generation circuit 3 may be increased accordingly.
[0019]
FIG. 6 shows characteristic signal waveforms of the present embodiment. At this time, the signal peak at the output (point A) of the adder 5 in FIG.
Spreading code length / (| f1-f2 |)
Occurs at intervals. By using a clock having a frequency such that the peak interval is equal to the reciprocal of the data clock cycle (data rate cycle) of the transmission digital data as the clock f2 of the spread code generating circuit 3, the output of the peak detector 6 (point B) Baseband output can be obtained. For example, when 10 kbps digital data is spread with a 10 MHz spreading code and transmitted in a 300 MHz radio band, the data clock cycle is 0.1 ms, and the cycle of the clock used for spreading (same as f1) is 0.1 μs, The period of the wireless carrier is 3.33 ns. As described above, despread demodulation can be performed using the spread code generation circuit 3 that does not require synchronization control.
[0020]
[Second Embodiment]
FIG. 7 shows a characteristic signal waveform of the despreading demodulator according to the second embodiment of the present invention. In the present embodiment, the spreading code generated in the spreading code generation circuit 3 is generated by the clock f2, but is input to the multipliers 4a to 4g in the reverse order of the sample holding order of the spreading signal. That is, the output of the flip-flop 32f of the spread code generating circuit 3 shown in FIG. 5 is supplied to the multiplier 4a, the output of the flip-flop 32e is supplied to the multiplier 4b,..., And the output of the flip-flop 32a is supplied to the multiplier 4f. The outputs of the exclusive OR circuit 31 are connected to the multipliers 4g, respectively. As described above, the configuration of the despreading demodulator is the same as that of the first embodiment shown in FIG. 1, but the order of input of the spreading code multipliers 4a to 4g is reversed from that of the first embodiment. ing.
[0021]
At this time, the signal peak at point A is
Spreading code length / (f1 + f2)
It occurs with a gap. By using a clock having a frequency such that the peak interval is equal to the reciprocal of the data clock cycle as the clock f2 of the spread code generating circuit 3, a baseband output can be obtained at point B. Therefore, as in the first embodiment, despread demodulation can be performed using the spread code generation circuit 3 that does not require synchronization control.
[0022]
FIG. 8 shows a characteristic signal waveform when analog signal demodulation is performed according to the second embodiment. Here, the period of the analog signal after demodulation is
Spreading code length / (f1 + f2)
If it is sufficiently longer than that, demodulation is possible by peak detection.
[0023]
【The invention's effect】
As described above, according to the present invention, since despread demodulation is performed using a spread code generation circuit that does not require external components and that does not require synchronization control, a low-power despread demodulator can be realized, and a portable radio device has low power. Effective for reducing power and cost.
[Brief description of the drawings]
FIG. 1 is a block diagram of a despreading demodulator according to a first embodiment of the present invention.
FIG. 2 is a block diagram of a switch control circuit used in the despreading demodulator of the first embodiment of the present invention.
FIG. 3 is a circuit diagram of a multiplier used in the despreading demodulator of the first embodiment of the present invention.
FIG. 4 is a circuit diagram of an adder used in the despreading demodulator of the first embodiment of the present invention.
FIG. 5 is a block diagram of a spreading code generation circuit used in the despreading demodulator of the first embodiment of the present invention.
FIG. 6 is a signal waveform diagram of an addition signal and a demodulated signal obtained by the despreading demodulator of the first embodiment of the present invention.
FIG. 7 is a signal waveform diagram of an addition signal and a demodulated signal obtained by the despreading demodulator of the second embodiment of the present invention.
FIG. 8 is a signal waveform diagram of an addition signal and a demodulated signal when an analog signal is demodulated in the despreading demodulator of the second embodiment of the present invention.
FIG. 9 is a block diagram of a despreading demodulator that is a first prior art.
FIG. 10 is a block diagram of a despreading demodulator that is a second prior art.
FIG. 11 is a signal waveform diagram of an addition signal and a demodulated signal obtained by a despreading demodulator that is the second prior art.
[Explanation of symbols]
1a-1g: switch, 2: switch control circuit, 3: spreading code generation circuit, 4a-4g: multiplier, 5: adder, 6: peak detector.

Claims (2)

N (N ≧ 2) switches for holding samples of the spread signal, a switch control circuit for controlling opening / closing of the N switches by inputting a first clock, and N for inputting a second clock A spreading code generating circuit for generating the spreading codes, N multipliers for individually multiplying the outputs of the N switches and the N spreading codes generated by the spreading code generating circuit, and the N An adder for adding the outputs of the multiplier; and a peak detector for detecting a peak of the output of the adder, wherein the period of the first clock is equal to the period of the clock used for spreading the spread signal, etc. teeth rather, the spreading code wherein each multiplier f input order of said spreading code generated at the generating circuit and the multiplier f input order the spread signal are the same, and the said first clock second The time obtained by dividing the spreading code length by the difference in clock frequency Despreading demodulator, characterized in that it is the same as the data clock period. N (N ≧ 2) switches for holding samples of the spread signal, a switch control circuit for controlling opening / closing of the N switches by inputting a first clock, and N for inputting a second clock A spreading code generating circuit for generating the spreading codes, N multipliers for individually multiplying the outputs of the N switches and the N spreading codes generated by the spreading code generating circuit, and the N An adder for adding the outputs of the multiplier; and a peak detector for detecting a peak of the output of the adder, wherein the period of the first clock is equal to the period of the clock used for spreading the spread signal The input order of the spread codes generated by the spread code generation circuit to the multipliers is opposite to the input order of the spread signals to the multipliers, and the first clock and the second clock The time obtained by dividing the spreading code length by the sum of the frequencies of Despreading demodulator, characterized in that it is the same as Takurokku period.

Images