JP3788796B2 - Despread demodulator - Google Patents

Description

  The present invention receives a spread signal transmitted by frequency spreading a desired signal by an operation using a spread code, and despreads the received spread signal by an operation using a spread code to extract the desired signal. The present invention relates to a despreading demodulator in wireless communication.

  FIG. 16 shows the configuration of a despreading demodulator as the first prior art. In this configuration, the received spread signal is multiplied by the spread code generated by the spread code generation circuit 1002 in the multiplier 1001 and passed through a low-pass filter (LPF) 1003 to remove harmonic components, and the received signal (baseband) Signal). Reference numeral 1004 denotes a synchronization control circuit for matching the phases of the spread code and the spread signal.

  FIG. 17 shows the configuration of a despreading demodulator according to the second prior art, and FIG. 18 shows the characteristics of the signal at point A on the input side and point B on the output side of the peak detector 1114 in the despreading demodulator of FIG. Shows a typical waveform. In this configuration, the received spread signal is converted into a correlation signal by the matched filter 1111 corresponding to the spread code, delayed by the reciprocal of the data clock by the delay line 1112, and the delayed signal and the correlation signal are multiplied by the multiplier 1113. The received signal is obtained by multiplying and then performing peak detection with the peak detector 1114.

The despreading demodulator having the synchronization control circuit of FIG. 16 and the despreading demodulator having the matched filter of FIG. 17 are described in Non-Patent Document 1, for example. The applicant has not yet found prior art documents related to the present invention by the time of filing other than the prior art documents specified by the prior art document information described in this specification.
Marubayashi Gen, Nakagawa Masao, Kawano Ryuji, "Spread Spectrum Communication and its Applications", IEICE, 1998, 94-145, ISBN 4-88562-163-X

  In the despreading demodulator which is the first prior art shown in FIG. 16, it is necessary to match the phase of the spreading code and the spread signal with high accuracy. For this reason, there has been a problem that the configuration of the synchronization control circuit 1004 becomes complicated, and the circuit scale and power consumption increase.

  In the despreading demodulator that is the second prior art shown in FIG. 17, a normal SAW (Surface Acoustic Wave) filter is used as the matched filter 1111. For this reason, there was a problem that the mounting area and the mounting cost increased. In addition, since a matched filter 1111 specialized for a specific spreading code is used, there is a problem that a spreading signal with a different spreading code cannot be demodulated. In addition, when the matched filter 1111 is configured by an on-chip circuit, there is a problem that an area size and power consumption increase.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a low-power despreading demodulator that eliminates the need for external components and does not require synchronization control, thereby enabling portable wireless communication. This contributes to low power and low cost.

The despreading demodulator according to the present invention includes N (N is an integer of 2 or more) sample-and-hold circuits that sample and hold a received spread signal, and a first clock having the same frequency as the clock used for spreading the spread signal. And a sample hold control circuit for controlling the N sample hold circuits to sequentially perform a sample hold operation in synchronization with the first clock, and the N first hold circuits in synchronization with the second clock. A first spreading code generating circuit for generating a spreading code, and a second spreading code for generating N second spreading codes in which the first spreading codes are rearranged in the reverse direction in synchronization with the second clock. Of the N spreading codes output from the spreading code generating circuit and the first spreading code generating circuit or the second spreading code generating circuit, the spreading signal having the newest received order or the spreading signal having the oldest spreading code is received. Signal Polarity is converted and output so that approximately half corresponding to the deviation exhibits two polarity states of inversion and non-inversion during one cycle of the second clock, and the remaining approximately half of the sign is output as it is. A conversion circuit, N multipliers for multiplying the signal output from the sample hold circuit and the spreading code output from the polarity conversion circuit for each corresponding signal, and adding the outputs of the N multipliers An adder to detect, a peak detector to detect a peak of the output of the adder, and each time the peak is detected by the peak detector, the first spreading code generation circuit to the polarity conversion circuit A spread code control circuit that alternately switches between the input of the first spread code and the input of the second spread code from the second spread code generation circuit to the polarity conversion circuit;
The first spreading code generation circuit includes N first flip-flop circuit groups for shifting the first spreading code in synchronization with the second clock, and among the first flip-flop circuit groups. A first exclusive OR circuit for inputting outputs of the plurality of flip-flop circuits, and a flip-flop circuit of the first flip-flop circuit group connected in cascade so as to be openable and closable, and the first exclusive OR circuit Of the first flip-flop circuit group to the input of the first flip-flop circuit of the first flip-flop circuit group so as to be openable and closable. N second flip-flop circuit groups for shifting the second spreading code in the opposite direction to the first spreading code in synchronization with the first clock, and the second flip-flop circuit group. A second exclusive OR circuit for inputting the output of the flip-flop circuit and a flip-flop circuit of the second flip-flop circuit group connected in a cascaded manner, and the output of the second exclusive OR circuit And a second switch group that is openably and closably connected to the input of the first flip-flop circuit in the second flip-flop circuit group, and the spreading code control circuit has the peak detected by the peak detector. Each time it is detected, the control to turn on the first switch group and the control to turn on the second switch group are alternately switched.

  The despreading demodulator according to the present invention also includes N (N is an integer of 2 or more) sample-and-hold circuits that sample-hold the received spread signal, and a first frequency having the same frequency as the clock used for spreading the spread signal. The sample and hold control circuit controls the N sample and hold circuits to sequentially perform the sample holding operation in synchronism with the first clock, and the N sample and hold circuits in synchronization with the second clock. A first spreading code generating circuit for generating one spreading code, and a second spreading code for generating N second spreading codes in which the first spreading codes are rearranged in the reverse direction in synchronization with the second clock. 2 spreading code generation circuits, the signal output from the sample and hold circuit, and the spreading code output from the first spreading code generating circuit or the second spreading code generating circuit are multiplied for each corresponding signal. Among the multiplier output signals of the N multipliers and the multiplier output signals of the N multipliers, approximately half corresponding to either the newer spread signal or the older spread signal in the received order is the second A polarity conversion circuit that converts the polarity so that two polarity states of inversion and non-inversion are exhibited in one cycle of the clock and outputs the output, and outputs the remaining half of the multiplier output signals as they are. An adder for adding outputs, a peak detector for detecting a peak of the output of the adder, and from the first spreading code generation circuit to the multiplier each time the peak is detected by the peak detector A spread code control circuit that alternately switches between the input of the first spread code and the input of the second spread code from the second spread code generation circuit to the multiplier.

  The despreading demodulator according to the present invention also includes N (N is an integer of 2 or more) sample-and-hold circuits that sample-hold the received spread signal, and a first frequency having the same frequency as the clock used for spreading the spread signal. The sample and hold control circuit controls the N sample and hold circuits to sequentially perform the sample holding operation in synchronism with the first clock, and the N sample and hold circuits in synchronization with the second clock. A first spreading code generating circuit for generating one spreading code, and a second spreading code for generating N second spreading codes in which the first spreading codes are rearranged in the reverse direction in synchronization with the second clock. Among the two spread code generation circuits and the sample-and-hold output signals of the N sample-and-hold circuits, the abbreviation corresponding to either the newer spread signal or the older spread signal in the order of reception. A polarity conversion circuit for converting the polarity so that the number exhibits two polarity states of inversion and non-inversion during one period of the second clock, and outputting the remaining half of the sample hold output signals as they are; N multipliers for multiplying the signal output from the polarity conversion circuit and the spreading code output from the first spreading code generating circuit or the second spreading code generating circuit for each corresponding signal, An adder for adding the outputs of the N multipliers; a peak detector for detecting a peak of the output of the adder; and each time the peak is detected by the peak detector, generating the first spreading code A spreading code control circuit for alternately switching the input of the first spreading code from the circuit to the multiplier and the input of the second spreading code from the second spreading code generation circuit to the multiplier; thing A.

  The despreading demodulator of the present invention samples and holds the received spread signal in synchronization with the first clock having the same frequency as the clock used for spreading the spread signal (N is an integer of 2 or more). Among the N sampled and held circuits, the spread code generating circuit for generating N spread codes in synchronization with the second clock, and the N spread codes output from the spread code generating circuit, the received order is Polarity conversion is performed so that approximately half corresponding to either the new spread signal or the old spread signal exhibits two polarity states of inversion and non-inversion during one period of the second clock. The remaining half of the codes are multiplied by the polarity conversion circuit that outputs the signals as they are, the signal output from the sample hold circuit and the spreading code output from the polarity conversion circuit for each corresponding signal N A multiplier for adding the outputs of the N multipliers, a peak detector for detecting the peak of the output of the adder, and the spreading code according to detection of the peak by the peak detector And a clock control circuit for controlling the input of the second clock to the generation circuit.

  The despreading demodulator of the present invention samples and holds the received spread signal in synchronization with the first clock having the same frequency as the clock used for spreading the spread signal (N is an integer of 2 or more). Sample hold circuits, a spread code generation circuit for generating N spread codes in synchronization with the second clock, a signal output from the sample hold circuit, and a spread code output from the spread code generation circuit Among the N multipliers and the output signals of the N multipliers, whichever is the newest spread signal or the oldest spread signal. So that approximately half of the second clock exhibits polarity inversion and non-inversion in one cycle of the second clock, and outputs the remaining half of the multiplier output signals as they are. polarity Conversion circuit, an adder for adding the outputs of the polarity conversion circuit, a peak detector for detecting the peak of the output of the adder, and the spreading code generation circuit according to detection of the peak by the peak detector And a clock control circuit for controlling the input of the second clock.

  The despreading demodulator of the present invention samples and holds the received spread signal in synchronization with the first clock having the same frequency as the clock used for spreading the spread signal (N is an integer of 2 or more). Among the sample and hold circuits, the spread code generation circuit that generates N spread codes in synchronization with the second clock, and the sample and hold output signals of the N sample and hold circuits, the one in which the received order is newer The half of the spread signal or the older spread signal of which is approximately half of the two spread states are inverted and output during one period of the second clock. The remaining half of the sample-and-hold output signals are output as they are, and a polarity conversion circuit, a signal output from the polarity conversion circuit, and a spread code output from the spread code generation circuit are paired. N multipliers for each signal to be multiplied, an adder for adding the outputs of the N multipliers, a peak detector for detecting a peak of the output of the adder, and the peak by the peak detector And a clock control circuit for controlling the input of the second clock to the spreading code generation circuit in response to detection of.

In the configuration example of the despreading demodulator of the present invention, the clock control circuit may be configured to input the second clock to the spreading code generation circuit every time the peak is detected by the peak detector. Switching between stop and restart alternately.
In the configuration example of the despreading demodulator of the present invention, the clock control circuit receives the second clock input to the spreading code generation circuit when the peak is detected by the peak detector. It stops for a certain time.
Also, in one configuration example of the despreading demodulator of the present invention, the spreading code generating circuit is configured by a flip-flop circuit, an exclusive OR circuit, and a switch for controlling the output path of the flip-flop circuit. is there.
Also, in one configuration example of the despreading demodulator of the present invention, the first spreading code generation circuit, the second spreading code generation circuit, and the spreading code control circuit are configured by a DSP. .
Also, one configuration example of the despreading demodulator of the present invention is such that the spreading code generation circuit and the clock control circuit are configured by a DSP.

  According to the present invention, a sample and hold circuit, a sample and hold control circuit, a first spreading code generation circuit, a second spreading code generation circuit, a polarity conversion circuit, a multiplier, an adder, and peak detection And a spread code control circuit constitute a despread demodulator that uses a spread code generation circuit that does not require external components and does not require synchronization control between the spread signal and the spread code. Thus, a low-power despreading demodulator can be realized, and a low-power and low-cost portable radio equipped with the despreading demodulator can be realized. In addition, the first spreading code generation circuit that generates N first spreading codes in synchronization with the second clock and the first spreading codes are rearranged in the reverse direction in synchronization with the second clock. A second spreading code generating circuit for generating N second spreading codes, and a first spreading code from the first spreading code generating circuit to the polarity conversion circuit each time a peak is detected by the peak detector And a spread code control circuit for alternately switching the second spread code generation circuit and the second spread code input to the polarity conversion circuit, the correlation peak signal from the adder becomes the first clock. Since the correlation peak signal can be obtained frequently without depending on the second clock and the spreading code, despread demodulation can be performed even when the data clock frequency of the data to be transmitted is high. Speed up It is possible. Furthermore, by providing a polarity conversion circuit, a peak always appears in the output of the adder even when the received signal, which is the output of the peak detector, changes from “1” to “0” or “0” to “1”. Therefore, the jitter of the received signal can be greatly reduced.

  In addition, a despreading demodulator is composed of a sample hold circuit, a spread code generation circuit, a polarity conversion circuit, a multiplier, an adder, a peak detector, and a clock control circuit, eliminating the need for external components. Since the spread signal is despread demodulated using a spread code generation circuit that does not require synchronization control between the spread signal and the spread code, a low-power despread demodulator can be realized, and the despread demodulation can be realized. Low power and low cost can be realized for portable wireless devices equipped with devices. Further, by providing a clock control circuit that controls the input of the second clock to the spread code generation circuit in accordance with the detection of the peak by the peak detector, the correlation peak signal from the adder is the first clock, the second Since the correlation peak signal can be obtained frequently without depending on the clock and spreading code of the data, despread demodulation can be performed even when the data clock frequency of the data to be transmitted is high, and the data clock frequency is increased. be able to. Furthermore, by providing a polarity conversion circuit, a peak always appears in the output of the adder even when the received signal, which is the output of the peak detector, changes from “1” to “0” or “0” to “1”. Therefore, the jitter of the received signal can be greatly reduced.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration of a despreading demodulator according to a first embodiment of the present invention. The despread demodulator according to the present embodiment includes N sample hold circuits 1a to 1g (N is an integer equal to or larger than 2 and 7 in the present embodiment) for holding an input spread signal as a sample, A sample hold control circuit 2 that controls the sample hold circuits 1a to 1g to sequentially perform the sample hold operation with the clock f1 as an input and a shift register that shifts the output signal from the sample hold control circuit 2 in synchronization with the clock f1 are configured. Flip-flop circuits 3a to 3f, a spread code generating circuit 4 for generating N spread codes in synchronization with the second clock f2, and among the N spread codes output from the spread code generating circuit 4, Almost half corresponding to either the newer spread signal or the older spread signal received by the despreading demodulator is inverted or not in one cycle of the clock f2. The polarity conversion circuit 101 outputs the signal after converting the polarity so as to exhibit two polarity states, and outputs the remaining half of the code as it is, and the diffusion signal and the polarity conversion circuit output from the sample hold circuits 1a to 1g. N multipliers 5 a to 5 g that multiply the spread code output from 101 for each corresponding signal, an adder 6 that adds the output signals of the multipliers 5 a to 5 g, and an output signal of the adder 6 And a peak detector 7 for detecting a peak value.

The first clock f1 is a clock having the same frequency as the clock used for spreading the spread signal on the transmission side. The second clock f2 is a clock having the same frequency as the clock used for generating the spread code on the transmission side.
In this embodiment, N = 7, and the sample hold circuits 1a to 1g, the flip-flop circuits 3a to 3g, and the multipliers 5a to 5g each have N = 7. However, N is 2 or more. Any integer is acceptable.

  FIG. 2 shows an example of the configuration of the multiplier 5 (5a to 5g). Each multiplier 5 includes NMOS transistors MN1 to MN7, and is configured by a two-stage vertically stacked differential circuit. The spread code output from the polarity conversion circuit 101 and the spread signal output from the sample hold circuit 1 (1a to 1g) are differential signals. The spreading code output from the polarity conversion circuit 101 is input to the differential circuit including the transistors MN1 and MN2 and the differential circuit including the transistors MN3 and MN4 in opposite phases, and is output from the sample hold circuit 1 (1a to 1g). The spread signal is input to a differential circuit composed of transistors MN5 and MN6. Thereby, the spread code and the spread signal are multiplied, and the multiplication result is output in the current mode.

  FIG. 3 shows an example of the configuration of the adder 6. The adder 6 includes load resistors 31 and 32 to which a power supply voltage is applied at one end and a differential output of the multipliers 5a to 5g is input to the other end. The differential outputs of the multipliers 5a to 5g output in the current mode are converted into voltages by the load resistors 31 and 32 in the adder 6 and added to be output in the voltage mode. The output signal of the adder 6 is peak detected by the peak detector 7 and output as a received signal (baseband signal).

  FIG. 4 shows an example of the configuration of the spread code generating circuit 4. The spread code generation circuit 4 includes exclusive OR circuits 41 and 42, flip-flop circuits 43a to 43n constituting shift registers that shift in synchronization with the clock f2, exclusive OR circuits 41 and 42, and flip-flop circuits. The switches 44a to 44p for turning on / off the output paths 43a to 43n and the spread code control circuit 45 for controlling the switches 44a to 44p are configured.

  In the present embodiment, the outputs of the flip-flop circuits 43a and 43c are taken into the exclusive OR circuit 41, and the operation result of the exclusive OR circuit 41 is returned to the input of the flip-flop 43a, whereby the first spreading code is obtained. appear. On the other hand, the outputs of the flip-flop circuits 43j and 43i are taken into the exclusive OR circuit 42, and the operation result of the exclusive OR circuit 42 is returned to the input of the flip-flop 43h, thereby rearranging the first spreading codes in reverse order. A second spreading code is generated.

  That is, the first exclusive OR circuit 41, the first flip-flop circuit group including the flip-flop circuits 43a to 43g, and the first switch group including the switches 44a to 44g and 44o are the first spreading code generation circuit 40. -1 and the second exclusive OR circuit 42, the second flip-flop circuit group including the flip-flop circuits 43h to 43n, and the second switch group including the switches 44h to 44n and 44p are the first diffusion. A second spreading code generation circuit 40-2 that generates a second spreading code in which a signal is shifted in a direction opposite to that of the first spreading code generated by the code generation circuit 40-1 is configured. By simply changing the combination of inputs to the exclusive OR circuits 41 and 42, it is possible to form spreading code generation circuits corresponding to various spreading codes. In this embodiment, since the spread signal is sampled and held in the order of the sample hold circuits 1a, 1b, 1c, 1d, 1e, 1f, and 1g, the signals sampled and held by the sample hold circuits 1a to 1g are inputted. The arrangement order is reverse to that of the spread signal. Therefore, in order to obtain the correlation between the spread signal input to the despread demodulator and the spread code, the order of the spread codes is reversed in accordance with the order of the spread signals sampled and held by the sample hold circuits 1a to 1g. That's fine. That is, the first spreading code output from the first spreading code generation circuit 40-1 may be arranged in the reverse order of the spreading codes used for spreading the spread signal on the transmission side.

  The spread code control circuit 45 controls the switches 44 a to 44 p according to the peak detection by the peak detector 7. When the switches 44a to 44g and 44o are on, the switches 44h to 44n and 44p are off, and the first spreading code generated by the first spreading code generation circuit 40-1 is shifted from left to right in FIG. I will do it. Conversely, when the switches 44a to 44g and 44o are off, the switches 44h to 44n and 44p are on, and the second spreading code generated by the second spreading code generation circuit 40-2 is from right to left in FIG. Shift to.

  The spread code control circuit 45 alternately switches between the first switch group (44a to 44g, 44o) and the second switch group (44h to 44n, 44p) each time a peak is detected by the peak detector 7. Switch the direction of spreading code shift. Of the first spreading code generation circuit 40-1 or the second spreading code generation circuit 40-2, the corresponding multipliers 5a to 5g from the flip-flop circuit group of one spreading code generation circuit whose switch group is on. A spreading code is input to the. In addition, since the output of this flip-flop circuit group is simultaneously input to the flip-flop circuit group of the other spreading code generation circuit whose switch group is off, when switching the switch group, it is output at that time. The spreading code starts to shift in the reverse direction while retaining the spreading code.

  FIG. 5 shows waveforms during the operation of the spreading code generation circuit of FIG. 4 (in this example, the spreading code of PN7 {1-1111-1-1}). FIG. 5A shows a first spreading code generated when the first spreading code generation circuit 40-1 is in an ON state, and FIG. 5B shows a second spreading code generation circuit 40-2 in an ON state. The second spreading code generated at the time is shown.

Hereinafter, the operation of the despreading demodulator of this embodiment will be described in detail.
The sample and hold control circuit 2 receives the first clock f1 and samples the spread signal for one clock every clocks equal to the number of the multipliers 5a to 5g (in this embodiment, every N = 7 clocks). A sample hold control signal to be held is generated.
The flip-flop circuits 3a to 3f constituting the shift register shift the sample hold control signal output from the sample hold control circuit 2 to the respective sample hold circuits 1b to 1g while shifting the sample hold control signal to the right in FIG. 1 in synchronization with the clock f1. Output.

  Assuming that the sample hold circuit 1a holds the spread signal in response to the sample hold control signal, the sample hold circuit 1b samples and holds the spread signal with a delay of one cycle of the clock f1, and further only one cycle of the clock f1. The sample hold circuit 1c samples and holds the spread signal with a delay. As described above, the sample hold circuits 1a to 1g sequentially perform the sample hold operation in synchronization with the clock f1.

Therefore, the new spread signal received is updated and held by the sample hold control circuit 2 and the flip-flop circuits 3a to 3f at the same number of clocks as the number of multipliers at the inputs of the multipliers 5a to 5g. . On the other hand, a spread code is generated from the spread code generation circuit 4 in synchronization with the clock f 2 and input to the polarity conversion circuit 101.
The spread signal output from the sample hold circuits 1a to 1g and the spread code output from the spread code generation circuit 4 via the polarity conversion circuit 101 are multiplied for each corresponding signal by the multipliers 5a to 5g. The multiplication results of the devices 5a to 5g are added by the adder 6 and output.

  Here, the operation when the polarity conversion circuit 101 is omitted and the spread code generation circuit 4 and the multipliers 5a to 5g are directly connected will be described. Due to the spread code from the spread code generation circuit 4, the phase of the spread signal and the spread code coincide with each other at least once in the time interval of the spread code length, and a correlation peak signal is obtained from the adder 6. When the peak detector 7 detects this peak, the signal path between the flip-flops in the spread code generation circuit 4 is switched by the spread code control circuit 45, and the direction in which the spread code is shifted is switched.

  When the spreading code shifts in one direction, the next correlation peak signal appears when the spreading code shifts and the same spreading code pattern is input to the multipliers 5a to 5g, and the spreading code length Once every time interval. In the present embodiment, every time a peak is detected by the peak detector 7, the direction in which the spreading code is shifted is switched. For this reason, when a correlation peak signal is obtained, the spreading code control circuit 45 switches the shifting direction of the spreading code, and the spreading code shifted in the reverse direction is input to the multipliers 5a to 5g.

  During the delay time from when the spread code control circuit 45 detects the correlation peak signal to when the spread code starts to shift in the reverse direction, the spread code being input to the multipliers 5a to 5g is shifted in the shift direction before switching. I keep doing it. For this reason, when the spread code pattern when the correlation peak signal is detected and the shift direction are switched, the phase of the spread code input to the multipliers 5a to 5g is shifted, but is input to the multipliers 5a to 5g. Since the spreading code starts to shift in the reverse direction, the phase of the spreading signal and the spreading code again coincide with each other shortly after the shift direction is switched, and the next correlation peak signal is obtained from the adder 6. The spread code control circuit 45 switches the shift direction of the spread code to the reverse direction when the peak detector 7 detects the next correlation peak signal.

Thereafter, by repeating the same control, a correlation peak signal can be frequently obtained regardless of the spreading code length to be used.
In this configuration, a positive / negative correlation value output is obtained from the adder 6 corresponding to “1” and “0” of the digital data sent from the transmission side. The peak detector 7 outputs a digital received signal (baseband signal) by detecting the peak of the output signal of the adder 6.

  Thus, the correlation peak signal from the adder 6 does not depend on the clocks f1 and f2 or the spreading code to be used by switching the shift direction of the spreading code in the spreading code generation circuit 4 in accordance with the detection of the peak by the peak detector 7. Since the configuration is adopted, it is possible to increase the data rate of the signal to be transmitted.

  However, in a configuration in which polarity conversion by the polarity conversion circuit 101 is not performed, for example, the despreading demodulator proposed in Japanese Patent Application No. 2002-352019, peak detection becomes impossible during transition of transmission data, and a detection impossible period occurs. For example, in the example of FIG. 6, when the received signal that is the output of the peak detector 7 (point B in FIG. 1) transitions from “1” to “0”, the output of the adder 6 (point A in FIG. 1). It takes time until the positive peak P1 corresponding to the received signal “1” appearing in FIG. 5 is interrupted and the negative peak P0 corresponding to the received signal “0” appears. As a result, there is a problem that large jitter occurs in the received signal after demodulation. Further, there is a problem that the transmission capacity cannot be increased.

  On the other hand, in this embodiment, a polarity conversion circuit 101 is provided between the spread code generation circuit 4 and the multipliers 5a to 5g. The polarity conversion circuit 101 has the second half of the N spreading codes output from the spreading code generation circuit 4 corresponding to either the newer spreading signal or the older spreading signal received in the second order. About half of the codes are converted and output so as to exhibit two polarity states of inversion and non-inversion during one period of the clock f2, and the remaining codes excluding the almost half of the N spreading codes are output. Output as is.

  The polarity conversion circuit 101 operates based on the third clock f3. FIG. 7 shows an example of the timing of the second clock f2 and the third clock f3. The clock f2 and the clock f3 are synchronized. The states of the N spread codes output from the spread code generation circuit 4 change in synchronization with the clock f2. In the example of FIG. 7C, “A”, “B”, “C”, “D”, “E”, “F”, “G”, “H”,... Thus, the state of the spreading code has changed.

  When the clock f3 changes from “0” to “1”, the polarity conversion circuit 101 reverses the polarity state of the substantially half of the spreading codes from non-inverted (“+” in FIG. 7D) (FIG. 7 ( In d), when the clock f3 changes from “1” to “0”, the polarity state of the substantially half of the spread codes is changed from inverted to non-inverted. That is, approximately half of the spreading codes exhibit two polarity states of inversion and non-inversion during one cycle of the clock f2, so that the clock f3 is changed from “0” to “1” during one cycle of the clock f2. The timings of the clock f2 and the clock f3 are set so as to change to “1” or “0”.

In the present embodiment, the clock f3 is ½ of the clock f2, but two polarity states, inverted and non-inverted, are present in the substantially half of the spread codes during one cycle of the clock f2. The clock f3 and the clock f2 may be set equal to each other, or the clock f3 may be larger than the clock f2.
The approximate half may be an integer obtained by dividing N by 2 when N is an even number, but when N is an odd number, a value obtained by adding 1 to an integer obtained by dividing N by 2 or an integer from 1 Any of the values obtained by subtracting. For example, approximately half of N = 7 is either 3 or 4.

  Further, when the latest spread signal is held in the sample hold circuit 1d, if the spread signal is arranged in the newest order, the sample hold circuits are in the order of 1d, 1c, 1b, 1a, 1g, 1f, 1e. The half of the spreading codes corresponding to the newer one is a spreading code corresponding to the multipliers 5d, 5c, 5b, 5a (when the half is about 4) or a spreading code corresponding to the multipliers 5d, 5c, 5b ( About half is 3). At the time when the latest spread signal is held in the sample and hold circuit 1a, the spread code corresponding to the multipliers 5a, 5g, 5f, and 5e (when approximately half is 4) or the multipliers 5a, 5g, and 5f is supported. Spreading code (when approximately half is 3).

  On the other hand, when the latest spread signal is held in the sample-and-hold circuit 1d, if the sample-and-hold circuits are arranged in order from the oldest spread signal, the order becomes 1e, 1f, 1g, 1a, 1b, 1c, and 1d. The half of the spreading codes corresponding to the older one is the spreading code corresponding to the multipliers 5e, 5f, 5g, 5a (when the half is approximately 4) or the spreading code corresponding to the multipliers 5e, 5f, 5g ( About half is 3). At the time when the latest spread signal is held in the sample hold circuit 1a, the spread code corresponding to the multipliers 5b, 5c, 5d, and 5e (when approximately half is 4) or the multipliers 5b, 5c, and 5d is supported. Spreading code (when approximately half is 3).

  As described above, approximately half of the spreading codes to be subjected to polarity conversion by the polarity conversion circuit 101 are determined by the position of the sample hold circuit in which the latest spread signal is held. For this reason, the polarity conversion circuit 101 checks the position of the sample and hold circuit in which the latest spread signal is held based on the sample and hold control signals output from the sample and hold control circuit 2 and the flip-flop circuits 3a to 3f. Based on the position, approximately half of the spreading codes corresponding to the newer or older spread signal are determined.

  FIG. 8 shows characteristic signal waveforms at points A and B in FIG. FIG. 8 shows a case where approximately half of the spreading codes whose polarity is converted by the polarity converting circuit 101 correspond to approximately half of the older spread signal. As can be seen from FIG. 8, when the received signal, which is the output of the peak detector 7 (point B in FIG. 1), transitions from “1” to “0”, the polarity conversion circuit 101 does not perform polarity conversion. In comparison with FIG. 1, a negative peak P0 ′ corresponding to the received signal “0” appears earlier in the output of the adder 6 (point A in FIG. 1). The reason is that in the middle of the transition of the received signal from “1” to “0”, approximately half of the new spread signal has already changed to “0”, while approximately half of the old spread signal is Although still “1”, the polarity of the spreading code corresponding to approximately half of the older spread signal is inverted so that the older half of the spread signal is substantially changed to “0”. Because it becomes. For the same reason, when the received signal transitions from “0” to “1”, the positive peak corresponding to the received signal “1” is higher in the adder 6 than when the polarity conversion by the polarity conversion circuit 101 is not performed. Appears early in the output.

  FIG. 9 shows a signal waveform when approximately half of the spreading codes whose polarity is converted by the polarity converting circuit 101 correspond to approximately half of the new spread signal. As can be seen from FIG. 9, when the received signal, which is the output (point B) of the peak detector 7, transitions from “1” to “0”, the received signal is compared with the case where the polarity conversion by the polarity conversion circuit 101 is not performed. A new positive peak P 1 ′ corresponding to “1” appears at the output (point A) of the adder 6. The reason is that by inverting the polarity of the spreading code corresponding to approximately half of the new spread signal, approximately half of the new spread signal is substantially changed to “1”. For the same reason, when the received signal transitions from “0” to “1”, a new negative peak corresponding to the received signal “0” is added to the adder compared to the case where the polarity conversion by the polarity conversion circuit 101 is not performed. Appears at output 6.

According to the present embodiment, despread demodulation can be performed without performing synchronization control between the spread signal and the spread code. In this embodiment, since the correlation peak signal from the adder 6 does not depend on the clocks f1 and f2 and the spreading code to be used, the data rate of the signal to be transmitted can be increased.
Furthermore, in this embodiment, even when the received signal changes from “1” to “0” or from “0” to “1”, a peak always appears at the output of the adder 6, so that detection cannot be performed. There is no. As a result, in this embodiment, the jitter of the received signal can be greatly reduced.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 10 is a block diagram showing the configuration of the despreading demodulator according to the second embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. The present embodiment has a configuration in which the installation location of the polarity conversion circuit is changed with respect to the despread demodulator of the first embodiment. In other words, the polarity conversion circuit 102 according to the present embodiment is provided between the multipliers 5 a to 5 g and the adder 6.

Of the N multiplier output signals of the multipliers 5a to 5g, the polarity conversion circuit 102 is approximately half corresponding to either the newer spread signal or the older spread signal received by the despread demodulator. Substantially half of the multiplier output signals are converted and output so as to exhibit two inverted and non-inverted polarity states in one cycle of the second clock f2, and among the N multiplier output signals, The remaining signals excluding approximately half are output as they are. The polarity conversion circuit 102 operates based on the third clock f3, and the latest spread signal is held based on the sample hold control signal output from the sample hold control circuit 2 and the flip-flop circuits 3a to 3f. As in the first embodiment, the position of the sample and hold circuit is checked, and approximately half of the multiplier output signals corresponding to the newer or older one of the spread signals are determined based on this position.
Thus, also in this embodiment, the same effect as that of the first embodiment can be obtained.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 11 is a block diagram showing the configuration of the despreading demodulator according to the third embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. The present embodiment has a configuration in which the installation location of the polarity conversion circuit is changed with respect to the despread demodulator of the first embodiment. That is, the polarity conversion circuit 103 according to the present embodiment is provided between the sample hold circuits 1a to 1g and the multipliers 5a to 5g.

The polarity conversion circuit 103 is an abbreviation corresponding to either the newer spread signal or the older spread signal in the order received by the despread demodulator among the N sample hold output signals of the sample hold circuits 1a to 1g. The half of the sample and hold output signals are converted in polarity so that half of them exhibit two polarity states of inversion and non-inversion during one period of the second clock f2, and the N sample and hold output signals are output. The remaining signals excluding the approximately half are output as they are. The polarity conversion circuit 103 operates on the basis of the third clock f3, and on the basis of the sample hold control signal, the position of the sample hold circuit where the latest spread signal is held is checked. Determining approximately half of the sample and hold output signals corresponding to the newer or older one is the same as in the first embodiment. Thus, also in this embodiment, the same effect as that of the first embodiment can be obtained.
In the first to third embodiments, in order to obtain the correlation between the spread signal and the spread code, the spread order of the spread codes is reversed in accordance with the spread order of the spread signals sampled and held by the sample hold circuits 1a to 1g. However, the signals sampled and held by the sample hold circuits 1a to 1g may be arranged in the same order as the input spread signals. In order to arrange them in the same order as the input spread signals, the output of the sample hold control circuit 2 shown in FIGS. 1, 10, and 11 is the flip-flop circuit 3f, and the output of the flip-flop circuit 3f is the flip-flop circuit 3e. The output of the flip-flop circuit 3e is the flip-flop circuit 3d, the output of the flip-flop circuit 3d is the flip-flop circuit 3c, the output of the flip-flop circuit 3c is the flip-flop circuit 3b, and the output of the flip-flop circuit 3b is the flip-flop. What is necessary is just to connect so that each may be input into the circuit 3a. In this case, it is not necessary to reverse the arrangement order of the spread codes, and the first spread code output from the first spread code generation circuit 40-1 was used for spreading the spread signal on the transmission side. The same order as the spreading codes may be used.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 12 is a block diagram showing a configuration of a despreading demodulator according to the fourth embodiment of the present invention. The despread demodulator of the present embodiment includes N (N = 7 in the present embodiment) sample and hold circuits 8a to 8g that hold the input spread signal in synchronization with the first clock f1, Of the N spreading codes generated from the N spreading codes in synchronization with the second clock f2, and the N spreading codes output from the spreading code generating circuit 9, the order received by the despreading demodulator is Polarity conversion is performed so that approximately half corresponding to either the new spread signal or the old spread signal exhibits two polarity states of inversion and non-inversion during one period of the clock f2, and the remaining approximately The polarity conversion circuit 104 that outputs half of the codes as they are, and N multipliers that multiply the signals output from the sample hold circuits 8a to 8g and the spreading codes output from the polarity conversion circuit 104 for each corresponding signal. And 0A～10g, an adder 11 for adding the output signals of the multipliers 10A-10G, made up of the peak detector 12 for detecting a peak value of the output signal of the adder 11. In the present embodiment, N = 7 and seven sample-hold circuits and seven multipliers are shown, but N may be an integer of 2 or more.

  FIG. 13 shows an example of the configuration of the spread code generating circuit 9 of the present embodiment. The spread code generation circuit 9 includes an exclusive OR circuit 91, flip-flop circuits 92a to 92g that constitute a shift register that shifts the output of the exclusive OR circuit 91 in synchronization with the clock f2, and a peak detector 12 And a clock control circuit 93 for controlling the input of the second clock f2 to the flip-flop circuits 92a to 92g in accordance with the detection of the peak. In the present embodiment, the outputs of the flip-flop circuits 92a and 92c are taken into the exclusive OR circuit 91, and the operation result of the exclusive OR circuit 91 is returned to the input of the flip-flop circuit 92a, thereby spreading code (this embodiment). In this form, PN7) is generated.

  Various spreading codes can be generated simply by changing the combination of inputs to the exclusive OR circuit 91. When the number of sample and hold circuits 8a to 8g and multipliers 10a to 10g is increased, the number of flip-flop circuits 92 of the spread code generation circuit 9 may be increased accordingly. In the present embodiment, unlike the first to third embodiments, the signals sampled and held by the sample hold circuits 8a to 8g are arranged in the same order as the input spread signals. Therefore, it is not necessary to reverse the arrangement order of the spreading codes, and the spreading code output from the spreading code generation circuit 9 may be the same as the spreading code used for spreading the spread signal on the transmission side.

  Hereinafter, the operation of the despreading demodulator of this embodiment will be described in detail. The spread signal is sampled and held by the sample and hold circuits 8a to 8g and inputted to the multipliers 10a to 10g. At this time, the spread signals received and held by the sample hold circuits 8a to 8g are input to the multipliers 10a to 10g, and are also input to the next stage sample hold circuit and held at the cycle of the clock f1 synchronized with the spread signals. The spread signal thus shifted is shifted in the cycle of the clock f1. With the above operation, the spread signal is supplied to the multipliers 10a to 10g by the sample and hold circuits 8a to 8g with a delay of one cycle of the clock f1. In the present embodiment, the spread signals corresponding to the 7-chip rate are always input to the multipliers 10a to 10 by the sample and hold circuits 8a to 8g. The 7-chip rate spread signal is updated in synchronization with the clock f1.

  On the other hand, the spread code generation circuit 9 outputs the spread code in synchronization with the clock f2. The spread codes output from the flip-flop circuits 92 a to 92 g of the spread code generation circuit 9 are output to the polarity conversion circuit 104. The flip-flop circuits 92a to 92g are connected in cascade and constitute a shift register. Therefore, the spread code is output to the polarity conversion circuit 104 while shifting in the right direction in FIG. 13 in synchronization with the clock f2.

  The polarity conversion circuit 104 is an abbreviation corresponding to either the newer spread signal or the older spread signal in the order received by the despreading demodulator among the N spread codes output from the spread code generation circuit 9. The substantially half of the codes are polarity-converted and output so that the half exhibits two polarity states of inversion and non-inversion during one cycle of the second clock f2, and the approximately half of the N spreading codes are excluded. The remaining codes are output as they are.

  In the present embodiment, the latest spread signal is always held in the sample hold circuit 8a, and the oldest spread signal is always held in the sample hold circuit 8g. Therefore, the approximately half of the spreading codes corresponding to the newer one of the spread signals corresponds to the spreading code corresponding to the multipliers 10a, 10b, 10c and 10d (when approximately half is 4) or the multipliers 10a, 10b and 10c. Spreading codes (when approximately half is 3), and approximately half of the spreading codes corresponding to the older spread signal are the spreading codes corresponding to the multipliers 10g, 10f, 10e, 10d (approximately half are 4). Or a spreading code corresponding to the multipliers 10g, 10f, 10e (when approximately half is 3). The polarity conversion circuit 104 operates based on the third clock f3 as in the first embodiment.

The spread signals output from the sample hold circuits 8a to 8g and the spread code output from the polarity conversion circuit 104 are multiplied for each corresponding signal by the multipliers 10a to 10g, and the multiplication results of the multipliers 10a to 10g are obtained. The signals are added by the adder 11 and output.
The peak detector 12 outputs a digital reception signal (baseband signal) by detecting the peak of the output signal of the adder 11.

  As described in the first embodiment, a correlation peak signal (referred to as a first correlation peak signal) is obtained from the adder 11 at the moment when the phases of the spread signal and the spread code coincide. When the peak detector 12 detects the first correlation peak signal, the clock control circuit 93 stops the input of the clock f2 to the flip-flop circuits 92a to 92g of the spread code generation circuit 9. Thus, the spread code is held in the flip-flop circuits 92a to 92g without shifting.

  During the delay time from when the peak detector 12 detects the first correlation peak signal until the spread code shift actually stops, the phase of the spread signal and the spread code is the frequency of the difference between the clock f1 and the clock f2. It keeps changing. For this reason, when the shift of the spread code is stopped, the phase of the spread signal and the spread code is shifted as compared with the case where the first correlation peak signal is detected. Slightly advanced phase.

  Even after the spread code shift is stopped, the spread signal is shifted in synchronism with the clock f1, so that the phase of the spread signal and the spread code changes at the speed of f1, and is delayed from the spread code. The phase of the spread signal changes in the direction of the lead phase. When the spread code shift is stopped, the spread code phase is only slightly advanced with respect to the spread signal, so the spread code and the spread code are again in phase soon after the spread code shift stop. , A correlation peak signal (referred to as a second correlation peak signal) is obtained from the adder 11.

  The clock control circuit 93 stops the input of the clock f2 to the spread code generation circuit 9 according to the first correlation peak signal, and then detects the second correlation peak signal by the peak detector 12 and then detects the spread code. The input of the clock f2 to the flip-flop circuits 92a to 92g of the generation circuit 9 is resumed. During the delay time from when the peak detector 12 detects the second correlation peak signal until the spread code shift is actually resumed, the phase of the spread signal and the spread code is the frequency of the difference between the clock f1 and the clock f2. It keeps changing. For this reason, when the shift of the spread code is resumed, there is a shift in the phase of the spread signal and the spread code compared to when the second correlation peak signal is detected. Slightly advanced phase.

  After resuming the shift of the spread code, the phase of the spread signal and the spread code starts to change again so that the spread code phase is advanced with respect to the spread signal by the frequency difference between f1 and f2. When the spread code shift is resumed, the phase of the spread signal is only slightly advanced with respect to the spread code, so that the spread signal and the spread code are again in phase soon after the spread code shift resumes. , A correlation peak signal (referred to as a third correlation peak signal) is obtained from the adder 11.

The clock control circuit 93 resumes the input of the clock f2 to the spread code generation circuit 9 in response to the second correlation peak signal, and when the third correlation peak signal is detected by the peak detector 12, the spread code The input of the clock f2 to the generation circuit 9 is stopped.
Thereafter, the correlation peak signal can be frequently obtained by repeating the same control.

  In the configuration in which the clock control circuit is omitted in the despreading demodulator of FIG. 12, the period at which the correlation peak signal is obtained depends on the sum frequency or difference frequency of the clock f1 and the clock f2 and the code length of the spreading code to be used. However, in this embodiment, a correlation peak signal can be obtained without depending on the clocks f1 and f2 and the spreading code to be used. Characteristic signal waveforms at the output of the adder 11 (point A in FIG. 12) and the output of the peak detector 12 (point B in FIG. 12) are the same as those in FIGS.

According to the present embodiment, as in the first embodiment, despread demodulation can be performed without performing synchronization control between the spread signal and the spread code. In this embodiment, since the correlation peak signal from the adder 11 does not depend on the clocks f1 and f2 and the spreading code to be used, the data rate of the signal to be transmitted can be increased.
Furthermore, in this embodiment, even when the received signal changes from “1” to “0” or from “0” to “1”, a peak always appears at the output of the adder 11, so that detection becomes impossible. There is no. As a result, in this embodiment, the jitter of the received signal can be greatly reduced.

  In this embodiment, every time a correlation peak signal from the adder 11 is detected, the input of the clock f2 to the spread code generation circuit 9 is stopped / restarted. However, the correlation peak signal is detected and spread. The same effect can be obtained even if the input of the clock f2 is resumed after waiting for a certain time without detecting the next correlation peak signal after the input of the clock f2 to the code generation circuit 9 is stopped.

[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described. FIG. 14 is a block diagram showing a configuration of a despreading demodulator according to the fifth embodiment of the present invention. The same components as those in FIG. 12 are denoted by the same reference numerals. This embodiment has a configuration in which the installation location of the polarity conversion circuit is changed with respect to the despreading demodulator of the fourth embodiment. That is, the polarity conversion circuit 105 of the present embodiment is provided between the multipliers 10 a to 10 g and the adder 11.

Of the N multiplier output signals of the multipliers 10a to 10g, the polarity conversion circuit 105 has approximately half of the N spread signals corresponding to either the new spread signal or the old spread signal received by the despread demodulator. Substantially half of the multiplier output signals are converted and output so as to exhibit two inverted and non-inverted polarity states in one cycle of the second clock f2, and among the N multiplier output signals, The remaining signals excluding approximately half are output as they are. The polarity conversion circuit 105 operates based on the third clock f3 as in the fourth embodiment. Of the N multiplier output signals of the multipliers 10a to 10g, approximately half of the multiplier output signals corresponding to the newer one of the spread signals are output signals of the multipliers 10a, 10b, 10c, and 10d (approximately half of them). 4) or output signals of the multipliers 10a, 10b, and 10c (when approximately half is 3), and approximately half of the multiplier output signals corresponding to the older spread signal are the multipliers 10g, 10f, 10e, 10d output signals (when approximately half is 4) or multipliers 10g, 10f, 10e (when approximately half is 3).
Thus, also in this embodiment, the same effect as that of the fourth embodiment can be obtained.

[Sixth Embodiment]
Next, a sixth embodiment of the present invention will be described. FIG. 15 is a block diagram showing the configuration of a despreading demodulator according to the sixth embodiment of the present invention. The same components as those in FIG. 12 are denoted by the same reference numerals. This embodiment has a configuration in which the installation location of the polarity conversion circuit is changed with respect to the despreading demodulator of the fourth embodiment. That is, the polarity conversion circuit 106 of the present embodiment is provided between the sample hold circuits 8a to 8g and the multipliers 10a to 10g.

The polarity conversion circuit 106 is an abbreviation corresponding to either the newer spread signal or the older spread signal received in the despreading demodulator among the N sample hold output signals of the sample hold circuits 8a to 8g. The half of the sample and hold output signals are converted in polarity so that half of them exhibit two polarity states of inversion and non-inversion during one period of the second clock f2, and the N sample and hold output signals are output. The remaining signals excluding the approximately half are output as they are. The polarity conversion circuit 106 operates based on the third clock f3 as in the fourth embodiment. Of the N sample and hold output signals of the sample and hold circuits 8a to 8g, approximately half of the output signals corresponding to the newer one of the spread signals are the output signals of the sample and hold circuits 8a, 8b, 8c, and 8d (approximately half of the output signals). 4) or the output signals of the sample-and-hold circuits 8a, 8b, and 8c (when approximately half is 3), and the approximately half of the output signals corresponding to the older spread signal are the sample-and-hold circuits 8g, 8f, 8e and 8d output signals (when approximately half is 4) or sample and hold circuits 8g, 8f and 8e (when approximately half is 3).
Thus, also in this embodiment, the same effect as that of the fourth embodiment can be obtained.

  The sample hold control circuit 2, the spread code generation circuit 4, and the spread code control circuit 45 of the first to third embodiments can be configured by a DSP (Digital Signal Processor), Further, the spread code generation circuit 9 and the clock control circuit 93 according to the fourth to sixth embodiments can be configured by a DSP.

  The present invention receives a spread signal transmitted by frequency spreading a desired signal by an operation using a spread code, and despreads the received spread signal by an operation using a spread code to extract the desired signal. Applicable to wireless communication.

FIG. 1 is a block diagram showing a configuration of a despreading demodulator according to a first embodiment of the present invention. It is a circuit diagram which shows one structural example of the multiplier used for the de-spreading demodulator of the 1st Embodiment of this invention. It is a circuit diagram which shows one structural example of the adder used for the de-spreading demodulator of the 1st Embodiment of this invention. It is a block diagram which shows one structural example of the spreading code generation circuit used for the de-spreading demodulator of the 1st Embodiment of this invention. It is a figure explaining the operation | movement of the spreading code generation circuit used for the despreading demodulator of the 1st Embodiment of this invention. It is a figure for demonstrating a problem at the time of omitting a polarity conversion circuit in the 1st Embodiment of this invention. It is a figure which shows one example of the timing of the 2nd clock used for the despreading demodulator of the 1st Embodiment of this invention, and a 3rd clock. It is a figure which shows one example of the signal waveform of the addition signal and baseband signal which are obtained with the despreading demodulator of the 1st Embodiment of this invention. It is a figure which shows the other example of the signal waveform of the addition signal obtained by the de-spreading demodulator of the 1st Embodiment of this invention, and a baseband signal. It is a block diagram which shows the structure of the de-spreading demodulator used as the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the de-spreading demodulator used as the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the de-spreading demodulator used as the 4th Embodiment of this invention. It is a block diagram which shows one structural example of the spreading code generation circuit used for the de-spreading demodulator of the 4th Embodiment of this invention. It is a block diagram which shows the structure of the de-spreading demodulator used as the 5th Embodiment of this invention. It is a block diagram which shows the structure of the de-spreading demodulator used as the 6th Embodiment of this invention. It is a block diagram which shows the structure of the despreading demodulator which is a 1st prior art. It is a block diagram which shows the structure of the despreading demodulator which is a 2nd prior art. It is a signal waveform diagram of an addition signal and a baseband signal obtained by a despreading demodulator that is the second prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a-1g, 8a-8g ... Sample hold circuit, 2 ... Sample hold control circuit, 3a-3f ... Flip-flop circuit, 4, 9 ... Spreading code generation circuit, 5a-5g, 10a-10g ... Multiplier, 6, 11 ... adder, 7, 12 ... peak detector, 101-106 ... polarity conversion circuit, MN1-MN7 ... NMOS transistor, 31, 32 ... load resistance, 40-1 ... first spreading code generation circuit, 40-2 ... Second spreading code generation circuit, 41, 42 ... exclusive OR circuit, 43a to 43n ... flip-flop circuit, 44a to 44p ... switch, 45 ... spreading code control circuit, 91 ... exclusive OR circuit, 92a to 92g ... Flip-flop circuit, 93 ... Clock control circuit.

Claims (11)

N (N is an integer of 2 or more) sample and hold circuits for holding and holding the received spread signal;
Sample hold control for controlling the N sample and hold circuits to sequentially perform a sample holding operation in synchronization with the first clock, with a first clock having the same frequency as the clock used for spreading the spread signal being input. Circuit,
A first spreading code generation circuit for generating N first spreading codes in synchronization with a second clock;
A second spreading code generation circuit for generating N second spreading codes obtained by rearranging the first spreading codes in reverse direction in synchronization with the second clock;
Of the N spreading codes output from the first spreading code generating circuit or the second spreading code generating circuit, the received order corresponds to either the newer spreading signal or the older spreading signal. A polarity conversion circuit that performs polarity conversion so that approximately half of the second clock exhibits two polarity states of inversion and non-inversion during one cycle of the second clock, and outputs the remaining approximately half of the codes as they are;
N multipliers that multiply the signal output from the sample hold circuit and the spreading code output from the polarity conversion circuit for each corresponding signal;
An adder for adding the outputs of the N multipliers;
A peak detector for detecting the peak of the output of the adder;
Each time the peak is detected by the peak detector, the input of the first spreading code from the first spreading code generation circuit to the polarity conversion circuit and the polarity conversion from the second spreading code generation circuit. A despreading demodulator comprising: a spreading code control circuit that alternately switches the input of the second spreading code to the circuit. N (N is an integer of 2 or more) sample and hold circuits for holding and holding the received spread signal;
Sample hold control for controlling the N sample and hold circuits to sequentially perform a sample holding operation in synchronization with the first clock, with a first clock having the same frequency as the clock used for spreading the spread signal being input. Circuit,
A first spreading code generation circuit for generating N first spreading codes in synchronization with a second clock;
A second spreading code generation circuit for generating N second spreading codes obtained by rearranging the first spreading codes in reverse direction in synchronization with the second clock;
N multipliers that multiply the signal output from the sample and hold circuit and the spreading code output from the first spreading code generation circuit or the second spreading code generation circuit for each corresponding signal;
Of the multiplier output signals of the N multipliers, approximately half corresponding to either the newest spread signal or the oldest spread signal received in one cycle of the second clock. A polarity conversion circuit that performs polarity conversion so as to exhibit two polarity states of inversion and non-inversion, and outputs the remaining substantially half of the multiplier output signals as they are;
An adder for adding the outputs of the polarity conversion circuit;
A peak detector for detecting the peak of the output of the adder;
Each time the peak is detected by the peak detector, the input of the first spreading code from the first spreading code generation circuit to the multiplier and the second spreading code generation circuit to the multiplier. A despreading demodulator comprising: a spreading code control circuit that alternately switches the input of the second spreading code. N (N is an integer of 2 or more) sample and hold circuits for holding and holding the received spread signal;
Sample hold control for controlling the N sample and hold circuits to sequentially perform a sample holding operation in synchronization with the first clock, with a first clock having the same frequency as the clock used for spreading the spread signal being input. Circuit,
A first spreading code generation circuit for generating N first spreading codes in synchronization with a second clock;
A second spreading code generation circuit for generating N second spreading codes obtained by rearranging the first spreading codes in reverse direction in synchronization with the second clock;
Of the sample-and-hold output signals of the N sample-and-hold circuits, approximately half corresponding to either the newest spread signal or the oldest spread signal received during one cycle of the second clock A polarity conversion circuit that converts the polarity so as to exhibit two polarity states of inversion and non-inversion, and outputs the remaining half of the sample hold output signals as they are,
N multipliers that multiply the signal output from the polarity conversion circuit and the spreading code output from the first spreading code generating circuit or the second spreading code generating circuit for each corresponding signal;
An adder for adding the outputs of the N multipliers;
A peak detector for detecting the peak of the output of the adder;
Each time the peak is detected by the peak detector, the input of the first spreading code from the first spreading code generation circuit to the multiplier and the second spreading code generation circuit to the multiplier. A despreading demodulator comprising: a spreading code control circuit that alternately switches the input of the second spreading code. N (N is an integer of 2 or more) sample and hold circuits that sample and hold the received spread signal in synchronization with a first clock having the same frequency as the clock used for spreading the spread signal;
A spreading code generating circuit for generating N spreading codes in synchronization with the second clock;
Of the N spreading codes output from the spreading code generating circuit, approximately half corresponding to either the newer spreading signal or the older spreading signal in the received order is 1 of the second clock. A polarity conversion circuit that converts the polarity so as to exhibit two polarity states of inversion and non-inversion during the period, and outputs the remaining half of the codes as they are;
N multipliers that multiply the signal output from the sample hold circuit and the spreading code output from the polarity conversion circuit for each corresponding signal;
An adder for adding the outputs of the N multipliers;
A peak detector for detecting the peak of the output of the adder;
A despreading demodulator comprising: a clock control circuit that controls input of the second clock to the spreading code generation circuit in accordance with detection of the peak by the peak detector. N (N is an integer of 2 or more) sample and hold circuits that sample and hold the received spread signal in synchronization with a first clock having the same frequency as the clock used for spreading the spread signal;
A spreading code generating circuit for generating N spreading codes in synchronization with the second clock;
N multipliers that multiply the signal output from the sample and hold circuit and the spreading code output from the spreading code generation circuit for each corresponding signal;
Of the multiplier output signals of the N multipliers, approximately half corresponding to either the newest spread signal or the oldest spread signal received in one cycle of the second clock. A polarity conversion circuit that performs polarity conversion so as to exhibit two polarity states of inversion and non-inversion, and outputs the remaining substantially half of the multiplier output signals as they are;
An adder for adding the outputs of the polarity conversion circuit;
A peak detector for detecting the peak of the output of the adder;
A despreading demodulator comprising: a clock control circuit that controls input of the second clock to the spreading code generation circuit in accordance with detection of the peak by the peak detector. N (N is an integer of 2 or more) sample and hold circuits that sample and hold the received spread signal in synchronization with a first clock having the same frequency as the clock used for spreading the spread signal;
A spreading code generating circuit for generating N spreading codes in synchronization with the second clock;
Of the sample-and-hold output signals of the N sample-and-hold circuits, approximately half corresponding to either the newest spread signal or the oldest spread signal received during one cycle of the second clock A polarity conversion circuit that converts the polarity so as to exhibit two polarity states of inversion and non-inversion, and outputs the remaining half of the sample hold output signals as they are,
N multipliers that multiply the signal output from the polarity conversion circuit and the spreading code output from the spreading code generation circuit for each corresponding signal;
An adder for adding the outputs of the N multipliers;
A peak detector for detecting the peak of the output of the adder;
A despreading demodulator comprising: a clock control circuit that controls input of the second clock to the spreading code generation circuit in accordance with detection of the peak by the peak detector. The despreading demodulator according to any one of claims 4 to 6,
The clock control circuit alternately switches stop and restart of input of the second clock to the spread code generation circuit every time the peak is detected by the peak detector. Demodulator. The despreading demodulator according to any one of claims 4 to 6,
The despreading demodulator, wherein the clock control circuit stops the input of the second clock to the spreading code generation circuit for a predetermined time when the peak is detected by the peak detector. The despreading demodulator according to any one of claims 1 to 6,
A despread demodulator comprising the spread code generating circuit comprising a flip-flop circuit, an exclusive OR circuit, and a switch for controlling an output path of the flip-flop circuit. The despreading demodulator according to any one of claims 1 to 3,
A despreading demodulator, wherein the first spreading code generation circuit, the second spreading code generation circuit, and the spreading code control circuit are configured by a DSP. The despreading demodulator according to any one of claims 4 to 6,
A despreading demodulator characterized in that the spread code generation circuit and the clock control circuit are constituted by a DSP.

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