JP3758121B2 - Correction circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present inventionIs differentMore specifically, the present invention relates to a so-called clock pulse skew correction circuit, which is not intended to be limited to this.
[0002]
[Prior art]
  In recent years, there has been remarkable progress in semiconductors, and semiconductor device state switching times are as short as about 1 μsec to 0.5 μsec, 0.35 μsec, 0.25 μsec, and 0.18 μsec, that is, those that operate at high speed. Provided. Also, the wiring layer has progressed from 2 layers to 3 layers, 5 layers, and 7 layers. The response time delay of the semiconductor element of the operation time up to about 1 μsec is dominated by the gate delay. However, in the case of the high-speed operation, the wiring delay becomes more than 50% of the weight than the gate delay. It is coming. Tool vendors and semiconductor manufacturers are working to solve these problems.
[0003]
  However, clock delay skew has become a problem, particularly due to RTL design. When branching and supplying clock pulses to various semiconductor circuits, branching after amplification by a clock buffer (clock pulse amplifier) or by inserting a clock buffer in each branch line prevents deterioration of clock pulses However, the capacitance between the reference potential and the branch line differs depending on the wiring length of the branch line, the difference in the wiring pattern, the number of electric circuit elements connected to it, the characteristics, or the arrangement, and this is the delay amount of the clock pulse. Cause variations. This causes a phase shift (skew) between clock pulses on different branch lines.
[0004]
  Conventionally, when a large skew occurs, back annotation is performed from the circuit layout result, and the clock buffer is changed in accordance with the delay information. However, in this work, the delay information is predicted as the MAX value MIN value and is not absorbed on the actual device, and often relies on the data hold of the flip-flop of the next stage connected to the branch line. Will occur.
[0005]
  In Japanese Patent Laid-Open No. 6-273478, a variable delay circuit is connected to each of a plurality of clock pulse output lines, and the phase difference between each pulse of different pulse output lines is compared by a phase comparison circuit to advance the phase. A clock skew correction circuit is disclosed in which the delay time of a variable delay circuit connected to a pulse output line on which a pulse is on is increased to reduce the phase difference between pulses of different pulse output lines. The correction circuit includes a variable delay circuit in a path for supplying a clock and a feedback path corresponding to the path, adjusts a delay time based on a result of phase comparison, and corrects a phase shift of the clock signal in the clock distribution system. The variable delay circuit used there is connected in parallel between a clock pulse output line and a reference potential (equipment ground) with a plurality of n switching elements for switching the capacitance between them in multiple stages, The a switching elements are made conductive, and the capacitance is set to a corresponding value to give a delay to the clock pulse.
[0006]
[Problems to be solved by the invention]
  However, since the pulse with the smaller phase delay is delayed by adding capacitance to the pulse signal line to reduce the phase shift between clock pulses on different lines, The bluntness is large and the pulse deteriorates.
[0007]
  The present inventionCorrection circuit that automatically reduces rising and falling phase differences between pulses on different linesTo provideEyesTargetTossThe
[0008]
[Means for Solving the Problems]
  (1)Clock pulse (CLK) First and second phase adjustment circuits(BUF2A, BUF2B)The first and second pulses output from the first and second phase adjustment circuits by controlling the number of conductive elements of the plurality of switching elements of at least one phase adjustment circuit(TpCA, TpCB)Phase adjusting means for adjusting the phase difference between the two (Ten) In a correction circuit having
  Said phase adjusting means (Ten) Is a detecting means for detecting a rising shift and a falling shift between the first and second pulses. (15 ~ 17 ) Count means for counting the number of times the detection means has detected a rising deviation and the number of times the detection means has detected a falling deviation. (18,28) And the number of rising phase adjustment conducting elements and falling phase adjustment conduction of the plurality of switching elements corresponding to the number of rising deviation detection times and the number of falling deviation detection times counted by the counting means. A correction circuit characterized by controlling the number of elements to independently adjust the rising phase and the falling phase.
[0009]
  For easy understanding, reference numerals or corresponding matters of corresponding elements or corresponding parts of the embodiments shown in the drawings and described later are added for reference.
[0010]
  According to this,Phase adjustment means (Ten)Automatically1 packLuz (TpCA)SecondPulse (TpCB)The phases of rising and falling are adjusted independently.Due to environmental changesFirst and secondBetween pulsesRise and fallThe phase shift, the delay when the frequency is overlapped, and the like are automatically corrected by the correction function of the correction means (10), and the design of each pulse output line becomes easy.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
  (2) First phase adjustment circuit (BUF2A)The clockpulse(CLK)ofHBeLeConductL levelA non-conductive, first set of first switching elements (PS1);Conduction / non-conduction is controlled by the first set of first correction signals.A plurality of first series circuits connected in series with a first set of second switching elements (PS2) are connected in parallel between a constant voltage power supply (Vc) and a first pulse output line (TpCA)., ClockLuz (CLK)LLebeLeA second set of first switching elements (NS1) that are conductive;Conduction / non-conduction is controlled by the first set of second correction signals.A plurality of second series circuits connected in series with the second set of second switching elements (NS2) are connected in parallel between the reference potential (GND) and the first pulse output line (TpCA).Is a thing;
  Second phase adjustment circuit (BUF2B)The clockpulse(CLK)ofHBeLeConductL levelAnd a third set of first switching elements that are non-conductive,Conduction / non-conduction is controlled by the second set of first correction signals.A plurality of third series circuits connected in series with the third set of second switching elements are connected in parallel between the constant voltage power supply (Vc) and the second pulse output line (TpCB)., ClockLuz (CLK)LA fourth set of first switching elements conducting at a level;Conduction / non-conduction is controlled by a second set of second correction signals.A plurality of fourth series circuits connected in series with the fourth set of second switching elements are connected in parallel between the reference potential (GND) and the second pulse output line (TpCB).Is a thing;Correction circuit according to (1) above.
[0012]
  By increasing the charging currentThe rising edge of a pulse whose rising phase is delayedTo advance the phase,Reduce the rising phase difference between the first and second pulsesBecause we setThepulseRise ofThere is no dullness and there is an effect of correcting the rise of the output pulse due to the wiring capacity of the pulse output line. Further, the collapse of the pulse duty ratio due to the dullness of the pulse rise due to the wiring capacity of the pulse output line is improved.Similarly,By increasing the discharge current, Falling of a pulse whose falling phase is delayedTo advance the phase,Reduce the falling phase difference between the first and second pulsesBecause we setTheThe fall of the pulse does not become dull, and there is an effect of correcting the fall of the fall of the output pulse due to the wiring capacity of the pulse output line. Further, the collapse of the pulse duty ratio due to the dullness of the pulse falling edge due to the wiring capacity of the pulse output line is improved.
[0013]
  (3)The counting means (18,28) Count means for counting the number of times the rising phase of the second pulse precedes the rising phase of the first pulse (18B) , A first set of second counting means for counting the number of times the rising phase of the first output pulse precedes the rising phase of the second pulse (18A) , A second set of first counting means for counting the number of times the falling phase of the second pulse precedes the falling phase of the first pulse (28B) And a second set of second counting means for counting the number of times the falling phase of the first pulse precedes the falling phase of the second output pulse. (28A) Including,
  Said phase adjusting means (Ten) Is a first set of first decoders for converting count data of the first set of first count means into a first set of first correction signals. (11A) , A first set of second decoders for converting count data of the first set of second count means into a first set of second correction signals (11B) , Second set of first decoders for converting count data of the second set of first count means into a second set of first correction signals (12A) , And a second set of second decoders for converting count data of the second set of second count means into a second set of second correction signals (12B) The correction circuit according to (1) or (2), including.
[0014]
  (4)Said phase adjusting means (Ten) Is the start instruction signal (START) Means for permitting said counting of a first set of first and second counting means and a second set of first and second counting means in response to (21,16A, 16B, 31,26A, 26B) The correction circuit according to (3), further including:.
[0015]
  (5)Said phase adjusting means (Ten) Is the reset instruction signal (RESET) Means for initializing each count data of the first set of first and second count means and the second set of first and second count means in response to (19A, 19B, 29A, 29B) The correction circuit according to (3) or (4), further including:.
[0016]
  (6)The initialization means (19A, 19B, 29A, 29B)Is2nd pulse (TpCB) The rising phase of the first pulse (TpCA) The first set of second counting means when preceding the rising phase of (18A) When the rising phase of the first pulse precedes the rising phase of the second pulse, the first set of first counting means (18B) When the falling phase of the second pulse precedes the falling phase of the first pulse, the second set of second counting means (28A) When the falling phase of the first pulse precedes the falling phase of the second pulse, the second set of first counting means is initialized. (28B) The correction circuit according to (5), wherein the count data is initialized.
[0017]
  For example, the first pulse (TpCA)Rise (fall)Is detected to be behind the second pulse (TpCB),Phase adjustment means (Ten)But,Rising (falling)Advance sideSecond pulse of (TpCB) The first set of second counting means for adjusting the rising (falling) phase of (18A) (Second set of second counting means 28A ) Count data,The second switching element (PS2(NS2)Corresponding) Initialize only one switching element in the group to be conductive, and keep current consumption by the second phase adjustment circuit (BUF2B) low. As a result, the second pulse (TpCB)Rise (fall)Is determined to be the lowest value (longest delay time) of the phase advance range that can be adjusted by the second phase adjustment circuit (BUF2B). This second pulse (TpCB)Rise (fall)Since the number of conducting elements of the second switching element (PS2) group of the first phase adjustment circuit (BUF2A) is determined so that the phase is adjusted to the same, the current consumption of the first phase adjustment circuit (BUF2A) is also reduced. Set to a low value.The same can be said for the falling, as shown in the parentheses.
[0018]
  Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.
[0019]
【Example】
  -1st Example-
  FIG.1The outline | summary of an Example is shown. In this embodiment, the clock pulse CLK is branched into two systems TpA and TpB, and TpCA and TpC, respectively.BAre outputted with a small phase difference. The clock pulse CLK passes through the buffer (buffer amplifier) BUF1, branches to the signal lines TpA and TpB, and is connected to the phase-adjustable clock buffers BUF2A and BUF2B. These are, PaThis is a pulse phase adjustment circuit. ThisThe fruitIn the embodiment, the correction circuit 10 is constituted by a logic circuit, and the logic circuit DIC generates control data and supplies it to the decoders 11A, 11B, 12A, and 12B.
[0020]
  Correction circuit10 piecesForce signalIsRESET, START, TpCA, TpCB. RESET is a reset signal for instructing initialization of the clock buffers BUF2A and BUF2B, START is a signal for instructing phase correction by the correction circuit 1, and TpCA and TpCB are feedback clock signals from the clock buffers BUF2A and BUF2B.
[0021]
  The clock buffers BUF2A and BUF2B each include a plurality of switching series circuits, and a correction circuit10ofFrom decoders 11A, 11B and 12A, 12BThe signal determines the conduction (on) / non-conduction (off) of the switching element of the switching series circuit. thesedecoderInLogic circuit DICBut controldataTheoutputTo do.Logic circuit DICThe output signals TpCA and TpCB from the clock buffers BUF2A and BUF2B are fed back. From the output line of the clock buffer BUF2A, that is, the output line of the pulse TpCA (CLOCK TREE), and from the output line of the clock buffer BUF2B, that is, the output line of the pulse TpCB,Logic circuit DICThe wiring length to is the same. The wiring additional capacitance CA of the output line of the first output pulse TpCA and the wiring additional capacitance CB of the output line of the second output pulse TpCB are determined by the wiring length and arrangement pattern of each output line and the electric circuit connected thereto. Since they are different, the first output pulse TpCA and the second output pulse TpCBA phase shift occurs between the two.Logic circuit DICDetects this phase shift and corrects the drive capabilities of the clock buffers BUF2A and BUF2B. That is, on / off of the switching element of the switching series circuit is controlled to adjust the charging current value and the discharging current value for the wiring additional capacitors CA and CB.
[0022]
  Figure2Shows the configuration of the logic circuit DIC. In this embodiment, a rising phase adjustment circuit DICr and a falling phase adjustment circuit DICf are provided in order to independently adjust the rising phase of the pulse and the falling position.
[0023]
  The rising phase adjustment circuit DICr detects the advance of the first output pulse TpCA with respect to the rise of the second output pulse TpCB, and detects the advance of the first output pulse advance detection circuit 13A and the rise of the second output pulse TpCB. A second output pulse advance detection circuit 13B that detects the advance of the one output pulse TpCA with respect to the rising edge. The rising detection circuits 15A and 15B of the output pulse advance detection circuits 13A and 13B generate narrow pulses immediately after the rising of the first output pulse TpCA and the second output pulse TpCB from L to H, respectively.
[0024]
  The falling phase adjustment circuit DICf detects the advance of the fall of the first output pulse TpCA with respect to the rise of the second output pulse TpCB, and the first output pulse advance detection circuit 14A and the fall of the second output pulse TpCB And a second output pulse advance detection circuit 14B for detecting the advance of the first output pulse TpCA with respect to the falling edge. The fall detection circuits 25A and 25B of the pulse advance detection circuits 14A and 14B generate narrow pulses immediately after the fall of the first output pulse TpCA and the second output pulse TpCB from L to H, respectively.
[0025]
  The difference in configuration between the rising phase adjustment circuit DICr and the falling phase adjustment circuit DICf is that these detection circuits 15A, 15B / 25A, and 25B detect rising / falling, and the configuration of other parts is the same. .
[0026]
  Figure3And decoders 11A, 12A andclockA combination with the buffer amplifier BUF2A is shown. Figure1Shown inDecoder 11B, 12BThe configuration of the clock buffer BUF2B is shown in FIG.3Shown inDecoder 11A, 12AAnd clock buffer BUF2AConfigurationIs the same. Figure1Shown inThepulseCLKBranches to two systems of pulses TpA and TpB via a buffer amplifier BUF1, while TpA (first input pulse TpA) is shown in FIG.3The level is inverted by the inverter IV1A at the input stage of the clock buffer BUF2A shown in FIG. 6 and the first switching elements PS1 and NS1 for positive side and negative side conduction of a total of 16 switching element series circuits from a to p. Applied to each gate.
[0027]
  Refer to FIG.The configuration of one series circuit will be described. A first pulse output line for outputting a first output pulse TpCA is connected between the positive and negative first switching elements PS1 and NS1. The positive-side switching element PS1 is connected to a positive-side second switching element PS2 whose ON / OFF is determined by a control signal. When this PS2 is turned on, a positive power supply voltage (constant voltage) Vc is applied to the positive-side first switching element PS1. In addition, when the first switching element PS1 on the positive side is turned on / off in accordance with the first input pulse TpA (H / L), the first pulse output line (TpCA) is at a high level in the H section of the first input pulse TpA. H (Vc). This charges the capacitor CA of the first pulse output line (TpCA).
[0028]
  The negative-side first switching element NS1 is connected to a negative-side second switching element NS2 that is turned on / off by a control signal. When this NS2 is turned on, a reference potential (equipment ground potential: GND) is applied to the negative-side first switching element NS1. In addition, when the first switching element NS1 on the negative side is turned on / off according to the first input pulse TpA (H / L), the first pulse output line (TpCA) is at a low level in the L section of the first input pulse TpA. L (GND). This discharges the capacitance CA of the first pulse output line (TpCA).
[0029]
  The series circuit (PS2 + PS1 + NS1 + NS2) described above is3In the embodiment shown in FIG. 6, 16 pieces a to p are connected in parallel between the output terminal of the inverter IV1A and the second pulse output line (TpCA). Many elements in the group of 16 positive second switching elements (PS2)Decoder 11AControl signal given fromIn issueBy turning on, the charging speed of the capacitor CA in the H section of the pulse signal obtained by inverting the first input pulse TpA by the inverter IV1A is increased, that is, the drive capability is increased.1The phase of the rising edge of the output pulse TpCA advances. Many elements of the group of 16 negative second switching elements (NS2)Decoder 12AControl signal given fromIn issueBy turning on, the discharge rate of the capacitor CA increases in the L section of the pulse signal obtained by inverting the first input pulse TpA by the inverter IV1A.1The phase of the falling edge of the output pulse TpCA advances.
[0030]
  For example, when only one of the clock buffers BUF2A and BUF2B is active (only the second switching elements PS2 and NS2 of the first series circuit a are on),4When the first output pulse TpCA is greatly delayed with respect to the second output pulse TpCB, as shown in FIG.3When the second switching elements PS2 and NS2 of the first to eighth series circuits a to h shown in FIG. 5 are all turned on, the phase of the first output pulse TpCA is advanced as shown in FIG. The phase shift is reduced.
[0031]
  The decoder 11A provides a conduction control signal to the rising phase advance switching element PS1 of the series circuit for phase advance of the amplifier BUF2A, while the decoder 12A controls the conduction to the switching element NS2 for advance falling phase. Give a signal. The combination of the decoders 11B and 12B and the second phase adjustment buffer amplifier BUF2B is also shown in FIG.3It is the same as shown in.
[0032]
  Note that the above-mentionedClock buffer BUF2A, BUF2BThen, the number of series circuits is 16 from a to p. However, when the resolution is insufficient by this adjustment, a plurality of buffer amplifiers (BUF2A) are connected in parallel. By doing this, the buffer is adjusted in steps of 50 psec, so that the adjusted skew can be reduced to 100 psec or less.
[0033]
  Figure2And figure3Please refer to. When a reset signal RESET (H is active) is given from a microcomputer, CPU or the like (not shown) (not shown), the counters 18A, 18B / 28A, 28B are passed through the oar gates 19A, 19B / 29A, 29B. The counter 18A, 18B / 28A, 28B is cleared (initialized), the count data indicates 0, and the Nos. Of the decoders 11B, 11A / 12B, 12A. 1-No. 16 of the output ends. Only 1 is H (active) and the others are L. Thereby, only the series circuit of the first column (leftmost column) of the first and second phase adjustment buffer amplifiers BUF2A and BUF2B, the switching element PS2 for applying a positive voltage and the switching element for applying a reference potential (GND) NS2 conducts. Thus, when there are input pulses TpA and TpB, output pulses TpCA and TpCB appear. However, both amplifiers BUF2A and BUF2B are set so that the phase is delayed most in the phase adjustment range.
[0034]
  When the host gives a start signal START (H is active), the flip-flop 21/31 is set and the flip-flops 17A, 17B / 27A, 27B are reset. Since the flip-flop 21/31 is set and its Q output rises to H, the AND gates 16A, 16B / 26A, 26B are driven by the rise detection circuits 15A, 15B / fall detection circuits 25A, 25B. / Falling detection pulse (H) can be applied to the set end S of the flip-flops 17A, 17B / 27A, 27B.
[0035]
  Here, assuming that the phase of the first output pulse TpCA is larger than that of the second output pulse TpCB, the phase of the second output pulse TpCB is more advanced than that of the first output pulse TpCA. After the signal START arrives, the rising detection circuit 15B / falling detection circuit 25B first generates a rising / falling detection pulse. As a result, the flip-flop 17B / 27B is set and its Q output becomes H, and the AND gate 20B / 30B supplies a rising / falling detection pulse to the counter 18B / 28B, thereby counting up the counter 18B / 28B. No. of the decoder 11A / 12A. The two output lines are also H, the switching elements (corresponding to PS2) / (corresponding to NS2) of the second series circuit of the buffer amplifier BUF2A are also conducted, and the rising / rising of the first output pulse TpCA The downstream phase advances one step. Since the Q gate output terminal L of the flip-flop 17B / 27B is added to the AND gate 16A / 26A, no count pulse is given to the counter 18A / 28A.
[0036]
  While the first output pulse TpCA is more than a predetermined phase behind the second output pulse TpCB, the rising detection circuit 15B / falling detection circuit 25B generates the rising / falling detection pulse of the second output pulse TpCB. Each time the counter 18B / 28B counts up by 1, the switching element (corresponding to PS2) / (corresponding to NS2) of the series circuit of the third column, fourth column,... Of the buffer amplifier BUF2A ) Also becomes conductive, and the rising / falling phase of the first output pulse TpCA advances sequentially. Then, the rising / falling detection pulse of the second output pulse TpCB generated by the rising detection circuit 15B / falling detection circuit 25B is combined with the rising / falling of the first output pulse TpCB generated by the rising detection circuit 15A / falling detection circuit 25A. When the phase of the first output pulse TpCA advances until the falling detection pulses partially overlap, H appears at the output of the AND gate 22/32, whereby the flip-flop 21/31 is reset and the AND -Gates 16A, 16B / 26A, 26B are gated off, and the count-up of counter 18B / 28B stops. This is a state in which the phase adjustment is completed, and this state continues until the reset signal RESET is given. In this state, the rising / falling phase difference between the first and second output pulses TpCA and TpCB is within the pulse width of the rising / falling detection pulse (H).
[0037]
  Since the rising phase adjustment circuit DICr and the falling phase adjustment circuit DICf operate relatively independently, the rising phase shift between the first and second output pulses TpCA and TpCB and the falling phase shift are relatively Adjusted independently. When the same pulse is branched into two lines, the duty ratio collapsed by each wiring capacity becomes substantially the same by adjusting the phases of rising and falling. That is, the duty ratio shift due to the wiring capacitance difference is absorbed on the actual device. It can be considered that the rising and falling edges on the actual device have the same waveform as the design stage, and the design can proceed smoothly.
[0038]
  Since the above-described phase correction is performed each time the START signal is turned on, the START signal is turned on immediately after the initialization of the power-on response or immediately after the host computer is reset. It is also possible to correct the phase shift between pulses. Also, skew adjustment accompanying process variations can be reliably performed within 100 ps by using this circuit.
[0039]
  When the clock signal is not required, the supply of the clock signal can be stopped by turning off the switching elements PS2 of all the series circuits, so that useless current consumption can be reduced. Further, if the inverter IV1A is replaced with a NAND gate and the signal from the other input is set to STANDBY, the clock supply to unnecessary circuits can be stopped. At the same time, skew adjustment of other parts is also possible. Furthermore, when the clock pulse is divided on an actual device, by arranging the circuit of this embodiment immediately after the frequency division, the edges of the divided clock can be compared for adjustment, and the frequency can be adjusted. Different clock phases can be matched.
[Brief description of the drawings]
FIG. 1 shows the present invention.1 ofIt is a block diagram which shows the structure of an Example.
FIG. 212 is a block diagram showing a configuration of a logic circuit DIC shown in FIG.
FIG. 312 is a block diagram showing a configuration of the phase adjustment buffer amplifier BUF2A and decoders 11A and 12A shown in FIG.
4 is a time chart showing time series level changes of first and second output pulses TpCB and TpCA before performing relative phase shift adjustment by the buffer amplifiers BUF2A and BUF2B shown in FIG.
5 is a time chart showing time-series level changes of first and second output pulses TpCB and TpCA in which the relative phase shift is reduced by the buffer amplifiers BUF2A and BUF2B shown in FIG.
[Explanation of symbols]
BUF1, BUF2A, BUF2B: buffer amplifier
DIC: Logic circuit
DICr: Rise phase adjustment circuit
DICf: falling phase adjustment circuit

Claims (6)

The first and second phase adjustment circuits output the first and second phase adjustment circuits by inputting clock pulses to the first and second phase adjustment circuits and controlling the number of conducting elements of the plurality of switching elements of at least one of the phase adjustment circuits. In a correction circuit having phase adjusting means for adjusting a phase difference between two pulses,
The phase adjusting means includes a detecting means for detecting a rising deviation and a falling deviation between the first and second pulses, and a count for counting the number of times the detecting means has detected a rising deviation and the number of times the falling deviation has been detected. And the number of rising phase adjustment conducting elements and the falling phase adjustment of the plurality of switching elements corresponding to the number of rising deviation detection times and the number of falling deviation detection times counted by the counting means. A correction circuit, wherein the number of conductive elements is controlled to independently adjust a rising phase and a falling phase . The first phase adjustment circuit, the non-conducting in the conducting and L level H Les bell clock pulses, a first set of the first switching element, conduction / non-conduction is controlled by a first set of the first correction signal a first set of second switching element first series circuit connected in series, a plurality in parallel, connected between the constant voltage power supply and the first pulse output line, the L level of the clock pulse that A plurality of second series circuits in which a second set of first switching elements that are conductive and a second set of second switching elements that are controlled to be conductive / non-conductive by the first correction signal are connected in series. the number in parallel, the reference potential and is obtained by connecting between the first pulse output line;
# 2 phase adjustment circuit is configured to conduct at H Les bell clock pulses of the non-conductive at the L level, and the third set of the first switching element, conduction / non-conduction control by the second set of the first correction signal the third set of a second switching element third series circuit connected in series, a plurality in parallel, connected between the constant voltage power supply and a second pulse output line, an input pulse of L level is A fourth series circuit in which a fourth set of first switching elements that are conducted in the series and a fourth set of second switching elements in which conduction / non-conduction is controlled by the second correction signal are connected in series. a plurality in parallel, the reference potential and which are connected between the second pulse output line;
The correction circuit according to claim 1 . The counting means counts the number of times the rising phase of the second pulse precedes the rising phase of the first pulse, and counts the number of times the rising phase of the first output pulse precedes the rising phase of the second pulse. One set of second counting means, a second set of first counting means for counting the number of times the falling phase of the second pulse preceded the falling phase of the first pulse, and the falling phase of the first pulse being the first A second set of second counting means for counting the number of times preceding the falling phase of the two output pulses,
The phase adjusting means converts the count data of the first set of first count means into the first set of first correction signals, the first set of first decoders, and the first set of second count means of the count data of the first set. A first set of second decoders for converting into a set of second correction signals, a second set of first decoders for converting count data of the second set of first count means into a second set of first correction signals, and The correction circuit according to claim 1, further comprising: a second set of second decoders that convert count data of the second set of second count means into a second set of second correction signals . The phase adjusting means further includes means for permitting the counting of a first set of first and second count means and a second set of first and second count means in response to a start instruction signal. 4. The correction circuit according to 3 . The phase adjusting means further includes means for initializing count data of the first set of first and second count means and the second set of first and second count means in response to a reset instruction signal. Item 5. The correction circuit according to Item 3 or 4 . The initialization means initializes the count data of the first set of second count means when the rising phase of the second pulse precedes the rising phase of the first pulse, and the rising phase of the first pulse is the rising edge of the second pulse. When the phase precedes, the count data of the first set of first counting means is initialized, and when the falling phase of the second pulse precedes the falling phase of the first pulse, the count of the second set of second counting means 6. The correction circuit according to claim 5, wherein data is initialized and count data of the second set of first count means is initialized when the falling phase of the first pulse precedes the falling phase of the second pulse .

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