JP3760822B2 - Signal control circuit and image forming apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal control circuit, and more particularly to a signal control circuit used in a printer or a copying machine.
[0002]
[Prior art]
In recent years, with the spread of digital cameras, scanners, and the like, it has become possible to easily perform image processing by converting an image into digital data and taking the converted image into a computer. For this reason, for example, color laser printers and copiers (hereinafter referred to as printers) are often used to print images captured by a computer cleanly and quickly.
[0003]
This printer or the like generally reproduces various colors by multiplying four colors of Y (yellow) M (magenta) C (cyan) K (black). For this reason, a writing unit (for example, a photosensitive drum, a laser ROS (Raster Optical Scanner), etc.) for printing an image is provided for each color of YMCK.
[0004]
When a writing unit is provided for each color of YMCK as in the above-described printer, etc., due to assembly errors of the writing unit (for example, deviation of the installation position of the photosensitive drum), characteristic changes in the writing unit due to temperature changes, etc. There is a problem that the writing position of an image or the like at the time of printing is shifted, that is, a color shift occurs. In order to cope with this problem, conventionally, a separate control signal is output to the writing unit for each color to control the writing timing at the time of printing.
[0005]
[Problems to be solved by the invention]
Specifically, a relatively large color shift (pixel-specific color shift) can be roughly adjusted by a pixel clock (reference clock). However, the shift below the reference clock (color shift less than a pixel unit) needs to be finely adjusted using a delay buffer or the like. Furthermore, since this fine adjustment is a fine adjustment of the delay amount of the delay buffer according to the reference clock, it takes time to add a delay buffer or the like. That is, conventionally, since the writing timing is controlled by manually changing a physical circuit, complicated work is required and the degree of freedom of the circuit itself is low.
[0006]
An object of the present invention is to realize a circuit that performs highly accurate timing control by outputting a signal with a resolution equal to or less than the period of a reference clock.
[0007]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present invention has the following features.
[0008]
  The invention described in claim 1
  First delay means for delaying a reference clock signal by a plurality of delay elements connected in multiple stages and outputting the delayed reference clock signal for each stage;
  With multiple delay elements connected in multiple stages,Index that controls the writing timing of the image forming deviceA second delay means for delaying the signal and outputting the delayed controlled signal for each stage;
  Based on the delayed reference clock signal, the reference clock signalThe number of stages for one cycle,Predetermined resolutionAnd the specified delay amountA delay amount calculating means for calculating a delay amount;
  Based on the delay amount calculated by the delay amount calculation means, a signal selection means for alternatively selecting a signal from the delayed controlled signals and outputting the selected signal to the outside;
  It is characterized by having.
[0009]
  According to the first aspect of the present invention, the reference clock signal is generated based on the delayed reference clock signal.The number of stages for one cycle,Predetermined resolutionAnd the instruction delay amountCalculate the amount of delay. Then, a signal alternatively selected from the delayed controlled signals based on the delay amount is output to the outside. Therefore, regardless of changes in the frequency of the reference clock signal, the reference clock signal has a predetermined resolution.indexThe signal can be delayed. For this reason,indexSignal timing can be controlled with high accuracy. And a reference clock signal,indexSince signals are delayed separately, they can be controlled simultaneously and in real timeindexThe signal can be delayed.
  The invention according to claim 2 is the invention according to claim 1,
  Input means for externally inputting a predetermined signal;
  Detecting means for detecting the number of stages of the delay elements for one period of the reference clock signal based on the delayed reference clock signal synchronized with the predetermined signal input by the input means;
  With
  The delay amount calculation means calculates the delay amount based on the number of stages detected by the detection means.
  Claim 2RecordAccording to the described invention, for example, based on a delay reference clock signal synchronized with a predetermined signal such as a pulse signal or a step signal, the number of stages of delay elements corresponding to one period of the reference clock signal is detected, and based on this number of stages. Thus, a signal control circuit for calculating the delay amount is realized.
[0010]
  Claim3The invention described in claim 1Or 2The signal control circuit described above is characterized in that the first delay means and the second delay means have the same circuit configuration.
[0011]
  According to the invention of claim 3, based on the reference clock signalindexIt is easy to calculate the delay amount of the signal.
[0012]
  Claim4The signal control circuit according to any one of claims 1 to 3, wherein the delay amount calculation means changes the delay characteristic of the first delay means to the delay characteristic of the second delay means. In order to match, a correction means for correcting the delay amount is provided.
[0013]
  According to the invention of claim 4, even if the delay characteristics of the first delay means and the delay characteristics of the second delay means are different, the delay characteristics can be made the same, and the reference clock signal,indexSince the delay amount with the signal can be the same, the delay amount calculated based on the reference clock signalindexIt can be applied to the amount of signal delay.
[0014]
  According to invention of Claim 5,
  A reference clock signal or a plurality of delay elements connected in multiple stagesIndex that controls the writing timing of the image forming deviceDelay means for delaying the signal and outputting each stage as a delayed reference clock signal or a delayed controlled signal;
  Based on the delayed reference clock signal, the reference clock signalThe number of stages for one cycle,Predetermined resolutionAnd the instruction delay amountA delay amount calculating means for calculating a delay amount;
  Based on the delay amount calculated by the delay amount calculation means, a signal selection means for alternatively selecting a signal from the delayed controlled signals and outputting the selected signal to the outside;
  With
  A reference clock signal input to the delay means;indexThe delay unit, the delay amount calculation unit, and the signal selection unit are operated according to the switched signal.
[0015]
  According to the invention of claim 5, the reference clock signal by one delay means,indexDelay the signal. Also, based on the delayed reference clock signal, the reference clock signalThe number of stages for one cycle,Predetermined resolutionAnd the instruction delay amountCalculate the amount of delay. Then, a signal alternatively selected from the delayed controlled signals based on the delay amount is output to the outside. Therefore, regardless of changes in the frequency of the reference clock signal, with a predetermined resolution with respect to the reference clock signal,indexThe signal can be delayed. For this reason,indexSignal timing can be controlled with high accuracy. In addition, with the same delay means, the reference clock signal,indexThe delay amount calculated based on the reference clock signal isindexThe present invention can be applied to the signal delay as it is.
  According to a sixth aspect of the present invention, in the signal control circuit according to the fifth aspect,
  Input means for externally inputting a predetermined signal;
  Detecting means for detecting the number of stages of the delay elements for one period of the reference clock signal based on the delayed reference clock signal synchronized with the predetermined signal input by the input means;
  Have
  The delay amount calculation means calculates the delay amount based on the number of stages detected by the detection means,
  A reference clock signal input to the delay means;indexThe delay unit, the detection unit, the delay amount calculation unit, and the signal selection unit are operated according to the switched signal.
  According to the sixth aspect of the present invention, for example, the number of stages of delay elements corresponding to one cycle of the reference clock signal is detected based on a delay reference clock signal synchronized with a predetermined signal such as a pulse signal or a step signal. A signal control circuit that calculates a delay amount based on the number of stages is realized.
  Further, as in the invention according to claim 7, the claimAn image forming apparatus including the signal control circuit according to 1 or 5 and having the writing timing controlled by a signal output from the signal selection unit may be realized.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
Hereinafter, a first embodiment of a signal control circuit 10 to which the present invention is applied will be described in detail with reference to FIGS. The signal control circuit 10 delays, for example, an INDEX signal (controlled signal) for controlling the writing timing of a plurality of writing units provided in the color laser printer.
[0017]
First, the configuration in the first embodiment will be described.
FIG. 1 is a diagram illustrating a configuration of the signal control circuit 10.
The signal control circuit 10 includes a delay chain unit 1, a state detection unit 2, a synchronization signal detection unit 3, a delay amount calculation unit 4, a delay chain unit 5, and a signal selection unit 6.
[0018]
As shown in FIG. 2, the delay chain unit 1 includes m delay cells DC1 to DCm and a plurality of inverters INV. The delay chain unit 1 delays the reference clock signal Ref (DL0) and outputs it to the state detection unit 2. To do. Here, the inverter INV is inserted in order to suppress the duty collapse of the reference clock signal Ref (DL0).
[0019]
Each of the delay cells DC1 to DCm outputs the input signal after delaying the input signal by a predetermined delay amount (for example, X [ps order]). That is, as shown in FIG. 2, delay cells DC1 to DCm are connected in multiple stages (in series), and an output stage corresponding to each delay cell is provided, thereby delaying by an integral multiple (1 to m times) of a predetermined delay amount. The input signal is output from each output stage. This is output to the state detection unit 2 as an mbit width signal.
[0020]
More specifically, in FIG. 2, the first-stage delay cell DC1 delays and outputs the reference clock signal Ref (DL0) by a predetermined delay amount (for example, X [ps order]). The output signal is output from the output stage corresponding to the delay cell DC1 to the state detection unit 2 as the delay signal DL1, and is also output to the delay cell DC2.
The second-stage delay cell DC2 delays the input delay signal DL1 by a predetermined delay amount (for example, X [ps order]) and outputs the delayed signal. The output signal is output from the output stage corresponding to the delay cell DC2 to the state detection unit 2 as the delay signal DL2, and also output to the delay cell DC3.
Similarly, the m-th delay cell DCm delays the input delay signal DLm-1 by a predetermined delay amount (for example, X [ps order]) and outputs it. The output signal is output from the output stage corresponding to the delay cell DCm to the state detection unit 2 as the delay signal DLm.
That is, here, the delay chain section 1 has a function as a first delay means. Here, the delay signals DL1 to m1 mean a delay reference clock signal.
[0021]
As shown in FIG. 3, the state detection unit 2 includes m D flip-flops FF1 to FFm. The state detection unit 2 receives the delay signals DL1 to m1 input from the delay chain unit 1 at the timing when the reference pulse signal is input. The state (“H” or “L”) is detected (latched) and output to the detection circuit 3 a of the synchronization signal detection unit 3. Here, a reference pulse signal is used as the predetermined signal. In addition, here, the state detection unit 2 has a function as input means.
[0022]
The D flip-flops FF1 to FFm receive the states ("H" or "L") of the delayed signals DL1 to m output from the delay chain unit 1 to the input terminals D, respectively, and reference pulses to the clock terminals. A signal is input. Then, the states of the delay signals DL1 to m input to the input terminals D are latched in synchronization with the reference pulse signal, the latched value is output from the output terminal Q, and the latched value is output from the inverted output terminal. Inverted output.
[0023]
The synchronization signal detection unit 3 includes a detection circuit 3a shown in FIG. 3 and an arithmetic circuit (not shown).
In FIG. 3, the detection circuit 3a is composed of m NAND gates N1 to Nm.
[0024]
The NAND gates N1 to Nm have values output from the output terminal Q of the D flip-flop of the previous stage (here, 1 to m stages) and the D flip-flop of the next stage (here, 2 to "m + 1" stages). The value output from the inverting output terminal is input, the negative logical product of the two input values (“H” or “L”) is calculated, and the calculation result is output to an arithmetic circuit (not shown). .
[0025]
The calculation circuit (not shown) receives the calculation result output from the detection circuit 3a. Then, based on the input calculation result, the number of delay cells that perform a delay of one cycle of the reference clock signal Ref is calculated. Further, the calculated number of delay cells is output to the delay amount calculation unit 4. Specific operations will be described later.
[0026]
As described above, the state detection unit 2 and the synchronization signal detection unit 3 have a function as detection means.
[0027]
The delay amount calculation unit 4 receives the number of delay cells output from the synchronization signal detection unit 3 and the instruction delay amount and resolution 1 / n specified from the outside (for example, CPU). Here, the resolution 1 / n is arbitrarily set, and may be a fixed value or a variable value.
[0028]
Then, the delay amount calculation unit 4 calculates the product of the number of input delay cells (number of stages), the resolution 1 / n, and the instruction delay amount as a delay amount. For example, when the number of delay cells is 100, the resolution is 1/32, and the instruction delay amount is A, 100 stages × 1/32 × A (A = 1, 2, 3,... The amount of delay is calculated according to 32). Based on this calculation, the delay amount calculation unit 4 generates a select signal for selecting the number of output stages of the delay chain unit 5 and outputs it to the signal select unit 6.
That is, here, the delay amount calculation unit 4 has a function as delay amount calculation means.
[0029]
The delay chain unit 5 has the same configuration as the delay chain unit 1 shown in FIG. 2, and delays an INDEX signal input from the outside by a predetermined delay amount (X [ps order]) by m delay cells. . Then, the delay signal output from each output stage corresponding to the delay cells DC1 to DCm is output to the signal selector 6 as an mbit width signal.
That is, here, the delay chain unit 5 has a function as second delay means. Further, the delayed signal output from the delay chain unit 5 means a delayed controlled signal.
[0030]
As shown in FIG. 4, the signal selector 6 includes a selector 6a. The selector 6a receives a select signal output from the delay amount calculation unit 4 and an mbit width signal output from each stage (1 to m stages) of the delay chain unit 5. Then, the selector 6a selects one of the mbit width signals according to the select signal, and outputs the selected signal to the outside as a delayed INDEX signal.
That is, here, the signal selection unit 6 has a function as signal selection means.
[0031]
Next, operations in the first embodiment will be described with reference to FIGS.
FIG. 5 is a diagram illustrating an example of the reference clock signal Ref (DL0) input to the delay chain unit 1 and the delay signals DL1 to 201 output from the delay chain unit 1.
[0032]
As shown in FIG. 5, the delay signal DL1 (first-stage output signal) is obtained by delaying the reference clock signal Ref (DL0) by a predetermined delay amount (X [ps order]) by the delay cell DC1, and delay signal DL2 ( The second stage output signal) is obtained by delaying the reference clock signal Ref (DL0) by a predetermined delay amount twice (that is, 2X [ps order]) by the delay cells DC1 and 2, and delay signal DL200 (200th stage output). Signal) delays the reference clock signal Ref (DL0) by 200 times the predetermined delay amount (that is, 200X [ps order]) by the delay cells DC1 to DC200.
[0033]
Here, the delay signals DL100 and 200 are synchronized with the reference clock signal Ref (DL0). That is, 100X seconds and 200X seconds, which are the delay amounts of the delay signals DL100 and 200, mean an integral multiple of the period of the reference clock signal Ref (DL0).
[0034]
Then, the delay chain unit 1 outputs the delay signals DL1 to m to the state detection unit 2, and the state detection unit 2 outputs the state of the delay signals DL1 to m (“H” or “H” at the timing when the reference pulse signal is input). “L”) is output to the synchronization signal detector 3.
[0035]
FIG. 6 is a timing chart of the reference pulse signal and delay signals DL1 to 201 and the reference clock signal Ref (DL0) input to the state detection unit 2.
[0036]
As shown in FIG. 6, the synchronization signal detector 3 detects a delay signal (here, the delay signal DL100 / 200) that is synchronized with the reference pulse signal. FIG. 6 shows an example in which the reference pulse signal is input to the state detection unit 2 at the timing (time T1 shown in FIG. 6) synchronized with the rising edge of the reference clock signal Ref (DL0).
[0037]
At this time T1, the delay signals DL1 to DL3, 101, and 201 are “L”, and the delay signals DL99, 100, 199, and 200 are “H”. Accordingly, at the time T1 when the reference pulse signal is input, the D flip-flops D1 to m latch the delay signals DL1 to m, respectively, and output them to the NAND gates N1 to m.
[0038]
Then, the NAND gates N1 to Nm calculate a negative logical product based on the state output from the D flip-flops FF1 to FFm, and output the calculation result to an arithmetic circuit (not shown). By this calculation, a signal that is synchronized with the reference pulse signal and a signal that is not synchronized are identified. Therefore, “L” is output to the arithmetic circuit from the NAND gates N100 and 200 corresponding to the delay signals DL100 and 200 (that is, signals synchronized with the reference pulse signal) shown in FIG. “H” is output from the NAND gate corresponding to.
[0039]
Then, the arithmetic circuit calculates a difference in the number of output stages of the delay chain unit 1 that outputs the delay signals DL100 and 200 (that is, “200” of the NAND gate N200− “100” = 100 stages of the NAND gate N100), and delays It outputs to the quantity calculation part 4.
[0040]
The delay amount calculation unit 4 includes the difference (100 stages) in the number of output stages of the delay chain unit 1 output from the synchronization signal detection unit 3, that is, the number of delay cells that perform a delay of one cycle of the reference clock signal Ref, and the external A select signal for selecting the output stage of the delay chain unit 5 is generated by calculating the product of the instruction delay amount and the resolution 1 / n input from (for example, CPU), and output to the signal select unit 6 To do.
[0041]
FIG. 7 is an example of a timing chart of the reference clock signal Ref and INDEX signal input from the outside to the signal control circuit 10 and the delayed INDEX signal output from the signal control circuit 10.
[0042]
In FIG. 7, the INDEX signal is input to the delay chain unit 5, and is delayed by an integral multiple (any one of 1 to m times) of a predetermined delay amount (X [ps order]) by the delay cells DC1 to DCm. Each output stage (1 to m stages) corresponding to the delay cells DC1 to m of the stage is output to the signal selection unit 6 as a mbit width signal.
Then, the signal selector 6 selects one of the mbit width signals output from the delay chain unit 5 according to the select signal input from the delay amount calculator 4 and delays the selected signal. Output to the outside as an INDEX signal.
[0043]
As described above, according to the signal control circuit 10 of the first embodiment, the delay chain unit 1, the state detection unit 2, and the synchronization signal detection unit 3 are delayed by one cycle of the reference clock signal Ref. The number of delay cells (number of stages) required for performing the above is detected. Then, the delay amount calculation unit 4 calculates the delay amount of the INDEX signal based on the number of detected delay cells and the resolution 1 / n and the instruction delay amount input from the outside (for example, CPU). To do. The delay amount calculation unit 4 generates a select signal based on the calculated delay amount and outputs the select signal to the signal selection unit 6.
[0044]
Also, the delay chain unit 5 delays the input INDEX signal by a predetermined delay amount (X [ps order]) by a plurality of delay cells equivalent to the delay chain unit 1, and from each output stage to the signal selection unit 6 Output to.
[0045]
Then, the signal selector 6 selects one of the output signals of the delay chain unit 5 according to the input select signal, and outputs the selected signal to the outside as a delayed INDEX signal.
[0046]
Therefore, the signal control circuit 10 always delays the INDEX signal (controlled signal) with the resolution 1 / n of the period of the reference clock signal Ref regardless of the change in the frequency (that is, the period) of the reference clock signal Ref. Can do. For this reason, the timing of the INDEX signal (controlled signal) can be controlled with high accuracy.
[0047]
Further, if the signal control circuit 10 is configured in the integrated circuit (digital circuit), the signal control circuit 10 can realize a highly accurate delay, so that a delay buffer added later for timing adjustment as in the prior art. Can be provided at low cost.
[0048]
Also, two delay chain units are provided, the delay amount of the INDEX signal (controlled signal) is calculated by one delay chain unit, and the INDEX signal (controlled signal) output from the other delay chain unit with the calculated delay amount Therefore, the two delay chains can perform their respective operations simultaneously, and can delay the controlled signal in real time.
[0049]
In the first embodiment, the case where the delay chain unit 1 and the delay chain unit 5 have the same characteristics has been described. However, when the characteristics (for example, the delay amount by each stage) are different, the delay amount is set to be different. It may be corrected. The correction in this case may be performed by the delay amount calculation unit 4 or may be performed by providing a correction unit separately. Moreover, it is good also as correcting by the instruction | indication from CPU.
That is, the delay amount calculation unit 4 or a correction unit provided separately has a function as a correction unit.
[0050]
In the first embodiment, the reference pulse signal is input to the state detection unit 2. However, the present invention is not limited to this, and a predetermined signal is input to the state detection unit 2 and synchronized with the predetermined signal. Based on the delayed signal, the number of stages of delay elements for one cycle of the reference clock signal may be detected. Therefore, for example, an INDEX signal may be input to the state detection unit 2 as a predetermined signal.
[0051]
[Second Embodiment]
Next, a second embodiment of the signal control circuit 20 to which the present invention is applied will be described in detail with reference to FIG. Note that in the configuration of the signal control circuit 20 in the second embodiment, detailed description of the same parts as those in the first embodiment is omitted, and the same components are denoted by the same reference numerals and described below. To do.
[0052]
First, the configuration in the second embodiment will be described.
FIG. 8 is a diagram illustrating a configuration of the signal control circuit 20.
The signal control circuit 20 includes a state detection unit 2, a synchronization signal detection unit 3, a delay amount calculation unit 4, a signal selection unit 6, an input signal selection unit 7, and a delay chain unit 8.
[0053]
The input signal selector 7 includes a selector (not shown), selects either the reference clock signal Ref or the INDEX signal input from the outside, and outputs the selected signal to the delay chain unit 8. .
[0054]
The delay chain unit 8 has the same configuration as the delay chain units 1 and 5 shown in FIG. 2, and a signal (reference clock signal Ref (DL0) or INDEX) input to the input unit (first-stage delay cell DC1). Signal) is delayed by a predetermined delay amount (X [ps order]) by each delay cell DC1 to m, and is output from each output stage (1 to m stage) to the state detection unit 2 or the signal selection unit 6.
That is, here, the delay chain unit 8 has a function as a delay means.
[0055]
As shown in FIG. 8, the state detection unit 2 detects (latches) the states (“H” or “L”) of the delay signals DL1 to m input from the delay chain unit 8 at the timing when the INDEX signal is input. And output to the detection circuit 3a of the synchronization signal detector 3. Here, an INDEX signal is used as the predetermined signal. In addition, here, the state detection unit 2 has a function as input means.
The detection circuit 3a of the synchronization signal detection unit 3 detects a plurality of delay signals synchronized with the INDEX signal, and the arithmetic circuit (not shown) determines the number of delay cells for delaying one cycle of the reference clock signal Ref. calculate.
That is, here, the state detection unit 2 and the synchronization signal detection unit 3 have a function as detection means.
[0056]
Next, the operation in the second embodiment will be described.
First, the input signal selector 7 selects a reference clock signal Ref input from the outside and outputs it to the delay chain unit 8. Here, the delay chain unit 8 delays the input reference clock signal Ref by a predetermined delay amount (X [ps order]), and outputs the state detection unit 2 as an mbit width signal from each output stage (1 to m stages). Output to.
[0057]
The state detection unit 2 latches the states of the delay signals DL1 to m output from the delay chain unit 8 at the timing when the INDEX signal is input, and outputs the latched signals to the detection circuit 3a of the synchronization signal detection unit 3. The detection circuit 3a detects the number of output stages for one cycle of the reference clock signal Ref based on the signal output from the state detection unit 2, and inputs the detected number of output stages and the outside (for example, CPU). A select signal for selecting the number of output stages of the delay chain unit 5 is generated based on the instruction delay amount and the resolution 1 / n, and is output to the signal select unit 6.
[0058]
Next, the input signal selection unit 7 selects an INDEX signal input from the outside, and outputs it to the delay chain unit 8. Here, the delay chain unit 8 delays the input INDEX signal by a predetermined delay amount (X [ps order]) by the delay cells DC1 to DCm, and the signal selection unit 6 from each output stage (1 to m stage). Output to.
[0059]
Then, the signal selection unit 6 selects one of the mbit width signals output from each output stage (1 to m stages) of the delay chain unit 8 in accordance with the select signal output from the delay amount calculation unit 4. A signal is selected, and the selected signal is output to the outside as a delayed INDEX signal.
[0060]
As described above, in the second embodiment, the signal control circuit 20 includes the delay chain unit 8, the state detection unit 2, the synchronization signal detection unit 3, and the delay amount calculation unit 4. The number of delay cells (the number of stages) necessary to perform a delay for one period is detected. Then, the delay amount calculation unit 4 calculates the delay amount of the INDEX signal based on the number of detected delay cells and the resolution 1 / n and the instruction delay amount input from the outside (for example, CPU). To do. The delay amount calculation unit 4 generates a select signal based on the calculated delay amount and outputs the select signal to the signal selection unit 6.
[0061]
The delay chain unit 8 delays the INDEX signal output from the input signal selection unit 7 by a predetermined delay amount (X [ps order]) by a plurality of delay cells, and outputs each output stage (1 to m stages). To the signal selector 6.
[0062]
Then, the signal selection unit 6 selects one of the mbit width signals output from the delay chain unit 8 according to the input select signal, and outputs the selected signal to the outside as a delayed INDEX signal. To do.
[0063]
Therefore, the INDEX signal (controlled signal) can always be delayed with the resolution 1 / n of the period of the reference clock signal Ref regardless of the change in the frequency (that is, the period) of the reference clock signal Ref. For this reason, the timing of the INDEX signal (controlled signal) can be controlled with high accuracy.
[0064]
Further, if the signal control circuit 10 is configured in the integrated circuit (digital circuit), the signal control circuit 10 can realize a highly accurate delay, so that a delay buffer added later for timing adjustment as in the prior art. Can be provided at low cost.
[0065]
In the second embodiment, the INDEX signal is input to the state detection unit 2. However, the present invention is not limited to this, and a predetermined signal is input to the state detection unit 2 and synchronized with the predetermined signal. Based on the delay signal, the number of stages of delay elements for one cycle of the reference clock signal may be detected. Therefore, for example, a reference pulse signal may be input to the state detection unit 2 as a predetermined signal.
[0066]
Further, the present invention is not limited to the contents of the above embodiment, and can be appropriately changed without departing from the gist of the present invention.
[0067]
【The invention's effect】
  According to the first aspect of the present invention, the reference clock signal can be obtained with a predetermined resolution regardless of a change in the frequency of the reference clock signal.indexThe signal can be delayed. For this reason,indexSignal timing can be controlled with high accuracy. And a reference clock signal,indexSince signals are delayed separately, they can be controlled simultaneously and in real timeindexThe signal can be delayed.
[0068]
  According to the second aspect of the present invention, for example, the number of stages of delay elements corresponding to one cycle of the reference clock signal is detected based on a delay reference clock signal synchronized with a predetermined signal such as a pulse signal or a step signal. A signal control circuit that calculates a delay amount based on the number of stages is realized.
  Claim 3RecordAccording to the invention described, based on the reference clock signalindexIt is easy to calculate the delay amount of the signal.
[0069]
  According to the invention of claim 4, the reference clock signal;indexSince the delay amount with the signal can be the same, the delay amount calculated based on the reference clock signalindexIt can be applied to the amount of signal delay.
[0070]
  According to the invention of claim 5, regardless of the change in the frequency of the reference clock signal, the reference clock signal has a predetermined resolution,indexThe signal can be delayed. For this reason,indexSignal timing can be controlled with high accuracy. In addition, with the same delay means, the reference clock signal,indexThe delay amount calculated based on the reference clock signal isindexThe present invention can be applied to the signal delay as it is.
  Claim 6RecordAccording to the described invention, for example, the number of stages of the delay elements corresponding to one period of the reference clock signal is detected based on the delayed reference clock signal synchronized with a predetermined signal such as a pulse signal or a step signal, and the number of stages is determined based on the number of stages. Thus, a signal control circuit for calculating the delay amount is realized.
  According to invention of Claim 7,,It is possible to realize an image forming apparatus in which the writing timing is controlled by a signal selected from the delayed controlled signals obtained by delaying the index signal.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a circuit configuration of a signal control circuit according to a first embodiment.
FIG. 2 is a diagram illustrating a circuit configuration of a delay chain unit.
FIG. 3 is a diagram illustrating a circuit configuration of a detection circuit.
FIG. 4 is a diagram illustrating a selector included in a signal selection unit.
FIG. 5 is a diagram illustrating a delay signal output from a delay chain unit and a reference clock signal.
FIG. 6 is a timing chart of a reference pulse signal and a delay signal input to a synchronization signal detection unit, and a reference clock signal.
FIG. 7 is a timing chart of a reference clock signal, an INDEX signal, and a delayed INDEX signal.
FIG. 8 is a diagram illustrating a circuit configuration of a signal control circuit according to a second embodiment.
[Explanation of symbols]
1, 5, 8 Delay chain
2 State detector
3 Sync signal detector
3a detection circuit
4 Delay calculation unit
6 Signal select section
6a selector
7 Input signal selector
10, 20 Signal control circuit
DC1-m delay cell
DL1-m Delay signal
INV inverter
N1-m NAND gate
FF1-m flip-flop
Ref Reference clock signal

Claims (7)

First delay means for delaying a reference clock signal by a plurality of delay elements connected in multiple stages and outputting the delayed reference clock signal for each stage;
Second delay means for delaying an index signal for controlling the writing start timing of the image forming apparatus by a plurality of delay elements connected in multiple stages, and outputting the delayed signal as a delayed controlled signal for each stage;
A delay amount calculating means for calculating a delay amount from the number of stages of one cycle of the reference clock signal , a predetermined resolution, and a specified delay amount based on the delay reference clock signal;
Based on the delay amount calculated by the delay amount calculation means, a signal selection means for alternatively selecting a signal from the delayed controlled signals and outputting the selected signal to the outside;
A signal control circuit comprising: Input means for externally inputting a predetermined signal;
Detecting means for detecting the number of stages of the delay elements for one period of the reference clock signal based on the delayed reference clock signal synchronized with the predetermined signal input by the input means;
With
The signal control circuit according to claim 1, wherein the delay amount calculation unit calculates the delay amount based on the number of stages detected by the detection unit.   3. The signal control circuit according to claim 1, wherein the first delay unit and the second delay unit have the same circuit configuration.   4. The delay amount calculating means includes correction means for correcting a delay amount so that the delay characteristic of the first delay means matches the delay characteristic of the second delay means. The signal control circuit according to any one of the above. Delay means for delaying a reference clock signal or an index signal for controlling the writing timing of the image forming apparatus by a plurality of delay elements connected in multiple stages, and outputting the delayed reference clock signal or a delayed controlled signal for each stage;
A delay amount calculation means for calculating a delay amount from the number of stages of one cycle of the reference clock signal , a predetermined resolution, and an instruction delay amount based on the delay reference clock signal;
Based on the delay amount calculated by the delay amount calculation means, a signal selection means for alternatively selecting a signal from the delayed controlled signals and outputting the selected signal to the outside;
And switching the reference clock signal and the index signal input to the delay means, and causing the delay means, the delay amount calculation means, and the signal selection means to act according to the switched signals circuit. Input means for externally inputting a predetermined signal;
Detecting means for detecting the number of stages of the delay elements for one period of the reference clock signal based on the delayed reference clock signal synchronized with the predetermined signal input by the input means;
With
The delay amount calculation means calculates the delay amount based on the number of stages detected by the detection means,
The reference clock signal and the index signal input to the delay unit are switched, and the delay unit, the detection unit, the delay amount calculation unit, and the signal selection unit are operated according to the switched signal. Item 6. The signal control circuit according to Item 5. The signal control circuit according to claim 1 or 5,
The write timing is controlled by a signal output from the signal selection means. An image forming apparatus characterized by the above.

Images