JP3770091B2 - Cache control method and cache control circuit - Google Patents

Description

このようにして、使用されないキャッシュラインに関しては、ＲＵカウンタの値が上がってゆき、使用される可能性が低いラインであると認識される。このＲＵカウンタ値がＲＵカウンタ制限値レジスタを超えない場合は、リプレース対象から外すことによって、使用される可能性の高いラインがキャッシュに残ることになる。
【００３６】
これらの動作を実現する本特許の特徴となる２次キャッシュの構成について、図２に基づいて説明する。ＶＬＤ範囲ＲＥＧ−１（値と有効ビットで構成され、有効ビットが点灯していない時、比較結果はｎｏｎ−ａｃｔｉｖｅである）は、乗算器−４によって計算された〔ＶＬレジスタ−２の出力〕＊〔ディスタンスレジスタ−３の出力〕と比較され、比較器−５の比較結果信号によって、ミス時にキャッシュに登録するか否かを決定する。命令コードレジスタ（ＯＰＣ）−１７の値から命令デコーダ−７によって、ＶＬＤ信号（信号線７０６）及びキャッシュ非登録ＶＬＤ信号（信号線７１０）を生成する。
【００３７】
ＡＮＤゲート−６は、ＶＬＤが範囲を超えるものであったことを示す信号を生成する。ＡＮＤゲート−９は、ＲＵカウンタ制限値ＲＥＧ−１２（値と有効ビットとで構成され、有効ビットが点灯していない時は、比較結果はＮｏｎ−ａｃｔｉｖｅである）とＲＵカウンタ−３０の値を比較する比較器−８の比較結果信号より、時間的局所性の解析結果の信号が生成される。ＯＲゲート−１０は、Ｎｏｎ−Ｃａｃｈａｂｌｅ（キャッシュ非登録）の判断結果信号を出力し、その結果信号をキャッシュ非登録指示フラグ−１１が受ける。
【００３８】
有効フラグ−１３は、Ａステージに１次キャッシュからのブロックロード、あるいは、ＶＰＵからのベクトルメモリアクセス命令のリクエストが有効であることを示し、２Ｗａｙセレクタ−１９は命令コードレジスタ（ＯＰＣ）−１７ヘ格納する値を選択する。
【００３９】
ＯＰＣ−１７及びアドレスレジスタ（ＡＤＲ）−１４には、Ａステージに存在する命令のコードとアドレスが格納される。ＯＲゲート−１５は、１次キャッシュからのブロックロード、あるいは、ＶＰＵからのベクトルメモリアクセス命令のリクエストが有効の出力を生成する。
【００４０】
ＷＥフラグ−１６の点灯するケースは、ストア命令がｗｒｉｔｅヒット時と、キャッシュミスリプライのデータを書き込む時である。その２つのタイミングをＯＲゲート−２０で生成している。前者はキャッシュヒット判定部−３３から、後者はＭｉｓｓＲＥＱ制御部−３６からそれぞれ送られる。また、その時のアドレスは、１次キャッシュ、ＶＰＵ、Ｂステ−ジのアドレスレジスタ−２６、ＭｉｓｓＲＥＱ制御部−３６から送られる、各々、１次キャッシュブロックロードアドレス、ベクトルメモリアクセス命令のアドレス、ストアｗｒｉｔｅヒット時のアドレス、キャッシュミスリプライのアドレスを、４Ｗａｙセレクタ−１８で選択するものである。
【００４１】
ＷＤＲ（Ｗｒｉｔｅ Ｄａｔａ Ｒｅｇｉｓｔｅｒ）−２０は、ＤＡ（Ｄａｔａ Ａｒｒａｙ）−３２に対する書き込みデータレジスタである。２Ｗａｙセレクタ−２１は、ストアｗｒｉｔｅヒット時のストアデータ、キャッシュミスリプライデータを選択する。２Ｗａｙセレクタ−２３は、１次キャッシュ／ＶＰＵからのストアリクエストのデータを選択し、ストアデータレジスタ−２２に格納する。ストアがｗｒｉｔｅヒットした場合、ストアデータレジスタ−２４で１サイクル持ち回った後、ＷＤＲ−２０に格納し、そしてＤＡ−３２に書き込む。有効フラグ−２５、アドレスレジスタ−２６、ストアデータレジスタ−２４、キャッシュミスフラグ−２７は、いずれもＢステージの情報である。
【００４２】
キャッシュ有効ビット−２９は、キャッシュのラインが有効であることを示す。アドレスアレイ（ＡＡ）−３１は、対応するラインが如何なるアドレスのデータであるかを示す。データアレイ−３２は、キャッシュデータを格納する。アドレス比較器−２８は、ＡＡ−３１の出力を読んで、アドレスレジスタ−１４の値と比較し、キャッシュミスを判定し、その結果をキャッシュミスフラグ−２７に格納する。
【００４３】
キャッシュヒット判定部−３３は、Ｂステージの制御情報を使用して、ＲＵカウンタ−３０を更新するための制御信号を生成する。ＤＡ−３２から読んだキャッシュデータと、メモリからのキャッシュミスリプライデータとを２Ｗａｙセレクタ−３４が選択し、ＲＤＲ（Ｒｅａｄ Ｄａｔａ Ｒｅｇｉｓｔｅｒ）−３５に格納する。
【００４４】
次に、図３に基づいて、本実施例が前提としている２次キャッシュ構成について説明する。本実施例では、ラインサイズ１２８Ｂ×２５６エントリ（容量３２ＫＢ）のダイレクトマップ方式を前提として説明する。このキャッシュの場合、ＡＡ（アドレスアレイ）及びＤＡ（データアレイ）から構成され、ＡＡに格納されるＩＮＤＥＸアドレスに対応するタグアドレスとリクエストのアドレスが比較され、キャッシュヒットの判定が行われる。メモリアクセスリクエストのアドレスは全体で４０ｂｉｔであり、そのうち上位２５ビットはＴＡＧアドレス、下位７ビットはラインアドレス、中間の８ビットはＩＮＤＥＸアドレスというように構成される。
【００４５】
次に、図２中のＲＵカウンタ−３０の周辺回路について、図４に基づいて説明する。ＲＵカウンタ−３０は、キャッシュのエントリに存在し、ＡＤＲ−１４の値に応じてデコーダ１４３とセレクタ３０１で選択され、その出力がＣａｃｈａｂｌｅ決定回路に送られる。
【００４６】
キャッシュヒット判定部３３は、ＩＮＤＥＸアドレスのデコーダ３３１、命令デコーダ３３２を使って、ＲＵカウンタ−３０に対して、キャッシュヒット時の状況を報告する信号を出力する。デコーダ３３１は、ＩＮＤＥＸアドレスの２５６ビットのデコード信号を生成する。命令デコーダ３３２は、信号線３３２１にキャッシュ入りロード命令デコード信号を、そして信号線３３２２にキャッシュ入りストア命令デコード信号をそれぞれ生成する。信号線３３３０の信号は、Ｂステージに存在する有効なメモリロード命令がヒットしたことを示す。信号線３３３１の信号は、あるキャッシュエントリで、Ｂステージに存在する有効なメモリロード命令がヒットしたことを示す。また、ストア命令でのｗｒｉｔｅヒット検出信号を信号線３３３２に生成し、Ｂステージの次のタイミングでＷＥフラグを点灯させ、キャッシュにストアデータを書き込む。
【００４７】
次に、図９に基づいてＶＬ＝２の時のＶＬＤ命令がキャッシュヒットした場合の動作について説明する。２次キャッシュをアクセスする命令は、Ａステージで命令コード、アドレスが、各々、ＯＰＣ−１７、ＡＤＲ−１４に設定される。Ｂステージで、１ｓｔ／２ｎｄリクエストが両方ヒットした場合、次のタイミングは両方ともＷステージに移行し、読み出しデータがＲＤＲ−３５を介してＶＰＵに送られる。
【００４８】
次に、図１０に基づいてＶＬ＝２の時のＶＳＴ命令がキャッシュヒットした場合の動作について説明する。Ａステージで命令コード、アドレス、ストアデータが、各々、ＯＰＣ−１７、ＡＤＲ−１４、ストアデータ−２２に設定される。Ｂステージで、１ｓｔ／２ｎｄリクエストが両方ヒットした場合、次のタイミングは両方ともストアデータが、ストアデータ−２２に格納され、ＷＥ−１６が点灯して、ＤＡ−３２に書き込まれる。
【００４９】
次に、図１１に基づいてＶＬ＝２の時のＶＬＤ命令がキャッシュミスした場合の動作について説明する。Ａステージで命令コード、アドレスが、各々、ＯＰＣ−１７、ＡＤＲ−１４に格納され、Ｂステージでミスが判定される。それと同時にＶＬ−２、ｄｉｓｔａｎｃｅ−３の値とＡＤＲ−２６、さらに、ＶＬＤ範囲ＲＥＧ−１との比較によって、Ｃａｃｈａｂｌｅであることを判定する。ここでのＣａｃｈａｂｌｅ判定条件は、〔ＶＬＤ範囲ＲＥＧ−１〕＞〔ＶＬ〕＊〔ｄｉｓｔａｎｃｅ〕である。キャッシュミス時のメモリリクエストは、１ライン分データのｂｌｏｃｋロ−ドとしてＡＴＢへ送られ、その後ミスリプライ有効信号としてターゲットになるワードデータから順に帰ってくる。そして、タイミング▲８▼及び▲９▼でＷＥ−１６を点灯させ、キャッシュに登録するとともにＲＤＲ−３５を介してＶＰＵにリプライデータを送出する。さらに、残りのキャッシュラインデータをキャッシュへ書き込むために、タイミング（１０）以後でも、ＷＥ−１６が点灯する。この場合、従来技術でも説明したように、後続命令の発行を止める必要がある。
【００５０】
次に、図１２に基づいてＶＬ＝２の時のＶＳＴ命令がキャッシュミスした場合の動作について説明する。Ａステージで、命令コード、アドレス、ストアデータが、各々ＯＰＣ−１７、ＡＤＲ−１４、ストアデータ−２２に設定される。Ｂステージで、１ｓｔ／２ｎｄリクエストが両方ミスした場合、次のタイミングで両方ともＡＴＢへのリクエストとして送出される。
【００５１】
次に、図１３に基づいてＶＬ＝２の時のＶＬＤ命令がキャッシュミスし、且つＮｏｎ‐ｃａｃｈａｂｌｅとなった場合の動作について説明する。Ａステージで命令コード、アドレスが、各々ＯＰＣ−１７、ＡＤＲ−１４に格納され、Ｂステージでミスが判定される。それと同時にＶＬ−２、ｄｉｓｔａｎｃｅ−３の値とＡＤＲ−２６、さらに、ＶＬＤ範囲ＲＥＧ−１との比較によって、Ｎｏｎ‐ｃａｃｈａｂｌｅであることを判定する。ここでのＣａｃｈａｂｌｅ判定条件は、〔ＶＬＤ範囲ＲＥＧ−１〕＜＝〔ＶＬ〕＊〔ｄｉｓｔａｎｃｅ〕である。キャッシュミス時のメモリリクエストは、要求するワードデータのみのリクエストとしてＡＴＢへ送られ、その後ミスリプライ有効信号として帰ってくる。しかし、Ｎｏｎ‐ｃａｃｈａｂｌｅであるため、ＷＥ−１６は点灯せず、リプライデータを単にＶＰＵへ返すだけである。したがって、その後のリフィル動作が発生しないので、その分後続命令の待ちが発生しない点で図１１の動作と異なる。
【００５２】
次に、図１４に基づいて、本特許におけるキャッシュ登録判定にかかわるＶＬＤ範囲ＲＥＧ−１、ＲＵカウンタ制限値ＲＥＧ−１３への命令による書き込み動作について説明する。上記２つのレジスタは、ＬＣＲＧ命令によってセットされる。その命令のＹフィールドで指定されたレジスタ内容にしたがって各々のレジスタに値を格納する。本発明における機能を有効にしたい場合は、各々のＶビットに“１”を立てる必要がある。一方、ＬＣＲＧ命令の動きとしては、Ａステージに到着する１サイクル前にＶＰＵからの指示によって、ＶＬＤ範囲ＲＥＧ（Ｖ、ｄａｔａ）−１、ＲＵカウンタ制限値ＲＥＧ（Ｖ、ｄａｔａ）−１３に設定される。
【００５３】
図１５は、図９〜図１３におけるＶＬＤ命令及びＶＳＴ命令が発生した場合の動作についてフローチャートとしてまとめたものである。図左側に示すフローのように、ＶＬＤ命令リクエストが発生すると、キャッシュヒットか否かが判定され、ヒットした場合は、キャッシュを読んでＶＰＵに返す（図９に対応するフロー）。
【００５４】
ヒットしない場合には、次いで、Ｃａｃｈａｂｌｅか否かが判定される。Ｃａｃｈａｂｌｅである場合には、ＡＴＢへ１ライン分のブロックＬＤリクエストを発行し、リプライターゲットデータをＶＰＵに返して、キャッシュにブロックデータを書き込む（図１１に対応するフロー）。
【００５５】
他方、Ｃａｃｈａｂｌｅでない場合は、ＡＴＢへ必要なワードのみのリクエストを発行し、そしてリプライターゲットデータをＶＰＵへ返す（図１３に対応するフロー）。
【００５６】
図１５右側のようにＶＳＴ命令リクエストが発生すると、キャッシュヒットか否かが判定される。ヒットした場合には、Ｃａｃｈｅにデータの書き込みを行う(図１０に対応するフロー）。他方、ヒットしない場合には、ＡＴＢへメモリ書き込みのリクエストを発行する(図１２に対応するフロー）。
【００５７】
【効果】
本発明にかかるキャッシュ制御方法並びに制御回路によれば、ロードリクエストの性質、あるいは、ヒットしたラインの履歴によって、キャッシュに登録させるロードにするか否かをＨＷが動的に判断することになる。
【００５８】
また、ＶＬＤ範囲レジスタとＲＵカウンタ制限値レジスタの更新によって、判断方法をＳＷが明示的に指定することができる。それによって、発明の背景で説明したような問題点を解決し、参照のローカリティが厳密な意味で保証されないプログラムであっても、キャッシュによる性能向上効果を得ることができる。
【図面の簡単な説明】
【図１】本発明の実施例におけるキャッシュ制御回路の全体構成図である。
【図２】本発明の実施例における２次キャッシュ周辺回路の構成図である。
【図３】本発明の実施例における２次キャッシュ構成図である。
【図４】ＲＵカウンタ制御回路周辺構成図である。
【図５】キャッシュリフィル時の性能低下について説明した図である。
【図６】本発明の実施例におけるＶＬＤ命令仕様を示す図である。
【図７】科学技術計算におけるメモリアクセスの局所性について説明した図である。
【図８】局所性のないプログラムにおいてキャッシュが意味をなさない例を説明した図である。
【図９】ＶＬ＝２の時のＶＬＤ命令がキャッシュヒットした時の動作について説明した図である。
【図１０】ＶＬ＝２の時のＶＳＴ命令がキャッシュヒットした時の動作について説明した図である。
【図１１】ＶＬ＝２の時のＶＬＤ命令がキャッシュミスした時の動作について説明した図である。
【図１２】ＶＬ＝２の時のＶＳＴ命令がキャッシュミスした時の動作について説明した図である。
【図１３】ＶＬ＝２の時のＶＬＤ命令がキャッシュミスし、且つ、Ｎｏｎｃａｃｈａｂｌｅとなった時の動作について説明した図である。
【図１４】キャッシュ登録判定にかかわるレジスタへの命令による書き込み動作について説明した図である。
【図１５】図９ないし図１３に対応するＶＬＤ命令及びＶＳＴ命令の動作に関するフロー図である。
【符号の説明】
ＳＰＵ スカラプロセッサユニット
ＶＰＵ ベクトルプロセッサユニット
ＡＴＢ アドレス変換バッファ
ＩＯＰ 入出力処理部
ＶＬＤ ベクトルロード
ＶＬ ベクトル長
ＡＡ アドレスアレイ
ＤＡ データアレイ
ＷＤＲ 書き込みデータレジスタ
ＲＤＲ 読み出しデータレジスタ
ＯＰＣ 命令コードレジスタ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a cache control method and a cache control circuit for controlling a cache memory used in various information processing systems.
[0002]
[Prior art]
In order to eliminate the bottleneck of memory access in various information processing systems, a technology that uses a small-capacity and high-speed buffer memory called a cache has been used in most systems for a long time. The effects of using the cache memory are the following two. The first is that it can be configured with a smaller capacity than the main memory or the like, so that it can be placed near the processor, for example, in the same LSI, and the latency of the operand data can be greatly reduced. .
[0003]
The second effect is that the throughput required for memory access can be suppressed particularly when writing to the memory is not always performed as in the case of a store-in type cache. Therefore, the memory structure can be simplified, which is advantageous in terms of cost, and conversely, by suppressing the memory access frequency, it is possible to avoid the memory interface request contention, so that the performance improvement can be realized.
[0004]
In order for this cache memory system to be effective, it is necessary to assume that the memory access behavior in the actual program shown below usually has a certain property. This is due to the nature of memory access called locality of reference (hereinafter also referred to as locality). That is, spatial locality (referenced addresses are fixed in a certain part) and temporal locality (referenced addresses are concentrated within a certain time).
[0005]
Here, the operation at the time of a cache miss will be briefly described. However, since there are many documents on the operation of the cache memory, for example, it is described in detail in “Parallel Computer” by Amano Hideharu (Shokodo), the description of the operation not directly related to the present invention is omitted.
[0006]
First, lines with the same cache line address already registered in the cache are evicted. In the case of a store-through cache, since it is always consistent with the memory, it is only necessary to overwrite the cache with a new line. However, in the case of a store-in type cache, since consistency with the memory is not maintained, it is necessary to write the cache line to be evicted into the memory.
[0007]
In addition, a block load request for line data is generated for refilling a new line. There is a process of bringing unnecessary data to the memory, but on the other hand, there is an advantage that implicit prefetching is performed, so the advantages and disadvantages are not completely decided.
[0008]
This operation is described in FIG. 5. “A”, “B”, and “W” are stages in which a load (hereinafter also referred to as LD) instruction issues a memory access request and a stage in which a cache access ends. , Means that it exists in the register write stage.
[0009]
First, LD-1 is a timing at the time of a cache hit (hit), and in this case, it ends in only three cycles. LD-2 is an operation in the case of a cache miss (miss), and it is common that the refill data is requested from the memory, and the target data is returned first. -2 can move to the W stage. However, it takes time to write data for one line to the cache for refilling, and during that time, subsequent cache access instructions cannot be issued. LD-3 is a cache bypass load timing in which data is not registered in the cache, and a difference from LD-2 is that, when a miss occurs, miss reply data is not registered in the cache.
[0010]
In the case of memory access without locality of reference, since the issue of subsequent cache access instructions during rewrite data cache writing is not suppressed, LD-3 is superior in performance from this case alone. I can say that.
[0011]
The cache control as described above causes the following problems when the locality of the assumed reference is lost. Problem 1) Putting a line that is LD only once into the cache requires extra storage and loading of the cache line data, compared to when no data is registered in the cache. Problem 2) Despite being a useful cache line, it is replaced.
[0012]
There is a science and technology calculation program that is said to have no locality of reference. However, in recent years, the cache capacity in microprocessors has been increased from KB units to MB units due to the continuous advancement of LSI technology. In addition, the program optimization technique considering the cache follows the trend of the cache capacity, and the performance of the science and technology calculation program has been improved even in the microprocessor of the store-in type cache. However, no matter how advanced the optimization technology of the compiler, there is a limit to realizing a high cache hit rate by recognizing the memory access behavior from the program before execution.
[0013]
By the way, there is a vector computer as an apparatus for efficiently executing a scientific and technological calculation program. In a vector type computer, processing for a register storing a plurality of word data called a vector register can be defined by one instruction called a vector instruction. For example, a vector load (hereinafter also referred to as VLD) instruction loads a value of a vector length register (hereinafter also referred to as VL), and stores the read data in a register called a vector register in which a plurality of words are collected. Conversely, a vector store (hereinafter also referred to as VST) stores a plurality of word data in a vector register in a memory.
[0014]
In this vector type computer, for example, when a VLD instruction having a large [distance] * [VL] is issued and it causes a cache miss, many cache lines are replaced by the VLD1 instruction. Among them, if there is a line that has just been used, the data registered in the cache is canceled in anticipation of temporal locality, and the cache line data is refilled again and again. To the situation.
[0015]
[Problems to be solved by the invention]
The present invention provides a cache control circuit that solves the problems of the prior art as described above and can obtain a performance improvement effect by a cache memory even for a program whose locality of reference is not guaranteed in a strict sense. It is to be.
[0016]
[Means for solving the problems]
  An object of the present invention is to provide a value for defining a vector load instruction access range, a vector length value, and a distance value in a cache control method for an information processing apparatus having a cache memory.And the product of,This comparison resultWhether the vector load instruction data is registered in the cache or unregistered based onFirstMake a decisionFirstThis is solved by a cache control method that selectively executes control of registration or non-registration in the cache according to the determination result.
Furthermore, the problem of the present invention is solved by the cache control method, wherein the value defining the vector load instruction access range is defined by software.
Furthermore, an object of the present invention is to measure the number of cache accesses corresponding to each entry of the cache in the above cache control method, compare the number of cache accesses and the limited number of cache access use, and from the comparison result, Cache control for performing second determination as to whether to register in cache or not, and to selectively execute control of registration or non-registration in cache according to the second determination result and the first determination result Solved by the method.
[0017]
  Furthermore, an object of the present invention is to provide a cache control circuit of an information processing apparatus having a cache memory, a first register that holds a value that defines a vector load instruction access range, a second register that holds a vector length, A third register for holding a distance; and the first registerRegister value andThe secondRegister vector length andThird registerProduct with distanceThe value of theCompare with,Based on this comparison resultDetermines whether vector load instruction data is registered or unregistered in the cacheFirst judgmentCircuit,Determination of the first determination circuitThis is solved by a cache control circuit including a fourth register for holding the result and a miss reply control circuit for selectively controlling registration or non-registration in the cache according to the determination result of the fourth register.
Another object of the present invention is to provide a cache control circuit for an information processing apparatus having the cache memory, wherein the value of the first register is set by software.
[0018]
  Another object of the present invention is to provide a fifth register for storing the limited number of times of cache access in a cache control circuit of an information processing apparatus having a cache memory, and a result of measuring the number of cache accesses corresponding to each entry in the cache. A sixth register group for holdingCache access count measurement resultWhether to register or not register in the cache is determined based on the result of comparing the control circuit that updates the value of the cache and the sixth register value and the fifth register value corresponding to the accessed cache entry.Second decisionCircuit andHave,SaidFourth registerHolds the results of the first determination circuit and the second determination circuit.,The miss reply control circuit selectively executes control of registration or non-registration in the cache according to the determination result of the fourth register.This is advantageously solved by a cache control circuit.
[0019]
According to the cache control method and the control circuit of the present invention, hardware (hereinafter also referred to as HW) determines whether or not to make a load to be registered in the cache memory according to the nature of the load request or the history of the hit line. Judge dynamically.
[0020]
Also, software (hereinafter, also referred to as SW) can explicitly specify the determination method by updating the VLD range register and the RU counter limit value register. As a result, the problems described in the background of the invention can be solved, and the performance improvement effect by the cache memory can be obtained even for a program whose reference locality is not guaranteed in a strict sense.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of a cache control device according to the present invention will be described with reference to the accompanying drawings. This cache control apparatus is applied to a basic configuration as shown in FIG. The scalar processor unit (hereinafter also referred to as SPU) -1 performs the decoding / execution instruction of all instructions and the execution of scalar instructions. The primary cache unit-2 stores only data used in scalar memory access system instructions. A vector processor unit (hereinafter also referred to as VPU) -3 executes a vector instruction in accordance with an instruction from SPU-1.
[0022]
The secondary cache unit-4 stores data used in both the scalar system / vector system. An address conversion buffer (hereinafter referred to as ATB) -5 is a buffer for converting a logical address into a physical address. The memory unit-6 includes a memory and a memory access control unit. IOP-7 performs input / output processing.
[0023]
In the case of a scalar LD, when an LD request is issued from the SPU-1 through the signal line 102 and a miss occurs in the primary cache unit-2, data is transferred to the secondary cache unit-4 via the signal line 204 as a line data block request. Go to find. If there is also a mistake, a memory request is sent to the ATB 5 via the signal line 405, converted into a physical address, and sent to the memory unit -6 via the signal line 506. The data read from the memory unit -6 returns to the secondary cache unit-4 via the signal line 604 and the line data is stored, returns to the primary cache unit-2 via the signal line 402, The line data is registered. At that time, the target data of the first LD instruction is sent to the SPU-1 via the signal line 201.
[0024]
Next, before describing the behavior of the VLD instruction, the specification of the VLD instruction will be described with reference to FIG. In VPU-3, there is a register file that can store a plurality of element data, also called a vector register. The VLD instruction collectively loads the number of memory loads specified by the register VL specified by Ry (distance) and Rz (start address) sent from the SPU-1 to the vector register specified by Vx. The instruction to perform.
[0025]
Here, in order to describe an embodiment of the present invention, a basic configuration as shown in FIG. 1 is used. A register VL is a register that can be rewritten by software in response to an instruction LVL, and exists in VPU-3. The operation of the VLD instruction will be described with reference to the block diagram of FIG. The VLD instruction is decoded by the SPU-1, and as a result, an execution instruction is sent to the VPU-3 via the signal line 103. In the VPU-3, the VLD instruction is processed. At this time, the start address, the distance, and the VL (vector length) are sent to the secondary cache unit-4 through the signal line 304.
[0026]
In the secondary cache unit-4, if a miss occurs, it becomes a block request for the corresponding line, passes through the ATB-5 like the scalar LD, and sends the reply data from the memory unit-6 via the signal line 604 to the secondary cache. Send to unit-4. The reply data received by the secondary cache unit-4 is stored in the corresponding cache line, and at the same time, only the target data is sent to the VPU-3 via the signal line 403 and stored in the vector register. Such processing is executed by the number specified by VL. However, when the secondary cache hits, only the read data of the secondary cache is sent to the VPU-3 via the signal line 403.
[0027]
Here, the cacheable determination circuit using the VLD range register or the RU counter limit value register according to the present invention does not necessarily take this VLD instruction into the cache when a cache miss occurs. In this case, a block load request of the secondary cache line size is not issued, a request for each element of the VLD is issued to the signal line 405, and the reply data sent via the signal line 604 is passed. And send it to VPU-3 via the signal line 403.
[0028]
First, the operation of the present invention by the VLD range register will be described. All conventional vector memory accesses were not cached. However, as described above, due to the significant increase in cache capacity due to advances in LSI technology and advances in optimization technology using compilers, a certain amount of cache is used in scientific and technical calculations. This makes it possible to realize reference locality that is meaningful. However, there are some parts that cannot be optimized to maintain locality. This is shown in FIG.
[0029]
In the non-local part, processing such as fetching vector operand data with a wide range of VLD instructions, calculating it, and writing it back to the memory with the VST instruction is performed. There is almost no reading. In such a case, it is meaningless to take the memory data of the VLD into the cache.
[0030]
FIG. 8 illustrates a case where the distance of the VLD instruction is 128B and the VL is 256, and the case is registered in the cache (line size 128B). Since the element data of the VLD instruction exists only in a certain part of the line data, the memory LD data requires only 8B × 256 (= 2 KB) for one VLD instruction, but 128B × 256 (= 32KB) blocks LD are generated, and useless LD requests are made for 30 KB. Furthermore, in the 32 KB cache, this VLD instruction creates a tragic situation in which the cache data required in the part where the reference locality is maintained as shown in FIG. 7 is overwritten. .
[0031]
As another means for avoiding such a situation, there is a method of explicitly designating from the beginning that data is not registered in the cache memory. The advantage of this method is that more effective cache control is possible because it is possible to consider the locality of the reference, which is insufficient only by focusing on the value such as address distance. If a VLD instruction not registered in the cache is executed, the cache registration is not unconditionally performed. However, if the data to be loaded exists in the cache memory, the cache memory is naturally read out.
[0032]
However, it is extremely difficult to determine by SW (software: compiler) whether or not data is registered in the cache memory, and a certain amount of support by HW is required. Therefore, in the present invention, an inefficient cache operation as shown in FIG. 8 can be avoided by implementing a circuit that determines whether the area of the VLD access area is local or not with the VLD range register. it can.
[0033]
Next, cache registration control focusing on temporal locality by the RU counter limit value register will be described. Temporal locality means that once accessed data tends to be accessed again. Such a line must be prevented from being evicted from the cache due to a cache miss during other memory accesses. Regarding the eviction algorithm in this cache, there is an LRU algorithm as in the prior art.
[0034]
However, this is useful in a cache constituted by a plurality of ways, and in the case of a direct map configuration, access on the same line is unconditionally expelled. Further, in the direction of enlarging the cache capacity, a direct map type cache is generally used from the viewpoint of HW cost.
[0035]
Further, if the cache registration data is not accessed at least twice as long as it exists in the cache, the cost of the block LD for one line is directly adversely affected. Therefore, in order to determine that the line has recently been accessed frequently, information called an RU counter is provided in each line. The operation logic of the RU counter is as follows.

In this way, regarding a cache line that is not used, the value of the RU counter increases, and it is recognized that the line is unlikely to be used. If this RU counter value does not exceed the RU counter limit value register, a line that is likely to be used remains in the cache by removing it from the replacement target.
[0036]
The configuration of the secondary cache, which is a feature of this patent that realizes these operations, will be described with reference to FIG. The VLD range REG-1 (consisting of a value and a valid bit and the comparison result is non-active when the valid bit is not lit) was calculated by the multiplier-4 [output of the VL register-2] * [Output of distance register-3] is compared, and the comparison result signal of the comparator-5 determines whether or not to register in the cache at the time of a miss. A VLD signal (signal line 706) and a cache non-registration VLD signal (signal line 710) are generated from the value of the instruction code register (OPC) -17 by the instruction decoder-7.
[0037]
AND gate-6 generates a signal indicating that VLD was out of range. The AND gate-9 sets the RU counter limit value REG-12 (consisting of a value and a valid bit, and when the valid bit is not lit, the comparison result is Non-active) and the value of the RU counter-30. An analysis result signal of temporal locality is generated from the comparison result signal of the comparator-8 to be compared. The OR gate -10 outputs a non-cacheable (cache non-registration) determination result signal, and the cache non-registration instruction flag-11 receives the result signal.
[0038]
The valid flag-13 indicates that the block load from the primary cache in the A stage or the request for the vector memory access instruction from the VPU is valid, and the 2-way selector-19 is set to the instruction code register (OPC) -17. Select the value to store.
[0039]
The OPC-17 and the address register (ADR) -14 store the code and address of an instruction existing in the A stage. The OR gate -15 generates an output in which a block load from the primary cache or a request for a vector memory access instruction from the VPU is valid.
[0040]
The case where the WE flag-16 is lit is when the store instruction hits write and when the cache miss reply data is written. The two timings are generated by the OR gate-20. The former is sent from the cache hit determination unit -33, and the latter is sent from the MissREQ control unit -36. Also, the addresses at that time are sent from the primary cache, VPU, B stage address register 26, and MissREQ control unit 36, respectively, the primary cache block load address, the address of the vector memory access instruction, and the store write. The address at the time of hit and the address of the cache miss reply are selected by the 4-way selector-18.
[0041]
WDR (Write Data Register) -20 is a write data register for DA (Data Array) -32. The 2Way selector-21 selects store data and cache miss reply data at the time of store write hit. The 2-way selector -23 selects store request data from the primary cache / VPU and stores it in the store data register -22. When a write hit occurs in the store, the store data register -24 goes around for one cycle, and is then stored in the WDR-20 and written in the DA-32. The valid flag-25, address register-26, store data register-24, and cache miss flag-27 are all B stage information.
[0042]
Cache valid bit -29 indicates that the cache line is valid. The address array (AA) -31 indicates what address data the corresponding line is. The data array-32 stores cache data. The address comparator -28 reads the output of AA-31, compares it with the value of the address register-14, determines a cache miss, and stores the result in the cache miss flag -27.
[0043]
The cache hit determination unit -33 uses the B stage control information to generate a control signal for updating the RU counter-30. The 2-way selector 34 selects the cache data read from the DA-32 and the cache miss reply data from the memory, and stores the selected data in an RDR (Read Data Register) -35.
[0044]
Next, based on FIG. 3, the secondary cache configuration assumed in this embodiment will be described. In the present embodiment, description will be made on the premise of a direct map system having a line size of 128 B × 256 entries (capacity: 32 KB). In the case of this cache, it is composed of AA (address array) and DA (data array), the tag address corresponding to the INDEX address stored in AA is compared with the address of the request, and a cache hit is determined. The address of the memory access request is 40 bits as a whole, of which the upper 25 bits are TAG address, the lower 7 bits are line address, and the middle 8 bits are INDEX address.
[0045]
Next, peripheral circuits of the RU counter-30 in FIG. 2 will be described with reference to FIG. The RU counter-30 exists in the cache entry, is selected by the decoder 143 and the selector 301 in accordance with the value of ADR-14, and the output is sent to the cache determination circuit.
[0046]
The cache hit determination unit 33 uses the INDEX address decoder 331 and the instruction decoder 332 to output a signal reporting a cache hit situation to the RU counter-30. The decoder 331 generates a 256-bit decode signal having an INDEX address. The instruction decoder 332 generates a cached load instruction decode signal on the signal line 3321 and a cached store instruction decode signal on the signal line 3322, respectively. The signal on the signal line 3330 indicates that a valid memory load instruction existing in the B stage has been hit. A signal on the signal line 3331 indicates that a valid memory load instruction existing in the B stage is hit in a certain cache entry. Further, a write hit detection signal in the store instruction is generated on the signal line 3332, the WE flag is turned on at the next timing of the B stage, and the store data is written into the cache.
[0047]
Next, the operation when the VLD instruction when VL = 2 has a cache hit will be described with reference to FIG. For the instruction to access the secondary cache, the instruction code and address are set to OPC-17 and ADR-14, respectively, at the A stage. When both the 1st / 2nd requests are hit in the B stage, both the next timing shifts to the W stage, and the read data is sent to the VPU via the RDR-35.
[0048]
Next, the operation when the VST instruction when VL = 2 causes a cache hit will be described with reference to FIG. In the A stage, the instruction code, address, and store data are set to OPC-17, ADR-14, and store data-22, respectively. When both the 1st / 2nd requests are hit in the B stage, the store data is stored in the store data-22 at the next timing, and WE-16 is lit and written to DA-32.
[0049]
Next, the operation when the VLD instruction when VL = 2 causes a cache miss will be described with reference to FIG. The instruction code and address are stored in OPC-17 and ADR-14, respectively, at the A stage, and a miss is determined at the B stage. At the same time, the values of VL-2 and distance-3 are compared with ADR-26, and further, the VLD range REG-1 is determined to be cacheable. The cache determination condition here is [VLD range REG-1]> [VL] * [distance]. A memory request at the time of a cache miss is sent to the ATB as a block load of data for one line, and then returns in order from the word data as a target as a miss reply valid signal. Then, the WE-16 is turned on at timings (8) and (9), registered in the cache and sent reply data to the VPU via the RDR-35. Furthermore, in order to write the remaining cache line data into the cache, WE-16 is lit even after timing (10). In this case, as described in the prior art, it is necessary to stop issuing subsequent instructions.
[0050]
Next, the operation when the VST instruction when VL = 2 makes a cache miss will be described with reference to FIG. In the A stage, the instruction code, address, and store data are set to OPC-17, ADR-14, and store data-22, respectively. If both the 1st / 2nd requests miss in the B stage, both are sent as requests to the ATB at the next timing.
[0051]
Next, an operation when the VLD instruction when VL = 2 is a cache miss and becomes non-cacheable will be described with reference to FIG. The instruction code and address are stored in the OPC-17 and ADR-14, respectively, at the A stage, and a miss is determined at the B stage. At the same time, it is determined to be non-cacheable by comparing the values of VL-2 and distance-3 with ADR-26 and the VLD range REG-1. The cache determination condition here is [VLD range REG-1] <= [VL] * [distance]. The memory request at the time of a cache miss is sent to the ATB as a request for only the requested word data, and then returns as a miss reply valid signal. However, since it is non-cacheable, WE-16 is not lit, and reply data is simply returned to the VPU. Therefore, since the subsequent refill operation does not occur, the operation is different from the operation of FIG.
[0052]
Next, based on FIG. 14, a write operation by an instruction to the VLD range REG-1 and the RU counter limit value REG-13 related to the cache registration determination in this patent will be described. The two registers are set by the LCRG instruction. A value is stored in each register according to the contents of the register designated in the Y field of the instruction. To make the function of the present invention effective, it is necessary to set "1" to each V bit. On the other hand, the movement of the LCRG instruction is set to the VLD range REG (V, data) -1 and the RU counter limit value REG (V, data) -13 by an instruction from the VPU one cycle before the arrival at the A stage. The
[0053]
FIG. 15 summarizes the operation when the VLD instruction and the VST instruction in FIGS. 9 to 13 are generated as a flowchart. As shown in the flow on the left side of the figure, when a VLD instruction request occurs, it is determined whether or not there is a cache hit. If a hit is found, the cache is read and returned to the VPU (flow corresponding to FIG. 9).
[0054]
If there is no hit, it is next determined whether or not it is cacheable. If it is cacheable, it issues a block LD request for one line to the ATB, returns the reply target data to the VPU, and writes the block data to the cache (flow corresponding to FIG. 11).
[0055]
On the other hand, if it is not Cacheable, a request for only the necessary word is issued to the ATB, and reply target data is returned to the VPU (flow corresponding to FIG. 13).
[0056]
When a VST instruction request is generated as shown on the right side of FIG. 15, it is determined whether or not there is a cache hit. If there is a hit, data is written to Cache (flow corresponding to FIG. 10). On the other hand, if there is no hit, a memory write request is issued to the ATB (flow corresponding to FIG. 12).
[0057]
【effect】
According to the cache control method and the control circuit according to the present invention, the HW dynamically determines whether or not to make a load to be registered in the cache based on the nature of the load request or the history of the hit line.
[0058]
Further, the SW can explicitly specify the determination method by updating the VLD range register and the RU counter limit value register. As a result, the problems described in the background of the invention can be solved, and the performance improvement effect by the cache can be obtained even for a program whose reference locality is not guaranteed in a strict sense.
[Brief description of the drawings]
FIG. 1 is an overall configuration diagram of a cache control circuit according to an embodiment of the present invention.
FIG. 2 is a configuration diagram of a secondary cache peripheral circuit in the embodiment of the present invention.
FIG. 3 is a secondary cache configuration diagram according to the embodiment of the present invention.
FIG. 4 is a peripheral configuration diagram of an RU counter control circuit.
FIG. 5 is a diagram for explaining performance degradation during cache refill.
FIG. 6 is a diagram showing VLD instruction specifications in the embodiment of the present invention.
FIG. 7 is a diagram illustrating the locality of memory access in scientific and technical calculations.
FIG. 8 is a diagram illustrating an example in which a cache does not make sense in a program without locality.
FIG. 9 is a diagram illustrating an operation when a VLD instruction when VL = 2 has a cache hit.
FIG. 10 is a diagram illustrating an operation when a VST instruction when VL = 2 has a cache hit.
FIG. 11 is a diagram illustrating an operation when a VLD instruction when VL = 2 has a cache miss;
FIG. 12 is a diagram illustrating an operation when a VST instruction when VL = 2 has a cache miss.
FIG. 13 is a diagram illustrating an operation when a VLD instruction when VL = 2 has a cache miss and becomes noncacheable.
FIG. 14 is a diagram illustrating a write operation by an instruction to a register related to cache registration determination.
FIG. 15 is a flowchart relating to the operation of the VLD instruction and the VST instruction corresponding to FIGS. 9 to 13;
[Explanation of symbols]
SPU scalar processor unit
VPU vector processor unit
ATB address translation buffer
IOP I / O processor
VLD vector load
VL vector length
AA address array
DA data array
WDR write data register
RDR read data register
OPC instruction code register

Claims (2)

A cache control method for an information processing apparatus having a direct mapped cache memory,
Compare the value specified by the software and specifying the vector load instruction access range with the product of the vector length value and the distance value,
Based on the result of this comparison, a first determination is made as to whether the data of the vector load instruction is registered in the cache or unregistered,
An RU counter is provided for each line of the cache, and the value of the RU counter is measured.
Compare the value of this RU counter with the value of the RU counter limit value register,
From this comparison result, it performs a second determination of whether the or unregistered to register to the cache,
In the cache control method for selectively executing control of registration or non-registration in the cache according to the determination result of the second determination and the determination result of the first determination,
If there is a hit in the cache line corresponding to the RU counter, the RU counter is cleared to 0,
If a hit occurs in another line other than the cache line corresponding to the RU counter, the value of the RU counter is incremented by 1,
Do not change the value of the RU counter if no line in the cache is hit,
When determining whether or not to replace a cache line due to a cache miss hit, if the value of the RU counter corresponding to the cache line does not exceed the value of the RU counter limit value register, the cache line is A cache control method characterized by excluding from replacement. A cache control circuit of an information processing apparatus having a direct mapped cache memory,
A first register that is set by software and holds a value defining a vector load instruction access range;
A second register holding the vector length;
A third register holding the distance;
Compare the value of the first register with the product of the vector length of the second register and the distance of the third register, and register the data of the vector load instruction in the cache based on the comparison result a first decision circuit which performs one of determination to whether or not registered,
A fifth register for storing the RU counter limit value ;
A sixth register group for holding the value of the RU counter corresponding to each line of the cache;
A control circuit for updating the value of the RU counter ;
A second determination circuit for determining whether to register or not register in the cache from a result of comparing the value of the sixth register and the value of the fifth register corresponding to the accessed cache line ;
A fourth register for holding a determination result of the first determination circuit and a determination result of the second determination circuit ;
According to the judgment result of the fourth register, the cache control circuit and a miss reply control circuit for executing controls of the registration or non-registration to the cache selectively,
The control circuit that updates the value of the RU counter clears the RU counter when it hits the cache line corresponding to the RU counter, and when it hits another line other than the cache line corresponding to the RU counter. the RU counter are those that value incremented by one of, are those not be change the value of the RU counter if you did not hit in any line of the cache,
The second decision circuit, in determining whether to replace the cache line is due to a cache miss, the value of RU counter corresponding to the cache line is stored before Symbol fifth register If it does not exceed the RU counter limit value, it is determined to remove the cache line from the replacement target .
A cache control circuit.

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