JP3778194B2 - Failure detection method and failure detection apparatus for semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and relates to a failure detection method and apparatus capable of efficiently detecting and evaluating a failure of a semiconductor device.

  2. Description of the Related Art In recent years, semiconductor integrated circuits have undergone rapid technological changes such as downsizing, low current consumption, and high speed as well as miniaturization, as well as large scale, high integration, and multifunctional / composite functions. At the same time, testing of semiconductor large scale integrated circuits becomes increasingly important, but makes test development more difficult.

  As a conventional semiconductor failure detection method, there has been a method using quiescent power supply current measurement (hereinafter referred to as IDDQ measurement) that is effective for an open fault, a short-circuit fault, and a stuck-at fault in a semiconductor integrated circuit.

  FIG. 6 is a flowchart showing the IDDQ measurement procedure of the conventional failure detection method. 6, the semiconductor integrated circuit operating condition setting 101 includes a power supply voltage, an input signal voltage level, a frequency, an input signal logic pattern for operating the semiconductor integrated circuit (an input logic pattern for IDDQ measurement is a specific node of the semiconductor integrated circuit). The semiconductor integrated circuit operation start 102, which indicates the setting of the resting state after the toggle is finished, starts the operation of the semiconductor integrated circuit based on the semiconductor integrated circuit operation condition setting 101. The semiconductor integrated circuit operation stop 103 stops the semiconductor integrated circuit operation based on the semiconductor integrated circuit operation condition setting 101. The semiconductor integrated circuit operation stop 103 means a toggle end of a specific node of the semiconductor integrated circuit, and the toggle end node can be arbitrarily set.

  At this time, the power is not turned off even when the toggle is completed. The power supply current measurement waiting time 104 indicates a time for waiting for the end of the change in power supply current of the semiconductor integrated circuit after the operation of the semiconductor integrated circuit is completed. A power supply current measurement 105 indicates a power supply current measurement of the semiconductor integrated circuit.

  In the conventional IDDQ measurement, after the semiconductor integrated circuit operation condition setting 101, the semiconductor integrated circuit operation start 102 is performed, then the semiconductor integrated circuit operation stop 103 is performed, and then the power supply current measurement waiting time 104 is waited. Measurement 105 was taken.

  Note that a point at which the semiconductor integrated circuit operation stop 103 is changed may be changed to measure a plurality of IDDQ measurements.

  As described above, the conventional IDDQ measurement procedure shown in FIG. 6 is a small amount of the dynamic current of the logic LSI in the semiconductor integrated circuit, that is, a small amount of the semiconductor integrated circuit in the stationary state after the period of the power supply current change that occurs at the time of transistor switching ends. A current is measured, and whether there is a failure or not is determined from the magnitude of the current obtained by IDDQ measurement (see, for example, Patent Documents 1 to 3).

  Various methods related to the conventional detection failure method have been devised as shown below.

  1. Delta IDDQ method: A method of taking the difference from the IDDQ value of the adjacent good die by utilizing the fact that the variance of the difference is smaller than the variance σ of the absolute value when IDDQ is measured at multiple points.

  2. Current Ratio method: A method in which a standard distribution of IDDQ is obtained and, for example, a die having a measured value of an average value + 3σ or an average value + 6σ is determined as defective.

3. DECOUPLE method: A method in which regression analysis is performed for all good dies to obtain a contribution rate, and those having a contribution rate less than a certain value (for example, 0.95) are determined to be defective.
JP 2000-230962 A JP 2000-241492 A JP 2001-13200 A

  However, with the high integration and miniaturization of the semiconductor integrated circuit, the operation condition setting 101 that makes the IDDQ value worst becomes complicated, the time for performing the condition setting increases, and the power supply until the dynamic current period ends. Since the current measurement waiting time 104 is increased and the measurement value of the power supply current measurement 105 is a minute value, there is a problem that the measurement takes too much time because the minute current is measured.

  In addition, in an SoC (System on Chip) in which a final product typified by a remote controller or a mobile phone is incorporated in a portable device, the absolute value of the IDDQ itself is a performance index. In addition to the operating power supply current IDD, the smaller the waiting time and standby current, the longer the life of the dry cell or battery. For such a device, it is a problem to measure IDDQ accurately in a short time (because the inside of the SoC is measured in a state where the IDDQ value is worst, and the value itself can be measured with high accuracy).

  An object of the present invention is to provide a new IDDQ measurement method, failure detection method, and failure detection apparatus for a semiconductor integrated circuit in order to solve the conventional problems.

  In order to solve the above-described conventional problems, a new IDDQ measurement method for a semiconductor device according to the present invention sets the operating frequency F of the semiconductor device to f under the same power supply voltage condition while almost all nodes in the semiconductor device are toggled. , F / L, f / M, f / N,... (L, M, N, and O are integers), and at the same time, all input signals input to the semiconductor device are fin, fin / L, fin / M, fin / N,..., And the operating power supply current of each frequency is measured after waiting the same time after operating the semiconductor device. An approximate line with the frequency as a variable is created from the power supply current value measured for each frequency under the above conditions. From the approximation line, the power supply current value obtained by extrapolating the static power supply current value (IDDQ value) when the frequency is 0 is used as a new IDDQ value. The power supply current value when the frequency is 0 can also be obtained by calculation using an extrapolated approximate expression.

  With this configuration, a new IDDQ of the semiconductor device can be obtained in a shorter time than conventional IDDQ measurement.

  Further, it becomes possible to determine a failure of a semiconductor device using a new IDDQ value obtained by this configuration.

  Further, the failure detection apparatus for a semiconductor device according to the present invention provides means for setting the same power supply voltage and operating frequencies F to f, f / L, f / M, f / N,. And means for simultaneously inputting fin, fin / L, fin / M, fin / N,... To the input signal to the semiconductor device in synchronism with the operating frequency of the semiconductor device, and measuring the power supply current under each frequency , Means for measuring with a constant measurement waiting time from the start of operation, means for obtaining an approximate line as a function of frequency using the measured power supply current of each frequency, and removing the power supply current of frequency 0 from the approximate line. And means for obtaining a quiescent power supply current value and means for determining the quality of the semiconductor device based on the quiescent power supply current value. With this configuration, a new IDDQ value of the semiconductor device can be measured.

  When measuring the conventional IDDQ, it takes a very long time until charging / discharging of the internal node of the semiconductor integrated circuit is settled. In addition, the operating power supply current can be measured 4 to 5 times with respect to the time for measuring IDDQ at one point of the conventional IDDQ measurement test pattern. Therefore, the new IDDQ measurement can be measured in a short time. Further, in the new IDDQ measurement method of the present invention, a pattern in which almost all the nodes inside the semiconductor integrated circuit are toggled so as to minimize the difference from the power supply current in the device in which the semiconductor integrated circuit is actually used. Run and measure. Therefore, a new IDDQ value with high failure detection accuracy can be obtained.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a flowchart showing a new IDDQ measurement procedure of the failure detection method for a semiconductor integrated circuit according to the first embodiment of the present invention.

  In FIG. 1, reference numeral 10 denotes a semiconductor integrated circuit operating condition setting. The power supply voltage, the input signal voltage level, the operating frequency F, the input signal frequency fin, and the input signal logic pattern for operating the semiconductor integrated circuit (almost in the semiconductor integrated circuit). (Repeat operation that all nodes toggle). Reference numeral 11 denotes a semiconductor integrated circuit operation start. After the semiconductor integrated circuit operation condition setting 10, the operation of the semiconductor integrated circuit is started. Reference numeral 12 denotes a measurement waiting time, and waits for a certain time after the semiconductor integrated circuit operation start 11. 13 is a power supply current measurement. After a measurement waiting time 12, the power supply current of the semiconductor integrated circuit is measured and the value is stored. Reference numeral 14 denotes a semiconductor integrated circuit operation stop. After the power supply current measurement 13, the operation of the semiconductor integrated circuit is stopped. Reference numeral 15 denotes a frequency change determination. After the semiconductor integrated circuit operation stop 14, the operation frequency switching is determined. If the switching is necessary, the operation is switched to 16, and the operation is shifted to 17 if not necessary. Reference numeral 16 denotes a frequency change setting. When the frequency change determination 15 requires a frequency change, the operating frequency F set in the semiconductor integrated circuit operating condition setting 10 is changed to f / L and the frequency fin of the input signal is also set to fin / L. change. Thereafter, the semiconductor integrated circuit operation start 11 is started. Thereafter, every time the frequency shifts to the frequency change setting 16, the operating frequency is f / M, the input signal frequency is fin / M, the operating frequency is f / N, and the input signal frequency fin / N at the same time. (L, M, N, and O are integers). Reference numeral 17 denotes approximate line creation and approximation function fitting, and each time steps 11 to 16 are repeated, approximation line creation and approximation function fitting using the operating frequency as a variable are performed based on the power supply current value obtained in the power supply current measurement 13. Here, the approximate line of the power supply current value is generally expressed by the following equation.

IDDa = af + IDDX
Here, IDDa is a power supply current value, a and IDDX are constants, f is an operating frequency, and a and IDDX are obtained from approximate lines.

  FIG. 2 is a characteristic diagram in which approximate line creation and approximate function fitting are performed, and shows a characteristic diagram in which the approximate line creation fitting 17 in FIG. 1 of Embodiment 1 of the present invention is performed. 21, 22, 23, and 24 are power supply current values, which were measured according to the procedures 11 to 16, and the obtained power supply current values were plotted with the operating frequency at the time of each power supply current measurement taken on the horizontal axis. 25 is an approximate line, a line that approximately connects the power source current values 21, 22, 23, and 24, and 26 is a point that extends the approximate line 25 with a new IDDQ value and intersects the Y axis, that is, a power source current having a frequency of 0 Value.

FIG. 3 is a characteristic diagram showing a relationship between an actual new IDDQ value obtained by the first embodiment of the present invention and a conventional IDDQ value. In FIG. 3, the new IDDQ value is described as IDDX in order to distinguish it from the conventional IDDQ value. The semiconductor integrated circuit to which the first embodiment of the present invention is applied is a 0.18 μm rule process product, a chip area of 35.14 mm ² , a semiconductor integrated circuit with 209 pins, and the operating current IDD standard is the operating frequency. Operate at 26 MHz, and with 2.80 V applied, 32.55 mA or more is regarded as defective. The waiting time until the power supply current is obtained is 10 ms. In IDDQ measurement, 16 μA or more is regarded as defective when 1.95 V is applied. The IDDQ measurement is performed at 8 points of the IDDQ test pattern, the overall toggle rate is 89.06%, and the waiting time until the IDDQ value stabilizes is 50 ms. The operating frequency was 1/1, 1/2, or 1/4 of 26 MHz, and a new IDDQ value was obtained according to the first embodiment of the present invention. As shown in FIG. 3, the conventional IDDQ value and the new IDDQ value are in good agreement. When the conventional IDDQ is about 10 μA, the new IDDQ value (IDDX in the figure) is as large as about 40 μA to 50 μA and is biased. However, when the conventional IDDQ value is 1000 μA or more, it is exactly one. I'm doing it.

  According to the above configuration, the power supply current measurement can be performed after a short waiting time without waiting for the time until the end of the power supply current change period in the conventional IDDQ measurement method, or the conventional IDDQ measurement method. Compared to the measured value of 100 μA or less, the new IDDQ measurement method has an effect that the measurement can be completed in a short time because the current value is 1 mA or more and large.

  The new IDDQ value 26 is obtained by plotting based on the measurement result, but can be obtained by approximate calculation from the measurement value. The operating frequency is set here as f, f / L, f / M, f / N, and f / O (L, M, N, and O are integers), but other settings are possible.

(Embodiment 2)
FIG. 4 is a flowchart showing a detection procedure of the failure detection method according to the second embodiment of this invention. In FIG. 4, the same components as those in FIG.

  In FIG. 4, reference numeral 50 denotes IDDQ determination, which determines whether or not there is a failure in the semiconductor integrated circuit depending on whether it is larger or smaller than the reference current value of the new IDDQ value obtained in the first embodiment of the present invention. The reference current value used for the determination of the IDDQ value is a value obtained by simulation at the design stage of the semiconductor integrated circuit or an actual semiconductor integrated circuit, and a new IDDQ according to the first embodiment of the present invention is used. It is possible to use a value distribution in which values are obtained from a plurality of semiconductor integrated circuits and to exclude values that are out of the distribution.

  Reference numeral 51 denotes a defect process, which performs a defect process when it is determined that there is a failure in the IDDQ determination 50, and 52 is a non-defective process, which performs a non-defective process when the IDDQ determination 50 determines that there is no failure.

  FIG. 5 is a comparison of a failure determination result of a conventional IDDQ value and a failure determination result of a new IDDQ value in failure determination comparison, and shows a result of applying the second embodiment of the present invention. In FIG. 5, when the conventional IDDQ value is determined to be 150 μA or more as a failure, and a new IDDQ value (IDDX for distinction in the figure) is determined to be a value of 150 μA or more as a failure (FIG. 5B). In the conventional IDDQ value determination, 16 μA or more is determined to be defective, and a new IDDQ value (IDDX in the figure is IDDX) indicates that a value of 75 μA or more is determined to be defective (FIG. 5A). ing. The semiconductor integrated circuit to which the invention is applied is the same as the semiconductor integrated circuit shown in FIG. 3 shown in the first embodiment of the present invention.

  As shown in the failure determination comparison of FIG. 5, even when the failure determination current value is small, 80% or more, and when the failure determination current value increases, almost 100% can be determined as a failure with a new IDDQ value.

  According to the above configuration, it is possible to determine the failure of the semiconductor integrated circuit based on the new IDDQ value obtained in the first embodiment of the present invention.

  The semiconductor device failure detection method using IDDQ measurement according to the present invention and the device thereof are provided with a large-scale, high-integration, multi-functional It can be used even if it has multiple functions.

The flowchart which shows the procedure of the new IDDQ measurement of the failure detection method of the semiconductor integrated circuit in Embodiment 1 of this invention Characteristic diagram of approximation line creation and approximation function fitting of the present invention The characteristic figure which showed the relationship between the IDDQ measured value of this invention, and the conventional IDDQ measured value The flowchart which shows the detection procedure of the failure detection method of the 2nd Embodiment of this invention The characteristic figure which compared the failure determination result of IDDQ measurement value of this invention and the conventional IDDQ measurement value Flow chart showing IDDQ measurement procedure of conventional failure detection method

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor integrated circuit operation condition setting 11 Semiconductor integrated circuit operation start 12 Measurement waiting time 13 Power supply current measurement 14 Semiconductor integrated circuit operation stop 15 Frequency change judgment 16 Frequency change setting 17 Approximation line creation, approximation function fitting 25 Approximation line 26 New IDDQ Value 50 IDDQ judgment 51 Defect processing 52 Good product processing

Claims (2)

In power supply current measurement of a semiconductor device, the power supply voltage is the same, and the operating frequency F is f, f / L, f / M, f / N,... (F is the operating frequency, L, M, and N are integers) At the same time, the frequency of the input signal to the semiconductor device is set to fin, fin / L, fin / M, fin / N,... (Fin is the operating frequency), and the operation starts in the measurement of the power supply current under each frequency. The measurement waiting time is measured at a constant, and an approximate line as a function of frequency is drawn using the measured power supply current of each frequency, and the power supply current of frequency 0 is extrapolated from the approximate line to obtain a static power supply current value (IDDQ And determining whether the semiconductor device is good or bad based on the static power supply current value. In the measurement of the power supply current of the semiconductor device, the power supply voltage is the same and the operating frequency F is f, f / L, f / M, f / N,..., And the semiconductor in synchronism with the operating frequency of the semiconductor device. The frequency of the input signal to the device is also set to fin, fin / L, fin / M, fin / N, etc., and the measurement waiting time from the start of operation is constant in the power supply current measurement under each frequency. Means for measuring, means for obtaining an approximate line as a function of frequency using the power supply current of each frequency measured, means for extrapolating a power supply current of frequency 0 from the approximate line to obtain a static power supply current value, A failure detection apparatus for a semiconductor device, comprising: means for determining whether the semiconductor device is good or bad based on a quiescent power supply current value.

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