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JP3788591B2 - Inverter device failure diagnosis method - Google Patents
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JP3788591B2 - Inverter device failure diagnosis method - Google Patents

Inverter device failure diagnosis method Download PDF

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JP3788591B2
JP3788591B2 JP2001307433A JP2001307433A JP3788591B2 JP 3788591 B2 JP3788591 B2 JP 3788591B2 JP 2001307433 A JP2001307433 A JP 2001307433A JP 2001307433 A JP2001307433 A JP 2001307433A JP 3788591 B2 JP3788591 B2 JP 3788591B2
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Prior art keywords
semiconductor switching
circuit
failure diagnosis
drive signal
inverter device
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JP2001307433A
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JP2003111432A (en
Inventor
吉弘 松本
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Fuji Electric FA Components and Systems Co Ltd
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Fuji Electric FA Components and Systems Co Ltd
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Description

【0001】
【発明の属する技術分野】
この発明は、インバータ主回路を構成する複数個の半導体スイッチング素子それぞれをオン,オフさせることにより所望の周波数,電圧の交流電力を負荷に供給するインバータ装置の故障診断方法に関する。
【0002】
【従来の技術】
この種の従来のインバータ装置においては、特にインバータ主回路を構成する複数個の半導体スイッチング素子が正常か否かを判定するための診断機能を該インバータ装置内部に備えているものが見当たらず、従って、前記半導体スイッチング素子が正常か否かはサービスマンによるチェックが一般的であった。
【0003】
【発明が解決しようとする課題】
従来のインバータ装置に故障が発生した場合で、インバータ主回路を構成する複数個の半導体スイッチング素子それぞれが正常か否かを判定する必要が生じたときには、このインバータ装置の該当する構成部品を予め分解してチェックを行うことが一般的であり、この分解作業は熟練した技術を要し、故障部品の解明に時間を要するという難点があった。
【0004】
この発明の目的は、上記難点を解消するインバータ装置の故障診断方法を提供することにある。
【0005】
【課題を解決するための手段】
この第1の発明は、インバータ主回路を構成する複数個の半導体スイッチング素子それぞれをオン,オフさせることにより所望の周波数,電圧の交流電力を負荷に供給するインバータ装置の故障診断方法において、
前記半導体スイッチング素子をオン,オフさせるためのゲート駆動回路および前記半導体スイッチング素子のオン,オフ状態を検出する状態検出回路を前記複数個の半導体スイッチング素子それぞれに設け、
前記半導体スイッチング素子それぞれへの故障診断用の駆動信号を生成し、この駆動信号に対応する前記半導体スイッチング素子のオン,オフ状態を検出し、この検出したオン,オフ状態と前記故障診断用の駆動信号との比較演算を行うことを特徴とする。
【0006】
また第2の発明は、ンバータ主回路を構成する複数個の半導体スイッチング素子それぞれをオン,オフさせることにより所望の周波数,電圧の交流電力を負荷に供給しつつ、前記半導体スイッチング素子への駆動信号それぞれに対応する前記半導体スイッチング素子それぞれのオン,オフ状態に基づいて前記駆動信号それぞれの波形を補正する動作も行うインバータ装置の故障診断方法において、
前記半導体スイッチング素子をオン,オフさせるためのゲート駆動回路および前記半導体スイッチング素子のオン,オフ状態を検出する状態検出回路を前記複数個の半導体スイッチング素子それぞれに設け、
前記半導体スイッチング素子それぞれへの故障診断用の駆動信号を生成し、この駆動信号に対応する前記半導体スイッチング素子のオン,オフ状態を検出し、この検出したオン,オフ状態と前記故障診断用の駆動信号との比較演算を行うことを特徴とする。
【0007】
この発明によれば、インバータ主回路を構成する複数個の半導体スイッチング素子それぞれが正常か否かを判定する機能をインバータ装置に内蔵させたので、この機能を動作させることにより、故障した半導体スイッチング素子を特定する際の分解作業が不要になる。
【0008】
【発明の実施の形態】
図1は、この発明の第1の実施の形態を示すインバータ装置の回路構成図であり、なお、図1では、以下の説明を簡単にするために、この発明に関係する一部の構成要素を図示しており、他の構成要素の図示は省略をしている。
【0009】
すなわち図1において、このインバータ装置には、一例として、IGBT1〜IGBT6それぞれを半導体スイッチング素子とした3相ブリッジ接続のインバータ主回路1と、マイクロプロセッサなどから構成され、このインバータ装置の制御,保護,監視動作を司るCPU回路11と、CPU回路11からの駆動信号に基づきIGBT2をオン,オフさせるためのゲート駆動回路12と、IGBT2のオン,オフ状態を検出する状態検出回路13とを備えている。
【0010】
この状態検出回路13はIGBT2のコレクタ電位をCPU回路11の論理レベルに変換するためのレベルシフト回路などで構成され、例えば、IGBT2がオン状態にあるときには状態検出回路13は論理「H」レベルを出力し、また、IGBT2がオフ状態にあるときには状態検出回路13は論理「L」レベルを出力するものとする。同様に、CPU回路11からIGBT2への駆動信号が論理「H」レベルのときIGBT2がオン状態になり、また、CPU回路11からIGBT2への駆動信号が論理「L」レベルのときIGBT2がオフ状態になるものとする。
【0011】
なお、図1ではIGBT2のみにゲート駆動回路12および状態検出回路13を設け、上記ではIGBT2のみについて説明をしているが、残りのIGBT1,IGBT3〜IGBT6についてもゲート駆動回路12および状態検出回路13と同等回路をそれぞれ備えており、IGBT2と同様の動作が行われる。
【0012】
従って、図1に示したインバータ装置に何らかの故障が発生し、インバータ主回路1を構成する各IGBT1〜IGBT6が正常か否かを判定する必要が生じたときには、図示しないタッチパネルなどを操作して故障診断機能を動作させることにより、CPU回路11からIGBT1〜IGBT6それぞれへの故障診断用の駆動信号を出力し、このときIGBT2ではこの駆動信号に対応して状態検出回路13が出力する論理レベルと前記駆動信号の論理レベルとの比較演算をCPU回路11が行い、この故障診断の結果を前記タッチパネルの表示器に表示させる。ここで、通常の運転時では駆動信号のパルスの繰り返し速度が早いため、両論理レベルの比較演算は困難であるから、前記故障診断用の駆動信号は、例えば、通常の運転時の駆動信号のパルス幅よりも広いパルス幅とすると共に、全てのIGBTについて、順次故障診断用の駆動信号を与えて両論理レベルの比較演算を行うものとする。すなわち、インバータ主回路1を構成する全てIGBTについて、順次、上述の動作をCPU回路11が行うようにしておけば、例えば、IGBT1〜IGBT6それぞれの接続を取り除くことなくチェックすることができる。
【0013】
図2は、この発明の第2の実施の形態を示すインバータ装置の回路構成図であり、なお、図2では、以下の説明を簡単にするために、この発明に関係する一部の構成要素を図示しており、他の構成要素の図示は省略をしている。
【0014】
すなわち図2において、このインバータ装置には図1に示した構成要素と同一機能のイバータ主回路1,ゲート駆動回路12,状態検出回路13の他に、マイクロプロセッサなどから構成され、このインバータ装置の制御,保護,監視動作を司るCPU回路21と、該インバータ装置の制御性能を高めるためにCPU回路21からのIGBT2への駆動信号と状態検出回路13からの検出信号とのパルス幅がほぼ等しくなるように補正した新たな駆動信号を生成し、この新たな駆動信号をゲート駆動回路12へ出力するパルス幅補正回路22とを備えている。
【0015】
また、図2に示したCPU回路21からパルス幅補正回路22への駆動信号が論理「H」レベルのときIGBT2がオン状態になり、また、CPU回路21からパルス幅補正回路22への駆動信号が論理「L」レベルのときIGBT2がオフ状態になるものとする。
【0016】
なお、図2ではIGBT2のみにパルス幅補正回路22とゲート駆動回路12と状態検出回路13とを設け、上記ではIGBT2のみについて説明をしているが、残りのIGBT1,IGBT3〜IGBT6についてもパルス幅補正回路22,ゲート駆動回路12,状態検出回路13それぞれと同等回路をそれぞれ備えており、IGBT2と同様の動作が行われる。
【0017】
従って、図2に示したインバータ装置に何らかの故障が発生し、インバータ主回路1を構成する各IGBT1〜IGBT6が正常か否かを判定する必要が生じたときには、図示しないタッチパネルなどを操作して故障診断機能を動作させることにより、CPU回路21から各IGBT1〜IGBT6への故障診断用の駆動信号を出力し、このときIGBT2ではこの駆動信号に対応して状態検出回路13が出力する論理レベルと前記駆動信号の論理レベルとの比較演算をCPU回路21が行い、この故障診断の結果を前記タッチパネルの表示器に表示させる。ここで、通常の運転時では駆動信号のパルスの繰り返し速度が早いため、両論理レベルの比較演算は困難であるから、前記故障診断用の駆動信号は、例えば、通常の運転時の駆動信号のパルス幅よりも広いパルス幅とすると共に、全てのIGBTについて、順次故障診断用の駆動信号を与えて両論理レベルの比較演算を行うものとする。すなわち、インバータ主回路1を構成する全てIGBTについて、順次、上述の動作をCPU回路21が行うようにしておけば、例えば、IGBT1〜IGBT6それぞれの接続を取り除くことなくチェックすることができ、また、このインバータ装置の場合には新たなハード部品の追加設置は不要である。
【0018】
なお、上述の第1,第2の実施の形態回路での説明ではインバータ装置に故障が発生したときについて述べたが、このインバータ装置に運転指令が与えられた時毎に通常の起動に先立って、故障診断用の駆動信号を出力するこの発明の診断方法を行わせ、その結果、インバータ装置の故障が発見されれば、その故障を表示することもできる。
【0019】
【発明の効果】
この発明によれば、インバータ装置に故障が発生し、インバータ主回路を構成する複数個の半導体スイッチング素子それぞれが正常か否かを判定する必要が生じたときには、前記半導体スイッチング素子それぞれへの故障診断用の駆動信号を生成し、この駆動信号に基づいて前記半導体スイッチング素子のチェックを自動的に行うことが可能になる。
【図面の簡単な説明】
【図1】この発明の第1の実施の形態を示すインバータ装置の回路構成図
【図2】この発明の第2の実施の形態を示すインバータ装置の回路構成図
【符号の説明】
1…インバータ主回路、11…CPU回路、12…ゲート駆動回路、13…状態検出回路、21…CPU回路、22…パルス幅補正回路。
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a failure diagnosis method for an inverter device that supplies alternating current power having a desired frequency and voltage to a load by turning on and off each of a plurality of semiconductor switching elements constituting an inverter main circuit.
[0002]
[Prior art]
In this type of conventional inverter device, in particular, there is no one having a diagnostic function for determining whether or not a plurality of semiconductor switching elements constituting the inverter main circuit are normal, and therefore In general, a serviceman checks whether or not the semiconductor switching element is normal.
[0003]
[Problems to be solved by the invention]
When a failure occurs in a conventional inverter device, when it becomes necessary to determine whether or not each of the plurality of semiconductor switching elements constituting the inverter main circuit is normal, the corresponding components of the inverter device are disassembled in advance. In general, this disassembling work requires a skillful technique and takes time to elucidate a failed part.
[0004]
An object of the present invention is to provide a fault diagnosis method for an inverter device that eliminates the above-mentioned difficulties.
[0005]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a failure diagnosis method for an inverter device for supplying AC power having a desired frequency and voltage to a load by turning on and off each of a plurality of semiconductor switching elements constituting the inverter main circuit.
A gate driving circuit for turning on and off the semiconductor switching element and a state detection circuit for detecting an on / off state of the semiconductor switching element are provided in each of the plurality of semiconductor switching elements,
A drive signal for failure diagnosis to each of the semiconductor switching elements is generated, an on / off state of the semiconductor switching element corresponding to the drive signal is detected, and the detected on / off state and the drive for failure diagnosis are detected. A comparison operation with a signal is performed.
[0006]
According to a second aspect of the present invention, a plurality of semiconductor switching elements constituting the inverter main circuit are turned on and off to supply alternating current power having a desired frequency and voltage to the load, while driving signals to the semiconductor switching elements are supplied. In the failure diagnosis method for an inverter device that also performs an operation of correcting the waveform of each of the drive signals based on the on / off states of the semiconductor switching elements corresponding to the respective semiconductor switching elements,
A gate driving circuit for turning on and off the semiconductor switching element and a state detection circuit for detecting an on / off state of the semiconductor switching element are provided in each of the plurality of semiconductor switching elements,
A drive signal for failure diagnosis to each of the semiconductor switching elements is generated, an on / off state of the semiconductor switching element corresponding to the drive signal is detected, and the detected on / off state and the drive for failure diagnosis are detected. A comparison operation with a signal is performed.
[0007]
According to the present invention, since the inverter device has a function of determining whether or not each of the plurality of semiconductor switching elements constituting the inverter main circuit is normal, the malfunctioning semiconductor switching element is activated by operating this function. The disassembling work when specifying the is no longer necessary.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit configuration diagram of an inverter device showing a first embodiment of the present invention. In FIG. 1, in order to simplify the following description, some components related to the present invention are shown. The other components are not shown.
[0009]
That is, in FIG. 1, this inverter device includes, as an example, a three-phase bridge-connected inverter main circuit 1 in which each of IGBT1 to IGBT6 is a semiconductor switching element, a microprocessor, and the like. A CPU circuit 11 that controls the monitoring operation, a gate drive circuit 12 for turning on and off the IGBT 2 based on a drive signal from the CPU circuit 11, and a state detection circuit 13 for detecting the on / off state of the IGBT 2 are provided. .
[0010]
This state detection circuit 13 is composed of a level shift circuit for converting the collector potential of the IGBT 2 to the logic level of the CPU circuit 11. For example, when the IGBT 2 is in the ON state, the state detection circuit 13 has a logic “H” level. In addition, when the IGBT 2 is in the OFF state, the state detection circuit 13 outputs a logic “L” level. Similarly, when the drive signal from the CPU circuit 11 to the IGBT 2 is at a logic “H” level, the IGBT 2 is turned on, and when the drive signal from the CPU circuit 11 to the IGBT 2 is at a logic “L” level, the IGBT 2 is turned off. Shall be.
[0011]
In FIG. 1, only the IGBT 2 is provided with the gate drive circuit 12 and the state detection circuit 13, and only the IGBT 2 is described above. However, the gate drive circuit 12 and the state detection circuit 13 are also provided for the remaining IGBTs 1, IGBT3 to IGBT6. And an equivalent circuit, and the same operation as that of the IGBT 2 is performed.
[0012]
Accordingly, when some failure occurs in the inverter device shown in FIG. 1 and it is necessary to determine whether each of the IGBTs 1 to 6 constituting the inverter main circuit 1 is normal, the failure is caused by operating a touch panel (not shown). By operating the diagnosis function, a drive signal for failure diagnosis is output from the CPU circuit 11 to each of the IGBT1 to IGBT6. At this time, the IGBT2 outputs the logic level output by the state detection circuit 13 corresponding to this drive signal and the above-described logic level. The CPU circuit 11 performs a comparison operation with the logic level of the drive signal, and displays the result of the failure diagnosis on the display of the touch panel. Here, since the repetition rate of the pulse of the drive signal is high during normal operation, it is difficult to compare the two logic levels. Therefore, the drive signal for failure diagnosis is, for example, the drive signal during normal operation. It is assumed that the pulse width is wider than the pulse width, and that for all the IGBTs, a drive signal for failure diagnosis is sequentially given to perform a comparison operation of both logic levels. That is, if all the IGBTs constituting the inverter main circuit 1 are sequentially operated by the CPU circuit 11, for example, the check can be made without removing the connections of the IGBTs 1 to 6.
[0013]
FIG. 2 is a circuit configuration diagram of an inverter device showing a second embodiment of the present invention. In FIG. 2, in order to simplify the following description, some components related to the present invention are shown. The other components are not shown.
[0014]
That is, in FIG. 2, this inverter device is composed of a microprocessor and the like in addition to the inverter function circuit 1, the gate drive circuit 12, and the state detection circuit 13 having the same functions as the components shown in FIG. The pulse widths of the drive signal from the CPU circuit 21 to the IGBT 2 and the detection signal from the state detection circuit 13 are substantially equal to improve the control performance of the CPU circuit 21 that controls, protects, and monitors, and the inverter device. A pulse width correction circuit 22 that generates a new drive signal corrected in this way and outputs the new drive signal to the gate drive circuit 12 is provided.
[0015]
Further, when the drive signal from the CPU circuit 21 to the pulse width correction circuit 22 shown in FIG. 2 is at the logic “H” level, the IGBT 2 is turned on, and the drive signal from the CPU circuit 21 to the pulse width correction circuit 22 is turned on. Assume that IGBT2 is turned off when is at a logic "L" level.
[0016]
In FIG. 2, only the IGBT 2 is provided with the pulse width correction circuit 22, the gate drive circuit 12, and the state detection circuit 13. In the above description, only the IGBT 2 is described. However, the remaining IGBTs 1, IGBT 3 to IGBT 6 also have a pulse width. The correction circuit 22, the gate drive circuit 12, and the state detection circuit 13 are each provided with an equivalent circuit, and the same operation as the IGBT 2 is performed.
[0017]
Accordingly, when some failure occurs in the inverter device shown in FIG. 2 and it is necessary to determine whether or not each of the IGBTs 1 to 6 constituting the inverter main circuit 1 is normal, the failure is caused by operating a touch panel (not shown). By operating the diagnostic function, a drive signal for failure diagnosis is output from the CPU circuit 21 to each of the IGBT1 to IGBT6. At this time, in the IGBT2, the logic level output by the state detection circuit 13 corresponding to this drive signal and the above-mentioned The CPU circuit 21 performs a comparison operation with the logic level of the drive signal, and displays the result of the failure diagnosis on the display of the touch panel. Here, since the repetition rate of the pulse of the drive signal is high during normal operation, it is difficult to compare the two logic levels. Therefore, the drive signal for failure diagnosis is, for example, the drive signal during normal operation. It is assumed that the pulse width is wider than the pulse width, and that for all the IGBTs, a drive signal for failure diagnosis is sequentially given to perform a comparison operation of both logic levels. That is, for all IGBTs constituting the inverter main circuit 1, if the CPU circuit 21 sequentially performs the above-described operation, for example, it is possible to check without removing the connections of the IGBT1 to IGBT6, In the case of this inverter device, it is not necessary to install new hardware components.
[0018]
In the above description of the circuits of the first and second embodiments, the case where a failure has occurred in the inverter device has been described. However, every time an operation command is given to this inverter device, prior to normal startup. The diagnosis method of the present invention that outputs a drive signal for failure diagnosis is performed. As a result, if a failure of the inverter device is found, the failure can be displayed.
[0019]
【The invention's effect】
According to the present invention, when a failure occurs in the inverter device and it is necessary to determine whether or not each of the plurality of semiconductor switching elements constituting the inverter main circuit is normal, failure diagnosis for each of the semiconductor switching elements is performed. For example, the semiconductor switching element can be automatically checked based on the drive signal.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram of an inverter device showing a first embodiment of the invention. FIG. 2 is a circuit configuration diagram of an inverter device showing a second embodiment of the invention.
DESCRIPTION OF SYMBOLS 1 ... Inverter main circuit, 11 ... CPU circuit, 12 ... Gate drive circuit, 13 ... State detection circuit, 21 ... CPU circuit, 22 ... Pulse width correction circuit

Claims (2)

インバータ主回路を構成する複数個の半導体スイッチング素子それぞれをオン,オフさせることにより所望の周波数,電圧の交流電力を負荷に供給するインバータ装置の故障診断方法において、
前記半導体スイッチング素子をオン,オフさせるためのゲート駆動回路および前記半導体スイッチング素子のオン,オフ状態を検出する状態検出回路を前記複数個の半導体スイッチング素子それぞれに設け、
前記半導体スイッチング素子それぞれへの故障診断用の駆動信号を生成し、この駆動信号に対応する前記半導体スイッチング素子のオン,オフ状態を検出し、この検出したオン,オフ状態と前記故障診断用の駆動信号との比較演算を行うことを特徴とするインバータ装置の故障診断方法。
In a failure diagnosis method for an inverter device that supplies AC power of a desired frequency and voltage to a load by turning on and off each of a plurality of semiconductor switching elements constituting the inverter main circuit,
A gate driving circuit for turning on and off the semiconductor switching element and a state detection circuit for detecting an on / off state of the semiconductor switching element are provided in each of the plurality of semiconductor switching elements,
A drive signal for failure diagnosis to each of the semiconductor switching elements is generated, an on / off state of the semiconductor switching element corresponding to the drive signal is detected, and the detected on / off state and the drive for failure diagnosis are detected. A method for diagnosing a fault in an inverter device, comprising performing a comparison operation with a signal.
インバータ主回路を構成する複数個の半導体スイッチング素子それぞれをオン,オフさせることにより所望の周波数,電圧の交流電力を負荷に供給しつつ、前記半導体スイッチング素子への駆動信号それぞれに対応する前記半導体スイッチング素子それぞれのオン,オフ状態に基づいて前記駆動信号それぞれの波形を補正する動作も行うインバータ装置の故障診断方法において、
前記半導体スイッチング素子をオン,オフさせるためのゲート駆動回路および前記半導体スイッチング素子のオン,オフ状態を検出する状態検出回路を前記複数個の半導体スイッチング素子それぞれに設け、
前記半導体スイッチング素子それぞれへの故障診断用の駆動信号を生成し、この駆動信号に対応する前記半導体スイッチング素子のオン,オフ状態を検出し、この検出したオン,オフ状態と前記故障診断用の駆動信号との比較演算を行うことを特徴とするインバータ装置の故障診断方法。
The semiconductor switching corresponding to each drive signal to the semiconductor switching element while supplying AC power of a desired frequency and voltage to the load by turning on and off each of the plurality of semiconductor switching elements constituting the inverter main circuit In the failure diagnosis method for an inverter device that also performs an operation of correcting the waveform of each of the drive signals based on the on / off state of each element,
A gate driving circuit for turning on and off the semiconductor switching element and a state detection circuit for detecting an on / off state of the semiconductor switching element are provided in each of the plurality of semiconductor switching elements,
A drive signal for failure diagnosis to each of the semiconductor switching elements is generated, an on / off state of the semiconductor switching element corresponding to the drive signal is detected, and the detected on / off state and the drive for failure diagnosis are detected. A method for diagnosing a fault in an inverter device, comprising performing a comparison operation with a signal.
JP2001307433A 2001-10-03 2001-10-03 Inverter device failure diagnosis method Expired - Fee Related JP3788591B2 (en)

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