JP3792026B2 - Semiconductor device and inspection method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and an inspection method thereof.
[0002]
[Prior art]
In recent years, electronic devices equipped with semiconductor integrated circuit devices (hereinafter referred to as “semiconductor devices”) have made remarkable progress in miniaturization and cost reduction. The demand is getting stronger.
[0003]
Normally, after a semiconductor chip and a lead frame are electrically connected by a bonding wire, the semiconductor device is supplied in a state where the semiconductor chip and the lead frame are sealed with resin or ceramics and mounted on a printed board. However, due to the demand for miniaturization of electronic equipment, a method for directly mounting a semiconductor device on a circuit board in a state where the semiconductor device is cut out from the semiconductor wafer (hereinafter, the semiconductor device in this state is referred to as a bare chip) has been developed. It is desired to supply a guaranteed bare chip at a low price.
[0004]
In order to perform quality assurance on a bare chip, it is necessary to inspect a semiconductor device such as burn-in in a wafer state. However, since it takes a lot of time to inspect a plurality of bare chips formed on a semiconductor wafer one by one or several times, it is realistic in terms of time and cost. is not. Therefore, it is required to perform an inspection such as burn-in on all bare chips in a wafer.
[0005]
In order to perform a batch inspection on a bare chip in a wafer state, it is necessary to simultaneously apply a power supply voltage or a signal to electrodes of a plurality of semiconductor chips formed on a semiconductor wafer to operate the plurality of semiconductor chips. . For this purpose, it is necessary to prepare a probe card having a very large number (usually several thousand or more) of probe needles. However, in order to do this, the conventional needle type probe card has a number of pins. However, it cannot respond from the point of price.
[0006]
In view of this, a probe card has been proposed that can collectively contact probe electrodes with a large number of pad electrodes on a wafer (Japanese Patent Laid-Open No. 7-231019). According to this technique, a large number of bumps are formed on the probe card, and these bumps are used as probe electrodes.
[0007]
[Problems to be solved by the invention]
When performing a burn-in inspection using a wafer batch type probe card, a large number of chips included in each wafer are operated simultaneously. If a large number of chips are started simultaneously, a large amount of current needs to be instantaneously supplied to the wafer at the beginning of the chip operation. In the calculation, if such a large amount of current is supplied to the wafer, the wiring on the probe card cannot be tolerated and there is a risk of disconnection.
[0008]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device that can disperse the peak of current flowing through each chip when a plurality of selected chips start operation. It is to provide an inspection method.
[0009]
[Means for Solving the Problems]
The semiconductor device of the present invention includes an internal circuit and a burn-in timer circuit that generates a burn-in internal clock signal necessary for the operation of the internal circuit in the burn-in mode, and outputs from the burn-in timer circuit in the burn-in mode. The operation of the internal circuit is controlled in synchronization with the burn-in internal clock. In the specification of the present application, the automatic determination of the burn-in cycle using an internal timer and the execution of the burn-in operation at that cycle are referred to as “self burn-in”.
[0010]
Another semiconductor device according to the present invention is necessary for the operation of the internal circuit when the internal circuit, the terminal for receiving the self burn-in signal, and the self-burn-in signal input to the terminal are in the self-burn-in mode. A burn-in timer circuit for generating an internal clock signal, a circuit for controlling the operation of the internal circuit in synchronization with the internal clock output from the burn-in timer circuit, and the self-burn-in signal input to the terminal Includes a control signal input circuit for externally supplying a signal necessary for the operation of the internal circuit to the internal circuit when instructing that it is not in the self-burn-in mode.
[0011]
Still another semiconductor device of the present invention is a semiconductor device comprising a memory cell array and an address decoder for selecting a memory cell from the memory cell array, further comprising a terminal for receiving a self burn-in signal, and a terminal electrode. When instructing that the input self-burn-in signal is in the self-burn-in mode, a burn-in timer circuit for generating an internal clock signal and an address are generated in synchronization with the internal clock output from the burn-in timer circuit And an address counter for giving the address to the address decoder, and an address for giving an address inputted from the outside to the address decoder when the self-burn-in signal inputted to the terminal indicates that the self-burn-in mode is not in the self-burn-in mode. With input circuit .
[0012]
The burn-in timer circuit preferably has a ring oscillator circuit.
[0013]
According to another aspect of the present invention, there is provided a method for measuring a semiconductor device, wherein the burn-in process is performed using the burn-in timer circuit.
[0014]
According to another semiconductor device measurement method of the present invention, the semiconductor device measurement method according to claim 2, wherein a signal instructing that the device is in the self-burn-in mode is input to the terminal, and the burn-in timer circuit is provided. A step of generating the internal clock signal and a step of performing burn-in while operating the internal circuit in synchronization with the internal clock.
[0015]
Still another semiconductor device measurement method according to the present invention is the semiconductor device measurement method according to claim 3, wherein a signal instructing that the device is in the self-burn-in mode is input to the terminal, and the burn-in timer circuit is provided. Generating the internal clock signal, generating the address in synchronization with the internal clock by the address counter, and performing burn-in while giving the address to the address decoder.
[0016]
According to another aspect of the present invention, there is provided a semiconductor device inspection method for performing a burn-in inspection on a wafer including a plurality of semiconductor devices each having a burn-in timer circuit using a wafer collective inspection / measurement probe card. In the inspection method, the step of operating the burn-in timer circuit included in each semiconductor device in the wafer, and operating each semiconductor device according to the internal clock signal output from the burn-in timer circuit, And burn-in of each semiconductor device.
[0017]
According to still another aspect of the present invention, there is provided a semiconductor device inspection method for performing a burn-in inspection on a wafer including a plurality of semiconductor devices using a wafer collective inspection / measurement probe card. A plurality of burn-in timer circuits are formed therein, and the plurality of semiconductor devices according to any of a step of operating the burn-in timer circuit and an internal clock signal output from the plurality of burn-in timer circuits A step of performing burn-in of each semiconductor device while operating each of the semiconductor devices.
The probe card may be a probe card for wafer batch type measurement inspection comprising a plurality of probe electrodes arranged two-dimensionally and a multilayer wiring board electrically connected to the plurality of probe electrodes. preferable.
[0018]
The probe electrode is preferably a bump electrode.
[0019]
It is preferable that a conductive rubber for electrically connecting the probe electrode to the multilayer wiring board is provided between the probe electrode and the multilayer wiring board.
[0020]
The probe electrode is preferably formed on a thin film stretched in a state where a tension is applied to the rigid ring.
[0021]
The probe electrode may be formed from at least part of the wiring of the multilayer wiring board.
[0022]
Still another semiconductor device measurement method according to the present invention is a semiconductor device inspection method using a wafer batch type probe card, in which a power supply voltage is supplied to each chip included in a wafer to be measured. The first level voltage is supplied for a certain period immediately after the start of the burn-in test, and then the second level voltage higher than the first level is supplied.
[0023]
The probe card may be a probe card for wafer batch type measurement inspection comprising a plurality of probe electrodes arranged two-dimensionally and a multilayer wiring board electrically connected to the plurality of probe electrodes. preferable.
[0024]
The probe electrode is preferably a bump electrode.
[0025]
It is preferable that a conductive rubber for electrically connecting the probe electrode to the multilayer wiring board is provided between the probe electrode and the multilayer wiring board.
[0026]
The probe electrode is preferably formed on a thin film stretched in a state where a tension is applied to the rigid ring.
[0027]
The probe electrode may be formed from at least part of the wiring of the multilayer wiring board.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
First, in order to facilitate understanding of the present invention, a wafer batch type measurement / inspection technique to which the present invention is applied will be described.
[0029]
FIG. 1 shows a probe card 1 that can collectively contact probe electrodes with a large number of pad electrodes on a wafer. A wafer (for example, a silicon wafer having a diameter of 200 mm) 2 on which elements and circuits to be measured and inspected are formed is placed on the wafer tray 3 as it is without being divided into chips. During measurement / inspection, the wafer 2 is sandwiched between the probe card 1 and the wafer tray 3. A small space formed between the probe card 1 and the wafer tray 3 is sealed from the atmosphere by the seal ring 4. By depressurizing the space through the vacuum valve 5 (for example, reducing the pressure by about 200 millitorr compared to the atmospheric pressure), the probe card 1 presses the wafer 2 evenly by applying the force of the atmospheric pressure. As a result, the probe electrode of the probe card 1 can press the pad electrode on the wafer 2 with a uniform force over the entire surface of the wide wafer 2. In order to make sure that a large number of probe electrodes on the probe card 1 are in contact with a predetermined pad electrode on the wafer 2, it is necessary to perform alignment between the probe card 1 and the wafer 2 with high accuracy before the contact. There is.
[0030]
According to such a wafer batch type measurement / inspection technique, a large number of probe electrodes formed on the probe card 1 are applied to a large number of pad electrodes of thousands to tens of thousands or more formed on the entire surface of the wafer 2. At the same time, the contact can be surely made.
[0031]
FIG. 2 shows a cross-sectional configuration example of the probe card 20 used in the present invention.
[0032]
This probe card 20 includes a multilayer wiring board 21 to be electrically connected to a measurement / inspection apparatus, a polyimide thin film 22 with bumps, and a localized anisotropic conductive rubber 23 provided therebetween. At least. The localized anisotropic conductive rubber 23 is an elastic member that electrically connects the electrode wiring 21b of the multilayer wiring board 21 and the bump 22b of the polyimide thin film 22 with bumps. FIG. 2 shows a state in which the three members 21 to 23 are separated in the vertical direction, but a single probe card 20 is formed by tightly fixing these members 21 to 23.
[0033]
As the multilayer wiring substrate 21, a substrate in which a multilayer wiring 21b is formed on a glass substrate 21a can be used. As the glass substrate 21a, one having high flatness over a wide area is preferable because it can be relatively easily manufactured. In addition, since the thermal expansion coefficient of glass is close to that of a silicon wafer, glass is particularly suitable as a material for a multilayer wiring board of a burn-in probe card.
[0034]
The multilayer wiring 21b can be formed using a known thin film deposition technique and patterning technique. For example, if a conductive thin film such as copper (Cu) is deposited on the glass substrate 21a by sputtering or the like and then the conductive thin film is patterned by a photolithography and etching process, a wiring 21b having an arbitrary pattern is formed. be able to. The wirings 21b at different levels are separated by the interlayer insulating film 21c. The interlayer insulating film 21c is obtained, for example, by forming a polyimide thin film on the glass substrate 21a by a method such as spin coating. The multilayer wiring 21b electrically connects a large number of bumps (probe electrodes) 22b arranged two-dimensionally in a plane to connection electrodes and connectors (not shown) provided in the peripheral region of the probe card 20, and externally. This enables the electrical connection between the inspection device or the inspection circuit and the probe electrode 22b.
[0035]
The polyimide thin film 22 with bumps is obtained, for example, as follows. First, a large number of openings (with an inner diameter of about 20 to 30 μm) are provided in a base material in which a polyimide thin film 22a having a thickness of about 18 μm and a copper thin film having a thickness of about 35 μm are formed into two layers. Each opening is filled with a metal material such as Ni using a method such as electrolytic plating to form bumps 22b. If unnecessary portions of the copper thin film are removed from the polyimide thin film 22a by etching, a polyimide thin film 22 with bumps as illustrated is obtained. As an example, the height of the bump 22b is about 20 μm. The lateral size of the bump is about 40 μm. The position on the polyimide thin film 22a where the bump 22b is formed is determined depending on the position on the measurement target wafer 25 where the pad electrode 26 is formed.
[0036]
In the localized anisotropic conductive rubber 23, conductive particles 23 b are arranged at specific positions in a silicone rubber sheet (thickness: about 200 μm) 23 a, and the conductive particles 23 b are chained in the conduction direction (thickness direction) at that position. It is connected in a shape. By interposing elastic rubber between the multilayer wiring board 21 and the bumps 22b, the bumps 22b of the probe card 20 and the wafer 25 are not affected by the steps on the wafer 25 or the warp of the wafer 25. Contact between the upper electrode 26 can be reliably realized.
[0037]
When such a probe card 20 is used for burn-in inspection, the thermal expansion coefficient of the polyimide thin film 22a (about 16 × 10 ^-6 / ° C.) and the thermal expansion coefficient of the wafer 25 (about 3 × 10 ^-6 Therefore, the position of the bump 22b on the polyimide thin film 22a is shifted laterally with respect to the position of the pad electrode 26 on the wafer 25 during heating for burn-in. This misalignment is larger at the peripheral portion than at the central portion of the wafer 25, and normal electrical contact cannot be obtained between the wafer 25 and the probe card 20. In order to solve such a problem, as disclosed in JP-A-7-231019, a polyimide thin film 22a is attached to a rigid ring (not shown) such as a ceramic ring having a thermal expansion coefficient close to that of a silicon wafer, It is effective to apply tension to the polyimide thin film 22a in advance. In this case, it is better to form the bump 22b after the polyimide thin film 22a is attached to the rigid ring. This is because the position of the bump 22b is difficult to shift.
[0038]
The wafer 25 is disposed on the wafer tray 28. After the alignment process is performed so that the wafer tray 28 on which the wafer 25 is mounted is positioned at an appropriate position with respect to the probe card 20, the distance between the probe card 20 and the wafer tray 28 is reduced. As a result, the pad electrode 26 on the wafer 25 and the bump 22b of the probe card 20 are in physical contact. As described above, by depressurizing the sealed space between the probe card 20 and the wafer tray 28, each bump 22b presses the pad electrode 26 on the wafer 25 with substantially equal force. Thereafter, an electrical signal and a power supply voltage from a drive circuit and an inspection circuit (not shown) are supplied to the pad electrode 26 on the wafer 25 through the bumps 22 of the probe card 20. In the case of the burn-in inspection, the probe card 20, the wafer 25, and the wafer tray 28 are integrally inserted into the burn-in apparatus and heated in a state as shown in FIG.
[0039]
The probe card 20, the wafer 25, and the wafer tray 28 are maintained in the state shown in FIG. 3 during and before and after the inspection / measurement. The wafer tray 28 in which the above-described sealed space is in a reduced pressure state does not separate from the probe card 20, and these members integrally hold the wafer 25.
[0040]
When the inspection and measurement of the wafer batch type is completed, the pressure in the sealed space formed between the probe card 20 and the tray 28 is increased and recovered to about atmospheric pressure. As a result, the tray 28 is separated from the probe card 20, and the wafer 25 is taken out from the inside.
[0041]
A semiconductor device and an inspection method thereof according to the present invention will be described below with reference to FIGS.
[0042]
The semiconductor device of FIG. 4 is a dynamic ram (DRAM) provided with a self-refresh timer circuit 40. The internal clock generated by the self-refresh timer circuit 40 is used to generate a self-refresh synchronization signal.
[0043]
This semiconductor device includes a burn-in timer circuit 41 in addition to the self-refresh timer circuit 40. The burn-in timer circuit 41 generates an internal clock that defines a burn-in cycle in the self-burn-in mode. This internal clock is used to operate the internal circuit of the semiconductor device in the self burn-in mode. The burn-in timer circuit 41 operates in accordance with a self-burn-in signal applied to a terminal 42 for a self-burn-in (SBI) signal. More specifically, burn-in timer circuit 41 generates an internal clock signal only when the self-burn-in signal indicates the self-burn-in mode. The internal clock generated by the burn-in timer circuit 41 is input to the synchronization signal generation circuit 43. When the self-burn-in signal indicates the self-burn-in mode, the synchronization signal generation circuit 43 gives a signal corresponding to the internal clock generated by the burn-in timer circuit 41 to the refresh address counter 46 and increments the refresh address counter 46. Let it run.
[0044]
When the self burn-in signal does not indicate the self-burn-in mode, the synchronization signal generation circuit 43 generates a synchronization signal corresponding to the RAS bar signal, CAS bar signal, and WE bar signal input from the outside. Based on this synchronization signal, address latching and the like are performed.
[0045]
When the self burn-in signal does not indicate the self burn-in mode, a normal self-refresh operation is also periodically performed. The normal self-refresh operation is executed in synchronization with the internal clock generated by the self-refresh timer circuit 40, and the refresh address counter 46 is incremented according to the internal clock.
The internal configurations of the burn-in timer circuit 41 and the synchronization signal generation circuit 43 will be described later with reference to FIG.
[0046]
The semiconductor device shown in FIG. 4 includes a row address buffer 44 that latches a row address, a column address buffer 45 that latches a column address, a row decoder 47 that decodes the row address, and a column decoder that decodes the column address, as in a normal DRAM. 48, a sense amplifier 49 and a memory cell array 50 are provided. In the present specification, these circuits are collectively referred to as “internal circuits”.
[0047]
In the normal operation mode, the internal circuit operates in synchronization with a control signal (RAS bar signal or the like) given from the outside. However, the self-refresh operation synchronized with the internal clock generated by the self-refresh timer circuit 40 is executed separately from the operation synchronized with the external control signal.
[0048]
This semiconductor device repeats the burn-in operation cycle synchronized with the internal clock generated by the internal timer circuit 41 in the self-burn-in mode (when the SBI signal is “High”). As a result, when the burn-in inspection is started collectively with a plurality of chips arranged in one wafer, the burn-in operation cycle of each chip is controlled by the timer circuit 41 built in each chip. The clock cycle of the burn-in timer circuit 41 varies within the wafer due to variations in manufacturing process parameters. For this reason, the clock cycle of the timer circuit 41 shows slightly different values even between chips contained in one wafer. Therefore, according to the present embodiment, the burn-in operation of each semiconductor device is performed at a different period for each chip even in one wafer. As a result, the current peaks flowing through the chips are dispersed, and the probe card is prevented from being damaged by a large current.
[0049]
Next, an internal configuration example of the burn-in timer circuit 41 and the synchronization signal generation circuit 43 will be described with reference to FIG.
[0050]
As shown in FIG. 5, the burn-in timer circuit 41 includes a 2n + 1 stage inverter 53 and a ring oscillator in which a delay capacitor is connected in a ring shape, and the potential of the SBI signal input to the SBI signal terminal 42. When the level is “High”, an internal clock (OSC) having a constant frequency is generated. This internal clock is input to the synchronization signal generation circuit 43 and applied to one of the input portions of the NAND circuit 54 in the synchronization signal generation circuit 43. The output of the NAND circuit 55 is supplied to the other input part of the NAND circuit 54, and a signal obtained by inverting the potential level of the SBI signal by the inverter 56 is supplied to one input part of the NAND circuit 55. As a result, in the self-burn-in mode (SBI signal is “High”), the output of the NAND circuit 55 is at the “High” level, and the output of the NAND circuit 54 is an inverted version of the internal clock. Here, the output of the NAND circuit 55 is expressed as “intRAS”.
[0051]
In the self burn-in mode (SBI signal is “High”), a signal obtained by inverting the potential level of the SBI signal by the inverter 58 is applied to one of the input portions of the NAND circuit 57. As a result, in the self-burn-in mode (SBI signal is “High”), the output of the NAND circuit 57 is at “High” level, and the output of the inverter circuit 59 that receives the output is at “Low” level. The output of the inverter circuit 59 is expressed as “intCAS”.
[0052]
As described above, in the self burn-in mode, the “intRAS” signal output from the synchronization signal generation circuit 43 is obtained by inverting the internal clock signal from the burn-in timer circuit 41, and is output from the synchronization signal generation circuit 43. The “intCAS” signal always indicates the “Low” level. FIG. 6 is a timing chart showing changes in the times of the “intRAS” signal and the “intCAS” signal.
[0053]
The “intRAS” signal is supplied to the refresh address counter 46 of FIG. The refresh address counter 46 sequentially generates row addresses while counting up in synchronization with the “intRAS” signal. The row addresses thus formed are sequentially supplied to the row decoder 47, and the corresponding memory cell rows of the memory cell array 50 are sequentially activated.
[0054]
When not in the self burn-in mode (the SBI signal is not “High”), the “intCAS” signal and the “intCAS” signal output from the synchronization signal generation circuit 43 in FIG. The levels of the RAS bar signal and CAS bar signal received by the circuit 51 and the CAS input circuit 52 are inverted. As a result, when not in the self-burn-in mode, the semiconductor device operates in synchronization with a control signal (such as a RAS bar signal) supplied from the outside as in the conventional semiconductor device. Needless to say, the self-refresh operation synchronized with the internal clock generated by the self-refresh timer circuit 40 is executed separately from the operation synchronized with the external control signal.
[0055]
Since the burn-in cycle time is typically about 1 to 3 microseconds, the clock cycle of the burn-in timer circuit 41 is determined so as to substantially coincide with this cycle time. The characteristics of the inverter and delay capacitor constituting the ring oscillator in the burn-in timer circuit 41 vary depending on the characteristics of the transistor and the variation of the oxide film capacitance. Since these variations show a value of about 2 to 5% in the wafer surface, the clock cycle of the timer circuit 41 also varies by about 2 to 5% in the wafer surface. That is, when the clock cycle of the burn-in timer circuit 41 is set to 2 microseconds, the clock cycle generated by each burn-in timer circuit 41 varies about 40 to 100 nanoseconds within the wafer surface. Due to this variation, even if the operation start point of each chip is the same, the deviation of the burn-in operation cycle is accumulated independently for each chip, and the current peak flowing through each semiconductor device is greatly dispersed. Become.
[0056]
The self-burn-in signal is applied by bringing the probe electrode (bump) of the probe card into contact with the SBI signal terminal 42, and a predetermined voltage (“High”, “Low” or “open state” via the bump of the probe card. ”) To the SBI signal terminal 42. Even during the burn-in inspection, it is possible to perform normal wafer batch burn-in without applying a self-burn-in signal to the terminal 42.
[0057]
Although the semiconductor device according to the above embodiment is a dynamic ram (DRAM), the application of the present invention is not limited to the DRAM. Further, the present invention can be applied to a semiconductor device other than the semiconductor memory device that originally includes the self-refresh timer circuit.
[0058]
In the above embodiment, the burn-in timer circuit 41 is provided for each chip, but one timer circuit 41 may be provided for a block including a plurality of chips. In that case, the timer circuit 41 may be formed in a scribe lane between chips. The positions where the timer circuits 41 are provided are preferably distributed in the central part and the peripheral part in the wafer, so that a relatively large variation in the clock cycle occurs.
[0059]
Hereinafter, another embodiment of the inspection method of a semiconductor device according to the present invention will be described with reference to FIG.
[0060]
In this embodiment, the power supply voltage applied to each chip in the wafer is lower than the power supply voltage (for example, 7 volts) in the normal burn-in mode (for example, 3 volts) until a predetermined time elapses after entering the burn-in mode. After a certain period of time has elapsed, the voltage is raised to the power supply voltage in the normal burn-in mode.
[0061]
The period during which the power supply voltage is kept low is preferably set within a range from about 10 milliseconds to about 100 milliseconds. The current flowing during this period is sufficiently smaller than the current flowing when the power supply voltage rises to 7 volts all at once. Thereafter, even if the power supply voltage level is raised to a high level normally used in the burn-in mode, a situation where a large current flows transiently in the semiconductor device can be avoided. In particular, when a large number of word lines of a semiconductor memory device are started up at a time, it is necessary to first pass a large current for boosting the word lines. As a result of the current peaks being dispersed, a situation where a large current flows transiently can be avoided.
[0062]
Also, in the case of a semiconductor device incorporating a substrate voltage generation circuit, if the operation of the semiconductor device is started by applying a power supply voltage, the substrate potential cannot be sufficiently controlled immediately after the operation starts, and the operation becomes unstable, and the CMOS Easy to cause latch-up. Such a problem is more likely to occur as the power supply voltage used is higher as in the burn-in inspection. However, according to the present embodiment, such a problem can be avoided because the power supply voltage is relatively lowered during an unstable operation period immediately after the start of the operation.
[0063]
The inspection according to the present embodiment is also executed using the probe card.
[0064]
In the probe card shown in FIG. 2, the localized anisotropic conductive rubber 23 is used to electrically connect the bumps to the multilayer wiring board. You may make a multilayer wiring board and a bump contact directly, without using. Conversely, if bumps are formed on the wafer to be measured, there is no need to form bumps on the probe card side. In that case, if the tip of the localized anisotropic conductive rubber 23 of the probe card is pressed against the bump on the wafer, wafer batch type measurement / inspection can be executed. Further, the wiring layer of the multilayer wiring board may be directly brought into contact with the bump on the wafer without using the localized anisotropic conductive rubber 23.
[0065]
【The invention's effect】
According to the semiconductor device and the inspection method of the present invention, even when a large number of chips operate during wafer batch measurement inspection, the operation start timing can be shifted for each semiconductor device. Thereby, the total value of the transient current peaks flowing through each chip is reduced. As a result, the current supply path on the probe card can avoid problems such as disconnection and short-circuit due to heat generated by a large current, and it is practical for performing burn-in inspection on a large number of chips using a wafer batch type probe card. Contribute greatly.
[0066]
According to another semiconductor device inspection method of the present invention, immediately after the start of burn-in inspection, the power supply voltage is boosted in two stages, so that transient current peaks flowing to the wafer after the start of inspection can be dispersed.
[Brief description of the drawings]
FIG. 1 is a perspective view for explaining a wafer batch type measurement / inspection technique.
FIG. 2 is a cross-sectional view showing configurations of a probe card, a wafer, and a wafer tray used in a wafer batch type measurement / inspection technique.
FIG. 3 is a cross-sectional view showing the relationship between a probe card, a wafer, and a wafer tray during measurement.
FIG. 4 is a diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention.
5 is a circuit diagram showing an internal configuration of a burn-in timer circuit and a synchronization signal generation circuit of FIG. 4;
FIG. 6 is a timing chart showing an output signal of the synchronization signal generation circuit.
FIG. 7 is a graph showing a time change of a power supply voltage applied in the semiconductor device measurement method according to the second embodiment of the present invention;
[Explanation of symbols]
1 Probe card
2 wafers (eg silicon wafers with a diameter of 200 mm)
3 Wafer tray
4 Seal ring
5 Vacuum valve
20 Probe card
21 multilayer wiring board
21a glass substrate
21b Electrode wiring
21c Interlayer insulating film
22 Bumped polyimide thin film
22a Polyimide thin film
22b Bump
23 Localized anisotropic conductive rubber
25 wafers
26 Pad electrode
28 Wafer tray
40 Self-refresh timer circuit
41 Timer circuit for burn-in
42 Self-burn-in signal terminal
43 Sync signal generation circuit
44 line address buffer
45 column address buffer
46 Refresh address counter
47 row address decoder
48 column address decoder
49 sense amplifier
50 memory cell array
51 RAS input circuit
52 CAS input circuit
53 Inverter circuit
54 NAND circuit
55 NAND circuit
56 Inverter circuit
57 NAND circuit
58 Inverter circuit
59 Inverter circuit

Claims (23)

Internal circuitry,
A burn-in timer circuit for generating a burn-in internal clock signal for the operation of the internal circuit in the burn-in mode;
Comprising a plurality of semiconductor devices ,
In each of the plurality of semiconductor devices, in the burn-in mode, the operation of the internal circuit is controlled in synchronization with the burn-in internal clock output from the burn-in timer circuit ,
The semiconductor device, wherein a cycle of the burn-in internal clock output from the burn-in timer circuit in each semiconductor device differs for each semiconductor device. Internal circuitry,
A terminal for receiving a self-burn-in signal;
A burn-in timer circuit for generating an internal clock signal required for the operation of the internal circuit when the self-burn-in signal input to the terminal indicates that the self-burn-in mode is in a self-burn-in mode;
A circuit for controlling the operation of the internal circuit in synchronization with the internal clock output from the burn-in timer circuit;
A control signal input circuit that externally supplies a signal necessary for the operation of the internal circuit to the internal circuit when the self-burn-in signal input to the terminal indicates that the self-burn-in mode is not in the self-burn-in mode;
Comprising a plurality of semiconductor devices ,
The semiconductor device characterized in that the cycle of the internal clock output from the burn-in timer circuit in each semiconductor device differs for each semiconductor device. A memory cell array;
An address decoder for selecting a memory cell from said memory cell array,
And a terminal for receiving a cell Rufuban'in signal,
A burn-in timer circuit for generating an internal clock signal when instructing that the self-burn-in signal input to the terminal electrode is in a self-burn-in mode;
An address counter that generates an address in synchronization with the internal clock output from the burn-in timer circuit and supplies the address to the address decoder;
An address input circuit for providing an address input from the outside to the address decoder when the self-burn-in signal input to the terminal indicates that the self-burn-in mode is not in the self-burn-in mode;
Comprising a plurality of semiconductor devices ,
The semiconductor device characterized in that the cycle of the internal clock output from the burn-in timer circuit in each semiconductor device differs for each semiconductor device.   4. The semiconductor device according to claim 3, wherein the burn-in timer circuit includes a ring oscillator circuit. A plurality of blocks comprising a plurality of semiconductor devices having internal circuits;
A plurality of burn-in timer circuits for generating a burn-in internal clock signal for the operation of the internal circuit in a burn-in mode provided for each block;
With
In each of the plurality of blocks, in the burn-in mode, the operation of the internal circuit of each semiconductor device is controlled in synchronization with the internal clock for burn-in output from the burn-in timer circuit,
The semiconductor device according to claim 1, wherein a period of the burn-in internal clock output from the burn-in timer circuit in each block is different for each block. The cycle of the internal clock output from the burn-in timer circuit in each semiconductor device differs from one semiconductor device to another due to variations in manufacturing process parameters. 4. The semiconductor device according to any one of 3. A method for measuring a semiconductor device according to claim 1, comprising:
A method for inspecting a semiconductor device, wherein a burn-in process is performed using the burn-in timer circuit. A method for measuring a semiconductor device according to claim 2, comprising:
Inputting a signal indicating that the self-burn-in mode is in the terminal, and causing the burn-in timer circuit to generate the internal clock signal;
Performing burn-in while operating the internal circuit in synchronization with the internal clock;
A method for inspecting a semiconductor device, comprising: A method for measuring a semiconductor device according to claim 3, comprising:
Inputting a signal indicating that the self-burn-in mode is in the terminal, and causing the burn-in timer circuit to generate the internal clock signal;
Performing the burn-in while generating the address in synchronization with the internal clock by the address counter and supplying the address to the address decoder;
A method for inspecting a semiconductor device, comprising: A semiconductor device inspection method for performing a burn-in inspection on a wafer including a plurality of semiconductor devices each having a burn-in timer circuit using a wafer collective inspection / measurement probe card,
Operating the burn-in timer circuit included in each semiconductor device in the wafer;
A step of performing burn-in of each semiconductor device while operating each semiconductor device in accordance with an internal clock signal output from the burn-in timer circuit;
Encompasses,
A method of inspecting a semiconductor device, wherein a cycle of the internal clock signal output from the burn-in timer circuit in each semiconductor device differs for each semiconductor device . A semiconductor device inspection method for performing a burn-in inspection on a wafer including a plurality of semiconductor devices using a wafer collective inspection / measurement probe card,
A plurality of burn-in timer circuits are formed in the wafer,
Operating the burn-in timer circuit;
Performing a burn-in of each semiconductor device while operating each of the plurality of semiconductor devices in accordance with any of the internal clock signals output from the plurality of burn-in timer circuits;
Encompasses,
A method for inspecting a semiconductor device, wherein a cycle of the internal clock signal output from each burn-in timer circuit is different for each semiconductor device . The probe card is a probe card for wafer batch type measurement / inspection comprising a plurality of probe electrodes arranged two-dimensionally and a multilayer wiring board electrically connected to the plurality of probe electrodes. 12. The method for inspecting a semiconductor device according to claim 10 or 11 , characterized in that: The semiconductor device inspection method according to claim 12, wherein the probe electrode is a bump electrode. 14. The semiconductor device inspection according to claim 13 , further comprising a conductive rubber for electrically connecting the probe electrode to the multilayer wiring board between the probe electrode and the multilayer wiring board. Method. 14. The method for inspecting a semiconductor device according to claim 13, wherein the probe electrode is formed on a thin film stretched in a state where tension is applied to the rigid ring. 13. The method of inspecting a semiconductor device according to claim 12, wherein the probe electrode is formed from at least a part of the wiring of the multilayer wiring board. 12. The semiconductor device according to claim 10, wherein a period of the internal clock signal output from each burn-in timer circuit differs for each semiconductor device due to variations in manufacturing process parameters. Inspection method. A method for inspecting a semiconductor device using a wafer batch type probe card,
When the power supply voltage is supplied to each chip included in the wafer to be measured, the first level voltage is supplied for a certain period immediately after the start of the burn-in inspection, and then the second level higher than the first level. A method for inspecting a semiconductor device, characterized in that a power supply voltage in a normal burn-in mode at a level of is supplied. The probe card is a probe card for wafer batch type measurement / inspection comprising a plurality of probe electrodes arranged two-dimensionally and a multilayer wiring board electrically connected to the plurality of probe electrodes. 11. The method for inspecting a semiconductor device according to claim 10 , wherein: 17. The semiconductor device inspection method according to claim 16, wherein the probe electrode is a bump electrode. 21. The semiconductor device inspection according to claim 20 , further comprising conductive rubber for electrically connecting the probe electrode to the multilayer wiring board between the probe electrode and the multilayer wiring board. Method. 21. The method of inspecting a semiconductor device according to claim 20, wherein the probe electrode is formed on a thin film stretched in a state where tension is applied to the rigid ring. 20. The method of inspecting a semiconductor device according to claim 19, wherein the probe electrode is formed from at least a part of the wiring of the multilayer wiring board.

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