JP3804582B2 - Gain control circuit and electronic volume circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a gain control circuit used in an audio system or the like and an electronic volume circuit having the gain control circuit.
[0002]
[Prior art]
An outline of the operation of the conventional gain control circuit in the zero cross mode will be described with reference to FIG. The conventional gain control circuit has a zero cross mode and a non-zero cross mode as operation modes. In FIG. 6, (A) is an input audio signal, (B) is a control signal CSN, (C) is volume data, and (D) is a volume value actually set in a volume adjusting unit (not shown). Setting volume value). Here, the input audio signal (FIG. 6A) is displayed by taking as an example a case where the signal level changes from large to small, such as a change from Fortissimo to Pianissimo, which is common in classical music and the like.
[0003]
Volume data is input to a storage unit (for example, a register) and stored and held during a period when the control signal CSN is at a low level.
In the conventional gain control circuit, in the non-zero cross mode, the set volume value is switched at the rise time of the control signal CSN, but in the zero cross mode, when the zero cross of the input audio signal is detected with reference to the rise time of the control signal CSN. Alternatively, when a zero cross is not detected, the set volume value is switched when a predetermined time elapses from the rising point of the control signal CSN (timeout by timer, set value Tout).
[0004]
As shown in FIG. 6, when the user operates the volume knob, the volume data corresponding to the operation amount is sequentially 0 dB, −3 dB, −6 dB in the period when the control signal CSN indicating the operation timing is at the low level. , −9 dB, −12 dB, and −15 dB to the storage unit and stored (FIG. 6B).
On the other hand, since the input audio signal zero-crosses at times t1 and t2 (FIG. 6A), the volume value set in the volume adjustment unit is switched to 0 dB at time t1 and −3 dB at time t2 (FIG. 6 ( D)).
[0005]
However, the input audio signal continues to be in a state where no zero cross is detected after time t2. Since a very small DC offset voltage (Δ) is inevitably added to the input signal level, zero crossing does not occur when the input audio signal level decreases. Under this state, volume data is input as -6 dB, -9 dB, -12 dB, and -15 dB (t3, t4, t5, tn), but a new data is input before the timer value becomes Tout, so a timeout occurs. Therefore, the volume value set in the volume adjustment unit remains at −3 dB and does not change. Since new data is not input until the timer value reaches Tout after the time tn when −15 dB is input, the time-out occurs at time t (n + 1), and the volume data of −15 dB is set as a volume value in the volume adjustment unit. . Accordingly, at the time t (n + 1), the set volume value changes rapidly from -3 dB to -15 dB.
[0006]
[Problems to be solved by the invention]
In the above-described conventional gain control circuit, in the zero cross mode, a timer is started at the time of rising of the control signal CSN, and the volume is set at a time interval shorter than the time interval from this point to the time point at which a predetermined time has elapsed. When data is input to the storage unit, the volume data in the meantime is ignored, and the last input is made to the storage unit when the zero cross of the input audio signal is detected or the timer times out. In order for the volume data to be set as the volume data to be set in the volume adjusting unit by the zero crossing of the input audio signal or the time-out of the timer as the newly set volume data, the set volume value changes greatly. Sudden changes in noise I, a problem that it is easy to appear there.
[0007]
The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a gain control circuit and an electronic volume circuit that can prevent the occurrence of noise even when volume data is continuously input. And
[0008]
[Means for Solving the Problems]
In order to achieve the above object, the invention described in claim 1 detects a zero cross of an input audio signal and outputs a zero cross detection signal at the time of the zero cross, and a sound volume for setting an input sound volume. Storage means for storing setting data; and control means for reading the volume setting data stored in the storage means when the zero cross detection signal is input and outputting the volume data for adjusting the volume of the input audio signal; The control means captures the detection output of the zero cross detection means, and when new volume setting data is input to the storage means within a waiting period until the zero cross of the input audio signal is detected , is input to the storage means immediately before the new volume setting data is inputted by the input timing, storage Reading volume setting data which is, and outputs the the sound volume setting data as the volume data.
[0009]
According to a second aspect of the present invention, in the gain control circuit according to the first aspect of the present invention, a timer that is activated when the volume setting data is input to the storage unit and times out when a predetermined time elapses is provided. The control means captures the timer output, until the timer does not time out and the input audio signal does not zero cross until the zero cross of the input audio signal is detected When the new volume setting data is input to the storage means within the waiting period, the stored volume setting data is read and input to the storage means immediately before the new volume setting data is input. The volume setting data is output as the volume data.
[0010]
According to a third aspect of the present invention, the gain control circuit according to the first or second aspect is provided.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Prior to the description of the embodiment of the present invention, an outline of the operation of the gain control circuit according to the present invention will be described with reference to FIG. In FIG. 7, as in FIG. 6, (A) is the input audio signal, (B) is the control signal CSN, (C) is the volume data, and (D) is actually set in the volume adjuster (not shown). Volume value (set volume value). Here too, the input audio signal is displayed as an example in which the signal level changes from large to small, such as from Fortissimo to Pianissimo.
[0012]
As shown in FIG. 7, when the user operates the volume knob, the volume data corresponding to the operation amount is sequentially 0 dB, -3 dB, -6 dB during the period when the control signal CSN indicating the input timing is at the low level. , −9 dB, −12 dB, −15 dB, −18 dB, and −21 dB are stored in the storage unit (FIGS. 7B and 7C).
On the other hand, since the input audio signal zero-crosses at times t10 and t11 (FIG. 7A), the volume value set in the volume adjustment unit is switched to 0 dB at time t10 and to -3 dB at time t11 (FIG. 7 ( D)).
[0013]
Further, the input audio signal continues in a state where zero crossing is not detected after time t11. Under this condition, the volume data is input as -6 dB, -9 dB, -12 dB, -15 dB, -18 dB, and -21 dB. However, since new data is input before the timer value becomes Tout, There is no switching of value settings.
However, in the gain control circuit according to the present invention, the volume value set in the volume adjustment unit is input immediately before the volume data is input while waiting for the detection of zero crossing. The set volume value is switched by the volume data thus set (t12, t13, t14, t15, t16).
[0014]
Therefore, every time the control signal CSN is output, the set volume value is changed from −3 dB → −6 dB → −9 dB → −12 dB → −15 dB → −18 dB until time t16 before the timer expires. And auditory noise can be suppressed. The set volume value is switched when the timer times out, as in the conventional example (t18).
[0015]
Next, the configuration of an audio system to which the present invention is applied is shown in FIG. In the figure, an audio system includes an electronic volume circuit 1, an input buffer circuit 2, a power amplifier 3, a speaker 4, a rotary encoder 5 as a volume operation unit, a control unit 6 that controls each unit, and a control unit. And a display unit 7 for displaying various data under the control of 6.
[0016]
In the above configuration, an audio signal is input to the electronic volume circuit 1 via the input buffer 2, and the audio signal whose volume level is adjusted by the electronic volume circuit 1 is power amplified by the power amplifier 3 and output from the speaker 4.
When the user operates a volume knob (not shown), a signal for setting the volume level is output from the rotary encoder 5 to the control unit 6 according to the operation amount. The control unit 6 outputs volume data for setting the volume level based on the signal input by the rotary encoder 5 and various control signals including a clock to the electronic volume circuit 1.
[0017]
The electronic volume circuit 1 adjusts the audio signal Vin to a volume corresponding to the input volume data and outputs the signal Vout to the power amplifier 3 based on the volume data input from the control unit 6 and various control signals. .
[0018]
Next, a specific configuration of the electronic volume circuit 1 in FIG. 1 is shown in FIG. In FIG. 2, for the sake of convenience of explanation, the configuration for only one channel is shown, but it is usually configured according to the required number of channels. In FIG. 2, the electronic volume circuit according to this embodiment includes an attenuator 110 for attenuating an audio signal input from the input terminal 100, a gain setting unit 112 for setting the gain of an amplifier 114, and an input audio signal. Volume data for actually adjusting the volume is output based on the volume setting data input from the amplifier 114 to be amplified, the zero cross detection circuit 116, the oscillator 118, and the S / P (serial / parallel) conversion register 124. A control unit 120, decoders 122 and 126, and an S / P conversion register 124 are provided.
[0019]
The attenuator 110 and the gain setting unit 112 constitute a volume adjustment unit.
The zero cross detection circuit 116 has a function of detecting a zero cross of an audio signal input from the input terminal 100 and outputting a zero cross detection signal ZERO.
The oscillator 118 generates a clock ZCLK for time measurement of a timer (not shown) that times out when a zero cross of the input audio signal cannot be detected within a certain time.
The decoder 122 can designate four operation modes including a zero cross mode by a 2-bit setting signal input from the terminals 230 and 232. In the present embodiment, it is assumed that the zero cross mode is designated.
[0020]
The S / P conversion register 124 is a register that takes in the volume setting data SDATAI that is serial data in synchronization with the clock SCLK and converts it into 8-bit parallel data.
In the above configuration, the control unit 120 outputs an enable signal ENBL that enables the zero-cross detection circuit 116 and the oscillator 118 to be operable based on various control signals to the zero-cross detection circuit 116 and the oscillator 118, and according to the volume setting data SDATAI. The obtained volume data is output to the decoder 126.
[0021]
Based on the input volume data, the decoder 126 sets the attenuation of the input audio signal and the gain of the amplifier 114 to the specified values for the attenuator 110 and the gain setting unit 112. As a result, the audio signal Vin input from the input terminal 100 is adjusted to a volume based on the volume data output from the control unit 120, and the output signal Vout is output from the output terminal 102 via the amplifier 114.
[0022]
Next, FIG. 3 shows the configuration of the gain control circuit in the electronic volume circuit shown in FIG. In the figure, the gain control circuit includes an S / P conversion register 124, a first register 130 that holds volume data output from the S / P conversion register 124, and volume data held in the first register 130. And a second register 132, a mask register (MASK) 134, a NAND gate 136, a pulse generation circuit 138, a counter 140, an initial mask circuit 142, a selector 144, and an RS flip-flop 146. is doing. Each of the first register 130, the second register 132, and the mask register 134 is composed of a flip-flop for 8 bits.
[0023]
The control signal CSN is input from the input terminal 204 to the clock terminal of the first register, the input terminal of the pulse generation circuit, and the reset terminal of the counter 140.
The pulse generation circuit 138 generates pulse signals CCK1 and CCK2 based on the control signal CSN.
The counter 140 is reset by the pulse signal CCK1, counts the clock ZCLK input from the input terminal 206, and outputs a time-out signal TCK when the count value reaches a count value corresponding to a time-out time. Function.
[0024]
The initial mask circuit 142 is a circuit that masks the initial output of the detection output ZERO of the zero cross detection circuit 116 (FIG. 2) input from the input terminal 208.
The selector 144 functions as a logical sum element because it is set to the zero cross mode by the operation mode designation signal MODE input from the input terminal 210.
[0025]
The signal output from the selector 144 is supplied to the clock terminal of the second register 132 as a clock signal VOLCK for rewriting the volume data stored and held in the second register 132, and the RS flip-flop 146. Is supplied as a reset signal to the reset terminal.
The RS flip-flop 146 is set by the pulse signal CCK1 output from the pulse generation circuit 138, reset by the signal output from the selector 144, and enabled to the zero-cross detection circuit 116 and the oscillator 118 shown in FIG. The signal ENBL is output.
[0026]
The mask register 134 normally holds the volume data held in the second register 132 as it is and outputs it to the output terminal 214, but all the 8-bit data held by the second register 132 is “1”. In this case, a reset signal is output to the mask register 134 via the NAND gate 136, and the 8-bit output of the mask register 134 is all “0”, so that the volume is reduced. The zero cross detection circuit 116 is a zero cross detection means, the first register 130 and the second register 132 are storage means of the present invention, a pulse generation circuit 138, a counter 140, an initial mask circuit 142, a selector 144, and an RS flip-flop 146. Each corresponds to the control means of the present invention.
[0027]
The operation of the gain control circuit having the above configuration will be described with reference to the timing chart shown in FIG. In the above configuration, the S / P conversion register 124 is
Volume setting data SDATAI (FIG. 4C), which is serial data input from the input terminal 200 in synchronization with the clock SCLK (FIG. 4B), is taken in and converted into 8-bit parallel data.
The 8-bit parallel data converted and held by the S / P conversion register 124 is sent to the first register 130 using the control signal CSN as a clock (specifically, DATA1 at the rising edge of the control signal CSN at time t101). However, DATA2 is stored and held at the rise of the control signal CSN at time t103.
[0028]
In addition, the pulse signal CCK1 generated by the pulse generation circuit 138 is output in synchronization with the rising edge of the control signal CSN, and the pulse signal CCK2 is output in synchronization with the falling edge of the control signal CSN (FIGS. 4D and 4D). E)). At time t101, the pulse signal CCK1 is output from the pulse generation circuit 138 to the RS flip-flop 146 and the counter 140. The counter 140 that counts the timeout period is reset. The enable signal ENBL (FIG. 4H) is output from the RS flip-flop 146 to the zero cross detection circuit 116 and the oscillator 118 shown in FIG. As a result, the clock ZCLK for counting the timeout period is input to the counter 140 from the input terminal 206, and the timeout counting is started.
Also, the zero cross detection circuit 116 becomes operable and starts zero cross detection.
[0029]
Assume that zero crossing is not detected and the next volume setting data DATA2 is input before the timeout counter 140 reaches the value of Tout (the signals TCK and ZCK are not output to the selector 144).
At time t102, the control signal CSN falls, and the pulse signal CCK2 is output from the pulse generation circuit 138 to the selector 144. The pulse signal CCK2 becomes the output signal of the selector 144 and outputs VOLCK. This VOLCK is output as a clock to the clock terminal of the second register 132 and as a reset signal to the reset terminal of the RS flip-flop 146.
[0030]
Due to this VOLCK (FIG. 4I), DATA1 previously held in the first register 130 is transferred to the second register 132 and stored / held. Further, since the enable signal ENBL becomes low level at time t102 (FIG. 4H), the operations of the zero cross detection circuit 116 and the oscillator 118 are stopped. DATA1 held in the second register 132 is output to the output terminal 214 via the mask register 134 as volume data. When the control signal CSN rises at time t103, DATA2 is stored and held in the first register 130. When the pulse signal CCK1 is output at time t103, the counter 140 that measures the timeout time is reset.
[0031]
When the pulse signal CCK1 rises at time t104, the enable signal ENBL rises (FIG. 4H), the oscillator 118 and the zero cross detection circuit 116 become operable, and the output of the clock ZCK is started from the oscillator 118. . The counter 140 starts counting, and the zero cross detection circuit 116 starts zero cross detection.
[0032]
Thereafter, when the zero crossing of the input audio signal is not detected and no new volume data is input, and the count content of the counter 140 that counts the timeout period reaches a set value at time t105, A time-out signal TCK is output from the counter 140 (FIG. 4F), and output from the selector 144 as VOLCK. This VOLCK is output as a clock to the second register 132 and as a reset signal to the reset terminal of the RS flip-flop 146. As a result, DATA2 is transferred to and stored in the second register 132, and the enable signal ENBL becomes low level. Therefore, DATA 2 is output as volume data from the output terminal 214 via the mask register 134.
[0033]
In the conventional gain control circuit, even when the next volume setting data DATA2 is input at time t102 to t103, the set volume value is not replaced.
That is, a signal corresponding to the clock signal VOCLK for rewriting data in the second register 132 is not output at time t102 in FIG. For example, it is as shown in FIG. 4 (I) VOCLK (old). What is stored and held in the second register (corresponding to 132) remains DATA1.
[0034]
That is, as shown in FIG. 5, DATA1 and DATA2 are written in the first register 130 at times t101 and t103, respectively, in both the conventional example and the present invention, but the second register 132 is written in time in the conventional example. Whereas DATA2 is written at t105, in the present invention, DATA1 is written at time t103, and then DATA2 is written at time t105.
[0035]
According to the gain control circuit of this embodiment, even when volume data is continuously input to the register group as the storage unit, the set volume value that is actually output to the volume adjustment unit is switched in stages. Therefore, it is possible to prevent audible noise caused by a sudden change in the set volume value.
In addition, according to the electronic volume circuit having the gain control circuit, even when volume data is continuously input, the set volume value that is actually output to the volume adjustment unit is output so as to be switched in stages. Therefore, it is possible to prevent the generation of audible noise due to a sudden change in the set volume value.
[0036]
【The invention's effect】
According to the gain control circuit of the present invention, even when volume data is continuously input, the set volume value that is actually output to the volume adjusting unit is output so as to be switched in stages. It is possible to prevent the generation of auditory noise due to a sudden change in value.
According to the electronic volume circuit of the present invention, since the gain control circuit is provided, even when volume data is continuously input, the set volume value that is actually output to the volume adjustment unit is switched in stages. Therefore, it is possible to prevent audible noise caused by a sudden change in the set volume value.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of an audio system to which the present invention is applied.
FIG. 2 is a block diagram showing a specific configuration of an electronic volume circuit in the audio system shown in FIG.
3 is a block diagram showing a configuration of a gain control circuit according to an embodiment of the present invention in the electronic volume circuit shown in FIG. 2;
4 is a timing chart showing an operating state of the gain control circuit according to the embodiment of the present invention shown in FIG. 3;
FIG. 5 is an explanatory diagram showing an operation of the gain control circuit according to the embodiment of the present invention in comparison with a conventional example.
FIG. 6 is an explanatory diagram showing an outline of the operation of a conventional gain control circuit.
FIG. 7 is an explanatory diagram showing an outline of the operation of the gain control circuit according to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Electronic volume circuit, 110 ... Attenuator, 112 ... Gain setting part, 114 ... Amplifier, 116 ... Zero cross detection circuit, 118 ... Oscillator, 120 ... Control part, 122, 126 ... Decoder, 124 ... S / P conversion register, DESCRIPTION OF SYMBOLS 130 ... 1st register, 132 ... 2nd register, 134 ... Mask register, 138 ... Pulse generation circuit, 140 ... Counter, 142 ... Initial mask circuit, 144 ... Selector, 146 ... RS flip-flop

Claims (3)

Zero-cross detection means for detecting a zero-cross of the input audio signal and outputting a zero- cross detection signal at the time of the zero-cross ,
Storage means for storing volume setting data for setting the input volume;
Control means for reading the volume setting data stored in the storage means when the zero cross detection signal is input and outputting the volume data for adjusting the volume of the input audio signal;
Wherein said control means captures the detection output of said zero-cross detection means, said at input new volume setting data within the waiting period until the zero crossing of the audio signal is detected is input to the storage means, the new volume A gain control circuit that reads the stored volume setting data that is input to the storage means immediately before the setting data is input, and outputs the volume setting data as the volume data. And a timer that is activated when the volume setting data is input to the storage unit and times out when a predetermined time elapses.
The control means captures the timer output, and waits until a zero cross of the input audio signal is detected in a state where the timer does not time out and the input audio signal does not zero cross. When new volume setting data is input to the storage means, the volume setting data input to and stored in the storage means immediately before the new volume setting data is input is read and the volume setting data is read. The gain control circuit according to claim 1, wherein data is output as the volume data.   An electronic volume circuit comprising the gain control circuit according to claim 1.

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