JP3808935B2 - Information recording / reproducing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an information recording / reproducing apparatus, and more particularly to an information recording / reproducing apparatus suitable for speeding up information recording or reproduction.
[0002]
[Prior art]
Conventionally, an information recording / reproducing apparatus (for example, a magnetic disk apparatus, an optical disk apparatus, or the like) connected to a host computer or a personal computer (hereinafter referred to as a host) via an interface (for example, a SCSI interface or an IDE interface) It is used for recording or reproducing information such as program data and image data on an information recording medium (for example, a magnetic disk, an optical disk, etc.).
[0003]
In such an information recording / reproducing apparatus, a cache memory is provided in the information recording / reproducing apparatus in order to speed up data access from the host, that is, data read processing or write processing, and the cache memory is managed by software. In general, a configuration in which read data or write data is written in the cache memory and data is transferred between the host and the information recording / reproducing apparatus is generally used. Such a cache memory is mounted not only on a magnetic disk device or an optical disk device but also on a CD-ROM device or the like, and contributes to an increase in data access speed.
[0004]
Examples of the system using the cache memory as described above include a configuration disclosed in Japanese Patent Application Laid-Open No. 62-58351.
[0005]
[Problems to be solved by the invention]
However, recently, the processing speed on the host side has been considerably increased, but the access speed of the information recording / reproducing apparatus is not sufficient, and the speed according to the processing speed on the host side is simply provided with a cache memory. In some cases, improvement cannot be obtained. For this reason, there is an increasing demand for further speeding up of the information recording / reproducing apparatus.
[0006]
The present invention has been made in view of these circumstances, and can further increase the access speed to the cache memory, and can transfer data between the host and the recording medium at a high speed. It is an object of the present invention to provide an information recording / reproducing apparatus capable of speeding up the recording or reproducing process.
[0007]
[Means for Solving the Problems]
  According to the inventionFirstAn information recording / reproducing apparatus includes a cache memory for temporarily storing data transferred between a host that is a host computer and a recording medium, a bit search circuit for searching for valid data in the cache memory, A cache memory, the bit search circuit, and a processor for controlling data transfer between the host and the recording medium, wherein the bit search circuit searches for data in the cache memory from an arbitrary position according to an instruction from the processor. Have the ability toIn addition, the bit search circuit searches for a continuous number of logic 1 or 0 in data composed of a plurality of bits, and a designated bit position register for storing bit position data for starting the bit search; A data holding register for holding data to be subjected to bit search, a search calculation circuit for performing bit search calculation, and a search calculation result register for storing bit search calculation results, wherein the search calculation circuit includes: In addition, based on the information in the designated bit position register, a continuous number of logic 1 or 0 is searched from an arbitrary bit position of the data holding register.
A second information recording / reproducing apparatus according to the present invention searches a cache memory for temporarily storing data transferred between a host, which is a host computer, and a recording medium, and valid data in the cache memory. A bit search circuit for controlling the data transfer between the cache memory, the bit search circuit, and the host and the recording medium, the bit search circuit in the cache memory according to an instruction from the processor The bit search circuit searches for the number of consecutive 1s or 0s in the data composed of a plurality of bits, and starts the bit search. The specified bit position register that stores the bit position data to be executed and the data to be subjected to bit search A data holding register to hold, a search calculation circuit for performing a bit search calculation, and a search calculation result register for storing a bit search calculation result, wherein the search calculation circuit is an arbitrary pointed to by the designated bit position register An arbitrary position bit search function for performing a search for the continuous number of logical 1 or 0 of the data in the data holding register from the bit position of the data, and the continuous number of logical 1 or 0 obtained by this search and the designated bit position Logical continuity for determining whether logical 1 or 0 in data in the data holding register is continuous to the least significant bit (LSB) or the most significant bit (MSB) based on the value in the register And a determination function.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
1 to 14 relate to an embodiment of the present invention, FIG. 1 is a block diagram showing a schematic configuration of an information recording / reproducing apparatus, and FIG. 2 is an explanatory diagram schematically showing a correspondence relationship between a cache memory and a flag register. 3 is a block diagram showing the overall configuration of the bit search circuit, FIG. 4 is an explanatory diagram showing the ranking of bits of each register of the FLAG module, FIG. 5 is a circuit diagram showing the circuit configuration of each bit of the FLAG module, and FIG. Is an explanatory diagram showing allocation of each bit of the SET register, FIG. 7 is an operation explanatory diagram showing a truth table of outputs of the SET register and the MASK module, FIG. 8 is a circuit diagram of a circuit configuration of a SERCH operation module, and FIG. FIG. 10 is an operation explanatory view showing a truth table of the output of the ENCODE module with respect to the result of the arithmetic module, and FIG. 10 is a circuit configuration of the COMP module. FIG. 11 is an explanatory diagram showing the allocation of each bit of the STATUS register, FIG. 12 is a circuit diagram showing the circuit configuration of each bit of the STATUS register, and FIG. 13 is a timing chart showing the operation of the bit search circuit. 14 is a flowchart showing a bit search operation in this embodiment.
[0009]
In the present embodiment, a configuration example of a disk recording / reproducing apparatus for recording / reproducing data on / from a disk-shaped medium is shown as an example of an information recording / reproducing apparatus. Examples of the disk-shaped medium include a magnetic recording medium such as a hard disk, a magneto-optical recording medium such as a magneto-optical disk, and an optical recording medium such as an optical disk and a CD-ROM.
[0010]
The information recording / reproducing apparatus includes a disk control device 2 that is connected to a host 1 such as a host computer or a personal computer and performs various controls of a disk device 3 that performs recording / reproduction with respect to a medium. The disk control device 2 includes a processor 5 responsible for the control sequence of the device, a ROM 4 in which microcode for operating the processor 5 is stored in advance, a cache memory 9 for temporarily storing write data and read data, Host interface control unit 6 that exchanges data with host 1 via an interface such as a SCSI bus, data transfer control unit 7 that accesses cache memory 9, and data writing to disk device 3 The drive interface control unit 8 that performs modulation and demodulation of data accompanying reading and positioning of the disk in the disk device 3 and logic corresponding to the address of valid data in the cache memory 9 at the time of data writing or reading Installed in processor 5 where “1” is stored A bit search circuit 10 for searching the bit of a flag register that is, is configured to include a.
[0011]
In the information recording / reproducing apparatus having such a configuration, data transfer between the host 1 and the recording medium of the disk device 3 is performed via the cache memory 9. The cache memory 9 is managed by the processor 5 in the disk controller 2. That is, in this information recording / reproducing apparatus, the data writing operation to the disk device 3 or the data reading operation from the disk device 3 is not directly performed by the host 1 and is controlled by the processor 5 in the disk control device 2. It is like that.
[0012]
During a write operation for writing data to the disk device 3, the processor 5 in the disk control device 2 once writes the data sent from the host 1 in the free area of the cache memory 9. Then, the data in the cache memory 9 is written into the recording medium by the processor 5 using the free time of the control sequence of the disk device 3.
[0013]
Further, when writing to the cache memory 9, the processor 5 sets a logical “1” in a flag register that has a one-to-one relationship with the address of the cache memory 9 that is written at the same time as data is written. By doing so, the processor 5 completes the writing in the cache memory 9 by searching for “1” of the logic of the flag register even when a certain amount of time has elapsed from the time when the data was written to the cache memory 9. Data that is not available can be retrieved, and only valid data in the cache memory 9 can be written to the recording medium. This flag register is provided in a memory area or the like in the processor 5.
[0014]
During a read operation for reading data from the disk device 3, the processor 5 in the disk control device 2 searches the cache memory 9, reads the cache hit data from the cache memory 9, and passes it to the host 1. At the time of this search, the processor 5 checks whether or not the data desired by the host 1 has a cache hit by checking the logic “1” of the flag register for the address of the data requested from the host 1 on the cache memory 9. It is possible to determine whether or not the requested data can be transferred quickly.
[0015]
FIG. 2 shows the correspondence between the address of the cache memory 9 and the flag register. In the flag register, a cache segment is divided for each address section of the cache memory, and is allocated to a memory area such as the processor 5 as a plurality of words. In the example of FIG. 2, cache segments of 8 bits each are divided and assigned as flag A, flag B, flag C,.
[0016]
For example, when valid data is stored in the address indicated by hatching in FIG. 2 in the cache memory 9, a logical “1” is set in the bit of the corresponding flag register.
[0017]
Such address search of the cache memory 9 must rely on logical search of each bit of the flag register (hereinafter referred to as bit search). In this embodiment, this bit search is realized by the bit search circuit 10. That is, a search for an empty area in the cache memory 9 during the write operation, a determination as to whether or not the data in the cache memory 9 has been written, and a determination as to whether or not the data in the cache memory 9 has been hit during the read operation. When performing the above, a bit search is performed by the bit search circuit 10 and an address search of the cache memory 9 is executed.
[0018]
The configuration and operation of the bit search circuit 10 in this embodiment will be described below. FIG. 3 shows the overall configuration of the bit search circuit 10. The bit search circuit 10 includes 10 modules of a FLAG module 11, a SERCH calculation module 12, a SET register 13, a MASK module 14, an ENCODE module 15, a SUB module 16, a COMP module 17, a STATUS register 18, a MODE module 19, and a SEQ module 20. It consists of functional modules. The bit search circuit 10 is configured by hardware inside or outside the processor 5.
[0019]
The FLAG module 11 is a data holding register that holds data to be subjected to bit search, and is configured by a 32-bit register in this example. The number of bits is not limited to 32 bits, but may be set to other values depending on the system configuration and the bit width desired by the user (that is, the bit width of the flag register).
[0020]
The FLAG module 11 is connected to, for example, a data bus 21 of a host processor (processor 5 or the like). The FLAG module 11 is configured as four 8-bit registers including FLAG registers a to d, and has a structure in which data can be taken in via a 16-bit data bus 21. The outputs of the FLAG registers a to d are also connected to the data bus 21 and are addressed so that the output value of the FLAG module 11 can be read by the host processor.
[0021]
Also, as shown in FIG. 4, the registers a to d of the FLAG module 11 are prioritized in bits. That is, it is assumed that the MSB bit (most significant bit) of the FLAG register a is positioned as the MSB bit of the entire FLAG module 11, and the order is assigned to the LSB bit (least significant bit) of the FLAG register d in order.
[0022]
A circuit configuration of each bit of the FLAG module 11 is shown in FIG. Here, 31 which is the MSB bit of the FLAG register a in FIG. 4 corresponds to the flag 31 surrounded by the one-dot chain line in FIG. Each bit of the FLAG module 11 has the following three functions.
[0023]
[1] A function of loading a value on the data bus 21 of each processor into each bit in synchronization with the write strobe signal ("WE" in FIG. 5) of the processor 5.
[0024]
[2] Bit search calculation end pulse (“END” in FIG. 5) and search result signal SER [31: 0] output from SERCH calculation module 12 described later (X [31: 0 in the description and drawings) ] Is synchronized with each output when the AND (AND) gate output with X31, X30,..., X0) and the SEL1 output of the MODE module 19 described later becomes “1”. A function that clears the flip-flop of each bit.
For example, in the case of the flag 31, the flip-flop is cleared by the AND result of the bit search calculation end pulse END and the search result signal SER31.
[0025]
[3] A function of selecting whether to output the flip-flop output of each bit with positive logic or with negative logic according to the state of the SEL2 output of the MODE module 19 described later.
[0026]
The output of each bit of the FLAG module 11 is input to the SERCH calculation module 12 described later as DATA31 to DATA0.
[0027]
FIG. 6 shows the configuration of the SET register 13 which is a designated bit position register for storing bit position data for starting a bit search. The SET register 13 is connected to the data bus 21 of the host processor, and is configured so that values on the data bus 21 can be loaded. The SET register 13 is composed of a 5-bit register in which bits D0 to D4 are allocated in order from the LSB bit. The reason why the SET register 13 is 5 bits is that the FLAG module 11 of the present embodiment is composed of 32 bits, and is not necessarily 5 bits. Accordingly, it may be configured with an appropriate number of bits.
[0028]
FIG. 7 shows a truth table corresponding to each output of the MASK module 14 that receives the SET register 13 and the outputs SET4 to SET0 of the SET register 13 and generates a mask signal to be input to the SERCH calculation module 12. .
[0029]
For example, when a bit search from the 20th bit of the FLAG module 11 is to be performed, the value of “14H” (xxH represents a hexadecimal number) in which the decimal number 20 is represented in hexadecimal in the SET register 13 in advance. You can write it. As a result, the outputs MASK31 to MASK0 of the MASK module 14 become "FFE00000H" from FIG. 7, and this mask signal is reflected in the SERCH calculation module 12 described later. Note that the MASK module 14 is realized by a combinational circuit based on the truth table of FIG. 7, but a detailed description of the circuit configuration is omitted here.
[0030]
FIG. 8 shows a circuit configuration of the SERCH calculation module 12. DATA31 to DATA0 in the figure are outputs of the respective bits of the FLAG module 11, and MASK31 to MASK0 are outputs of the MASK module 14 described above.
[0031]
For example, when it is desired to perform a bit search from the 20th bit of the FLAG module 11, the output of the MASK module 14 is “FFE00000H” as described above, and the DATA 31 to DATA 21 by the OR (logical sum) gate in the SERCH calculation module 12. Is masked by “1”, and the outputs SER31 to SER21 of the SERCH calculation module 12 are forcibly set to “1”.
[0032]
Further, the outputs SER30 to SER0 of the SERCH operation module 12 of the 20th bit or less of the FLAG module 11 are all "0" after the bit in which the value of the FLAG register becomes "0". This calculation is performed by an AND gate in the SERCH calculation module 12. In this embodiment, the search direction is from the MSB direction of the FLAG module 11, but it may be from the LSB direction depending on the circuit configuration.
[0033]
FIG. 9 shows a truth table of the ENCODE module 15 which is a combinational circuit that receives the output of the SERCH calculation module 12 and determines how many logic “1” s are present in the FLAG module 11.
[0034]
For example, the outputs SER31 to SER0 of the SERCH calculation module 12 are
1111 1111 1111 1111 0000 0000 0000 0000
In this case, the output of the ENCODE module 15 is “10H”. The ENCODE module 15 is realized by a combinational circuit based on the truth table of FIG. 9, but a detailed description of the circuit configuration is omitted here.
[0035]
The SUB module 16 provided on the output side of the ENCODE module 15 is a circuit for subtracting the output of the ENCODE module 15 and the inverted output of the SET register 13 or subtracting the output of the ENCODE module 15 and the fixed value “1FH”. It is. These subtractions are switched based on the SEL1 output of the MODE module 19. The MODE module 19 includes a 3-bit register and is connected to the data bus 21 so that a value can be written from a host processor.
[0036]
When the SEL1 output of the MODE module 19 is “1”, the inverted output of the SET register 13 is subtracted from the output of the ENCODE module 15. This is an operation for determining how many logical “1” s from the designated bit position of the FLAG module 11 are continuous.
[0037]
When the SEL1 output of the MODE module 19 is “0”, the output value of the ENCODE module 15 is subtracted from the fixed value “1FH”. This is an operation for detecting at which bit position the logic “1” is set for the first time when a bit search is performed from the MSB bit of the FLAG module 11.
[0038]
FIG. 10 is a circuit that receives the outputs ANS5 to ANS0 of the SUB module 16 and detects that logical "1" continues from the designated bit position of the FLAG module 11 to the LSB bit based on the result of the bit search operation. The structure of the COMP module 17 is shown.
[0039]
In the figure, the output value of the SET register 13 is input to the D2 input, and the output of the SUB module 16 is input to the D1 input. When it is detected that logical “1” continues from the designated bit position of the FLAG module 11 to the LSB bit of the FLAG module 11, the output CMP of the COMP module 17 becomes “1”.
[0040]
FIGS. 11 and 12 show the configuration of the STATUS register 18 which is a search calculation result storage register for taking in the output CMP of the COMP module 17, the bit search calculation end pulse END, and the outputs ANS5 to ANS0 of the SUB module 16. It is. FIG. 11 shows the assignment of each bit of the STATUS register 18, and FIG. 12 shows the circuit configuration of each bit of the STATUS register 18.
[0041]
The STATUS register 18 is an 8-bit register. In the STATUS register 18, bit S7 is a search calculation end bit indicating the end of the search calculation, and S6 is detected that logical "1" continues from the designated bit position of the FLAG module 11 to the LSB bit. Is a “1” continuous detection bit. Further, S5 to S0 are outputs ANS5 to ANS0 of the SUB module 16, which is a logical “1” continuous number from the designated bit position of the FLAG module 11 or a logical “from the MSB bit of the FLAG module 11”. This corresponds to a start bit position of 1 ″. The host processor can know the bit search calculation result by monitoring the search calculation end bit.
[0042]
The MODE module 19 is a 3-bit register that stores a search mode of a bit search operation and a start instruction. The output Q1 (START) of the MODE module 19 is a search calculation start bit for instructing the start of the search calculation, and the calculation is started when the upper processor writes “1” to this bit. The output Q2 (SEL1) of the MODE module 19 is a subtraction switching bit for switching the subtraction of the SUB module 16. The output Q3 (SEL2) of the MODE module 19 is a search switching bit for switching the logic “1” search or the logic “0” search in the FLAG module 11. When the value of SEL2 is “1”, a bit search of logic “1” in the FLAG module 11 is performed. When the value of SEL2 is “0”, a bit search of logic “0” in the FLAG module 11 is performed. carry out.
[0043]
The SEQ module 20 is a sequencer dedicated to bit search operation. When START of the output of the MODE module 19 becomes “1”, a pulse CLR that clears all the STATUS registers 18 is output first. After a certain period of time, a bit search calculation end pulse END is output to the STATUS register 18 and the FLAG module 11. The START bit of the MODE module 19 is cleared by the bit search calculation end pulse END.
[0044]
In the bit search circuit 10, an arbitrary position bit for performing a bit search from an arbitrary bit position of the FLAG module 11 by each of the SERCH operation module 12, the SET register 13, the MASK module 14, the ENCODE module 15, and the SUB module 16 A search function block 31 is configured. Further, the COMP module 17 and the STATUS register 18 constitute a logical continuity determination function block 32 for determining whether or not the logic “1” or “0” in the FLAG module 11 that has performed the bit search is continuous to the LSB. Is done. Further, the FLAG module 11 has a bit clear function for clearing only the bit positions where the logic “1” or “0” in the FLAG module 11 in which the bit search is performed as described above.
[0045]
Next, as an operation of the bit search circuit 10, a bit search calculation example will be described in detail. FIG. 13 shows a timing chart of the bit search described below.
[0046]
As an example of the bit search, the bit search calculation when the following value is set in the FLAG module 11 will be described in order.
FLAG: 0000 1111 1111 0000 0000 1111 0000 0000 (0FF00F00H)
MSB side LSB side
[0047]
(1) First, as a first calculation example, an operation when a bit search is performed from the MSB of the FLAG module 11 to know the bit position of the first logic “1” will be described.
[0048]
The SET register 13 is set to perform a bit search from “1FH”, that is, the 31st bit. Further, the SEL2 bit of the MODE module 19 is set to “0”, and the SEL1 bit is set to “0”.
[0049]
In the above state, the output of each module of the bit search circuit 10 when the bit search is started is sequentially shown.
[0050]
Since the output of the FLAG module 11 is the detection of logic “0” from SEL2 = 0, the output is inverted as follows.
FLAG output: 1111 0000 0000 1111 1111 0000 1111 1111 (F00FF0FFH)
[0051]
The outputs SER31 to SER0 of the SERCH calculation module 12, the output of the ENCODE module 15, and the outputs ANS5 to ANS0 of the SUB module 16 are as follows. At this time, the SUB module 16 subtracts the output value of the ENCODE module 15 from the fixed value “1FH” from SEL1 = 0.
SERCH output: 1111 0000 0000 0000 0000 0000 0000 0000 (F0000000H)
ENCODE output: 000100 (04H, 4 consecutive “1” s)
SUB output: 011011
(The first “1” is detected in the 27th bit of the 1BH and FLAG module 11)
[0052]
The outputs ANS5 to ANS0 of the SUB module 16 and the output CMP of the COMP module 17 are taken into the STATUS register 18, and data of the start bit position of the logic "1" in the FLAG module 11 is held.
[0053]
After completion of the bit search calculation, the FLAG module 11 clears the flip-flop of each bit according to the AND result of the bit search calculation end pulse END and the outputs SER31 to SER0 of the SERCH calculation module 12. However, in this case, even if the above bit search operation is completed, the FLAG module 11 is not cleared from 31 bits to 28 bits. This is because SEL1 is set to “0”. Therefore, the output of the FLAG module 11 after completion of the bit search operation is as follows.
FLAG output: 1111 0000 0000 1111 1111 0000 1111 1111 (F00FF0FFH)
[0054]
(2) Next, as a second calculation example, an operation when a bit search is performed from an arbitrary bit position of the FLAG module 11 to know the number of consecutive bits of logic “1” will be described.
[0055]
The SET register 13 is set to perform a bit search from “1BH”, that is, the 27th bit. This is the first logical “1” bit position detected in the bit search from the MSB. Further, the SEL2 bit of the MODE module 19 is set to “1”, and the SEL1 bit is set to “1”.
[0056]
In the above state, the output of each module of the bit search circuit 10 when the bit search is started is sequentially shown.
[0057]
The output of the FLAG module 11 is as follows because the logic “1” is detected from SEL2 = 1.
FLAG output: 0000 1111 1111 0000 0000 1111 0000 0000 (0FF00F00H)
[0058]
The inputs of the SERCH calculation module 12 are as follows for D1 and D2.
SERCHD1 input:
0000 1111 1111 0000 0000 1111 0000 0000 (0FF00F00H)
SERCHD2 input:
1111 0000 0000 0000 0000 0000 0000 0000 (F0000000H)
[0059]
Here, since the D2 input is the output of the MASK module 14 and the SET register 13 is set to “1BH”, the outputs MASK31 to MASK28 of the MASK module 14 are all “1”, and the SERCH calculation module of FIG. The OR circuit outputs from the 31st bit to the 28th bit in 12 are all “1”.
[0060]
Accordingly, the outputs SER31 to SER0 of the SERCH calculation module 12 and the output of the ENCODE module 15 are as follows.
SERCH output: 1111 1111 1111 0000 0000 0000 0000 0000 (FFF00000H)
ENCODE output: 001100 (0CH, 12 consecutive “1”)
[0061]
In the SUB module 16, the inverted output of the SET register 13 is subtracted from the output value of the ENCODE module 15 from SEL1 = 1. That is,
001100−00100 (inversion of “1BH”) = 001000
Thus, the outputs ANS5 to ANS0 of the SUB module 16 are as follows.
SUB output: 001000 (08H, 8 consecutive "1")
[0062]
The COMP module 17 compares the output of the SET register 13 with the output of the SUB module 16. In this case, the output value of the SUB module 16 is not equal to 1CH (28) which is the value of the output value +1 of the SET register 13, that is, 28 “1” s are not consecutive from the 27th bit of the FLAG module 11. The output CMP of the COMP module 17 is “0”.
COMP output: 0
[0063]
The outputs ANS5 to ANS0 of the SUB module 16 and the output CMP of the COMP module 17 are taken into the STATUS register 18, and the continuous number of data of logic "1" in the FLAG module 11 is held.
[0064]
After completion of the bit search calculation, the FLAG module 11 clears the flip-flop of each bit according to the AND result of the bit search calculation end pulse END and the outputs SER31 to SER0 of the SERCH calculation module 12. That is, when the above bit search operation is completed, the FLAG module 11 is cleared from 31 bits to 20 bits and the output is as follows. This is because SEL1 is set to “1”.
FLAG output: 0000 0000 0000 0000 0000 1111 0000 0000 (00000F00H)
[0065]
Thereafter, the bit search is performed again from the MSB to execute the calculation for obtaining the bit position of the first logic “1”. Thereafter, the bit search calculation is repeated until the bit of the logic “1” of the FLAG module 11 is eliminated.
[0066]
The operation of the bit search circuit 10 that performs the bit search operation as described above will be described with reference to FIG. The control of each part of the bit search circuit 10 is performed by the processor 5 which is a host processor.
[0067]
First, in step S1, the processor 5 sends the data of the 32-bit segment among the data stored in the flag register assigned to the memory area of the processor 5 or the like to the FLAG module 11 via the data bus 21. set.
[0068]
In step S2, a bit search of the FLAG module 11 is performed by a bit search operation similar to that described in (1) above. That is, the SERCH calculation module 12, the ENCODE module 15, and the SUB module 16 perform a calculation to detect the bit position of the first logic “1” by performing a bit search from the MSB of the FLAG module 11.
[0069]
After the end of the first bit search operation, in step S3, it is determined whether or not the logic “1” is detected in the FLAG module 11. If detected, the process proceeds to S4, and the logic detected in the SET register 13 is detected. Set the data at the bit position of “1”. If no logic “1” is detected in the FLAG module 11 in step S3, the process is terminated.
[0070]
Next, in step S5, a bit search of the FLAG module 11 is performed by a bit search operation similar to that described in (2) above. That is, the SERCH operation module 12, the ENCODE module 15, and the SUB module 16 execute an operation for detecting the number of consecutive bits of logic “1” by performing a bit search from the detected logic “1” bit position of the FLAG module 11. Start.
[0071]
After the end of the second bit search operation, in step S6, only the bit position where the logic “1” detected in the FLAG module 11 is continuous is cleared. At this time, the cleared data of the FLAG module 11 is overwritten on the corresponding segment of the flag register.
[0072]
In step S7, the COMP module 17 and the STATUS register 18 determine whether or not the detected logic "1" bit of the FLAG module 11 continues to the LSB. After the start bit position of the logic “1” in the current FLAG module 11 and the continuous number of data of the logic “1” are saved from the STATUS register 18 to the memory area in the processor 5, the process proceeds to step S8. Data of the next 32-bit segment of the flag register is set in the module 11 via the data bus 21. At the same time, the MSB bit position data of the FLAG module 11 is set in the SET register 13.
[0073]
Thereafter, the process returns to step S5, the second bit search operation is executed in steps S5 to S7, and the operations of steps S5 to S8 are performed until the detected logic "1" bit of the FLAG module 11 does not continue to LSB. repeat.
[0074]
When the detected logic “1” bit of the FLAG module 11 is not continuous up to LSB in step S7, the process proceeds to step S9, and the cache memory 9 corresponding to the bit of the flag register in which logic “1” is detected. The data at the corresponding address is transferred to the host 1 or the disk device 3. Thereafter, the process returns to step S1 and the above operation is repeated until the logic "1" is not detected in the FLAG module 11.
[0075]
In the present embodiment, the following points are improved by performing a bit search as shown in the flowchart of FIG.
[0076]
First, by enabling bit search from an arbitrary bit position, there is no need for search from the MSB in the second bit search calculation (step S5 in FIG. 14) of the FLAG module 11, and processing time Is shortened. In the conventional configuration, the start position of the bit search is determined to be a fixed position such as the MSB, and search time is wasted, and access between the processor and the cache memory may take time.
[0077]
Second, by determining whether or not the bit of logic “1” of the FLAG module 11 continues to LSB (step S7 in FIG. 14), in the bit search operation over a plurality of times of the FLAG module 11, that is, the flag register Since it is possible to determine the continuity of logic “1” between the plurality of segments, the data in the cache memory 9 corresponding to the bits straddling the plurality of segments of the flag register is read continuously, It becomes possible to write to the recording medium of the disk device 3 or transfer it to the host 1. In the conventional configuration, when valid data in the cache memory spans multiple segments of the flag register, it is necessary to read in multiple times, and in the case of a disk-shaped recording medium, wait for one cycle. The processing time may be increased because the processing continues from the beginning.
[0078]
Third, after the execution of the second bit search operation (step S5 in FIG. 14) of the FLAG module 11, only the bit position where the logic “1” in the FLAG module 11 is continuous is cleared in step S6. Therefore, it is not necessary for the processor to clear the flag register by software, and the processing time is further shortened. In the conventional configuration, the processor clears the flag register bit by bit by a bit clear command or the like by software, so that processing takes time.
[0079]
As described above, by providing the bit search circuit 10 having the above configuration in an information recording / reproducing apparatus such as a magneto-optical disk apparatus, the bit search operation can be performed more quickly, and the following effects can be obtained. Can bring in. In other words, since the bit search can be performed from an arbitrary position, it is possible to eliminate the waste of search time and to shorten the access time to the cache memory. In addition, it is possible to detect the continuity of logic “1” between a plurality of segments of the flag register, that is, to detect the continuity of valid data between the plurality of segments of the flag register. Write time and data read time from the cache memory can be shortened. In addition, since the bit search circuit performs the bit clear of the flag register by hardware instead of software, the access time to the cache memory can be shortened.
[0080]
From the above points, the processing time of the system can be further shortened.
[0081]
[Appendix]
(1) The bit search circuit searches for a continuous number of logic 1 or 0 in data composed of a plurality of bits, and a designated bit position register for storing bit position data for starting a bit search; A data holding register that holds data to be subjected to bit search, a search calculation circuit that performs bit search calculation, and a search calculation result register that stores a bit search calculation result,
The data holding register has a bit clear function for resetting or presetting only the bit positions where the logic 1 or 0 of the data holding register is continuous when the search operation by the search operation circuit is completed. The information recording / reproducing apparatus according to claim 1.
[0082]
【The invention's effect】
As described above, according to the present invention, the access speed to the cache memory can be further increased, and data transfer between the host and the recording medium can be performed at a high speed. As a result, information is recorded or reproduced. There is an effect that the processing can be further speeded up.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of an information recording / reproducing apparatus according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram schematically showing a correspondence relationship between a cache memory and a flag register.
FIG. 3 is a block diagram showing the overall configuration of the bit search circuit of the present embodiment.
FIG. 4 is an explanatory diagram showing the ranking of bits in each register of the FLAG module.
FIG. 5 is a circuit diagram showing a circuit configuration of each bit of the FLAG module.
FIG. 6 is an explanatory diagram showing the assignment of each bit of the SET register.
FIG. 7 is an operation explanatory view showing a truth table of outputs of the SET register and the MASK module.
FIG. 8 is a circuit diagram showing a circuit configuration of a SERCH operation module.
FIG. 9 is an operation explanatory diagram showing a truth table of the output of the ENCODE module with respect to the result of the SERCH calculation module.
FIG. 10 is a circuit diagram showing a circuit configuration of a COMP module.
FIG. 11 is an explanatory diagram showing allocation of each bit of the STATUS register.
FIG. 12 is a circuit diagram showing a circuit configuration of each bit of the STATUS register.
FIG. 13 is a timing chart showing the operation of the bit search circuit of this embodiment.
FIG. 14 is a flowchart showing a bit search operation in the present embodiment.
[Explanation of symbols]
1 ... Host
2 ... Disk controller
3. Disk unit
5 ... Processor
7. Data transfer control unit
9 ... Cache memory
10: Bit search circuit
11 ... FLAG module
12 ... SERCH calculation module
13 ... SET register
14 ... MASK module
15 ... ENCODE module
16 ... SUB module
17 ... COMP module
18 ... STATUS register
19 ... MODE module
20 ... SEQ module
21 ... Data bus
31 ... Arbitrary position bit search function block
32 ... Logical continuity determination function block

Claims (2)

A cache memory for temporarily storing data transferred between a host, which is a host computer, and a recording medium, a bit search circuit for searching for valid data in the cache memory, the cache memory, and the bit search A circuit and a processor for controlling data transfer between the host and the recording medium,
The bit search circuit, the data in the cache memory have a function for searching an arbitrary position in accordance with an instruction from the processor,
Further, the bit search circuit searches for a continuous number of logic 1 or 0 in data composed of a plurality of bits, a designated bit position register for storing bit position data for starting a bit search, and a bit A data holding register for holding data to be searched, a search calculation circuit for performing a bit search calculation, and a search calculation result register for storing a bit search calculation result,
The information recording / reproducing apparatus according to claim 1, wherein the search operation circuit searches for a continuous number of logic 1 or 0 from an arbitrary bit position of the data holding register based on information in the designated bit position register . A cache memory for temporarily storing data transferred between a host, which is a host computer, and a recording medium, a bit search circuit for searching for valid data in the cache memory, the cache memory, and the bit search A circuit and a processor for controlling data transfer between the host and the recording medium,
The bit search circuit has a function of searching data in the cache memory from an arbitrary position in accordance with an instruction from the processor,
Further, the bit search circuit searches for a continuous number of logic 1 or 0 in data composed of a plurality of bits, a designated bit position register for storing bit position data for starting a bit search, and a bit A data holding register for holding data to be searched, a search calculation circuit for performing a bit search calculation, and a search calculation result register for storing a bit search calculation result,
The search operation circuit performs an arbitrary position bit search function for performing a search for a continuous number of logical 1 or 0 of data in the data holding register from an arbitrary bit position indicated by the designated bit position register, and obtained by this search. The logic 1 or 0 in the data in the data holding register is the least significant bit (LSB) or the most significant bit (MSB) based on the consecutive number of logic 1 or 0 and the value in the designated bit position register. And a logical continuity determination function for determining whether or not it is continuous .

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